fond
Model Checking Contest 2026
16th edition, Hamburg, Germany, June 23, 2026
Execution of r364-tall-178024404400101
Last Updated
Jun 17, 2026

About the Execution of TY for SupplyChain-PT-00002

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
636.523 11374.00 37954.00 35.30 ? normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2026-input.r364-tall-178024404400101.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2026-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5973
Executing tool TY
Input is SupplyChain-PT-00002, examination is ReachabilityDeadlock
Time confinement is 1800 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r364-tall-178024404400101
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 448K
-rw-r--r-- 1 mcc users 6.7K May 27 07:38 CTLCardinality.txt
-rw-r--r-- 1 mcc users 72K May 27 07:38 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.7K May 27 07:38 CTLFireability.txt
-rw-r--r-- 1 mcc users 53K May 27 07:38 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.6K May 27 10:56 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K May 27 10:56 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K May 27 10:56 LTLFireability.txt
-rw-r--r-- 1 mcc users 20K May 27 10:56 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 May 26 18:17 NewModel
-rw-r--r-- 1 mcc users 9.2K May 27 07:38 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 97K May 27 07:38 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.6K May 27 07:38 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 87K May 27 07:38 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K May 27 10:56 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K May 27 10:56 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 26 18:17 equiv_col
-rw-r--r-- 1 mcc users 6 May 26 18:17 instance
-rw-r--r-- 1 mcc users 6 May 26 18:17 iscolored
-rw-r--r-- 1 mcc users 9.1K May 26 18:17 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

FORMULA_NAME ReachabilityDeadlock

=== Now, execution of the tool begins

BK_START 1780305946470

FORMULA ReachabilityDeadlock CANNOT_COMPUTE TECHNIQUES EXPLICIT BFS STRUCTURAL TOPOLOGICAL PARTIAL_ORDER

BK_STOP 1780305957844

--------------------
content from stderr:

TY MCC
Host: mcc2026
BK_TOOL: TY
Input: /home/mcc/execution
Examination: ReachabilityDeadlock
Threads: 4
Storage: /tmp/ty-mcc-storage
Fingerprint set backend: cas
Backend evidence: /tmp/ty-mcc-storage/backend-capability.jsonl
auto-sized (FingerprintOnly): 30 places (24 packed, 8B exact) × 1B/place max = 56B/state → primary_capacity=360047385 state_limit=unbounded
ReachabilityDeadlock: PDR phase exceeded 5s wall cap; abandoning
AIGER encoding: 31 latches, 19 transitions, 1 constraints
preprocess: latches 31->31->22 inputs 19->19->19 gates 317->317->188 clauses 957->579 const_elim=0 scorr_elim=9(iters=2) frts_elim=1 bve_elim=0 frts_bve_iters=2 rewrite_elim=0 dag_rewrite_elim=1 refactor_elim=0 synthesis(rounds=2,gates=-2,depth=-0) ternary=0 ternary_sim=0 renumber=180
Compaction: max_var 234->234 (0% reduction)
IC3: 22 latches, 19 inputs, 1 constraints, 31 init_clauses, 579 trans_clauses, 1 bad (trans/latch: 26.3x, constraint/latch: 0.0x, consec_verify: 18446744073709551615, crosscheck_disabled: false, predprop: false)
IC3 depth=1 lemmas=[0] total=0 inf=0
IC3 depth=1 blocked=0 natural_exit=true
IC3: 22 latches, 19 inputs, 1 constraints, 31 init_clauses, 579 trans_clauses, 1 bad (trans/latch: 26.3x, constraint/latch: 0.0x, consec_verify: 18446744073709551615, crosscheck_disabled: false, predprop: false)
IC3 depth=1 lemmas=[0] total=0 inf=0
IC3 depth=1 blocked=0 natural_exit=true
IC3 depth=2 lemmas=[0, 0] total=0 inf=0
IC3: 22 latches, 19 inputs, 1 constraints, 31 init_clauses, 579 trans_clauses, 1 bad (trans/latch: 26.3x, constraint/latch: 0.0x, consec_verify: 18446744073709551615, crosscheck_disabled: false, predprop: false)
IC3: 22 latches, 19 inputs, 1 constraints, 31 init_clauses, 579 trans_clauses, 1 bad (trans/latch: 26.3x, constraint/latch: 0.0x, consec_verify: 18446744073709551615, crosscheck_disabled: false, predprop: false)
IC3 depth=1 lemmas=[0] total=0 inf=0
IC3 depth=1 blocked=0 natural_exit=true
IC3 depth=2 lemmas=[0, 0] total=0 inf=0
IC3: 22 latches, 19 inputs, 1 constraints, 31 init_clauses, 579 trans_clauses, 1 bad (trans/latch: 26.3x, constraint/latch: 0.0x, consec_verify: 18446744073709551615, crosscheck_disabled: false, predprop: false)
IC3 depth=1 lemmas=[0] total=0 inf=0
IC3 depth=1 blocked=0 natural_exit=true
IC3 depth=2 lemmas=[0, 0] total=0 inf=0
IC3: 22 latches, 19 inputs, 1 constraints, 31 init_clauses, 579 trans_clauses, 1 bad (trans/latch: 26.3x, constraint/latch: 0.0x, consec_verify: 18446744073709551615, crosscheck_disabled: false, predprop: false)
IC3 depth=1 lemmas=[0] total=0 inf=0
IC3 depth=1 blocked=0 natural_exit=true
IC3 depth=2 lemmas=[0, 0] total=0 inf=0
IC3 depth=2 lemmas=[0, 0] total=0 inf=0
IC3: 22 latches, 19 inputs, 1 constraints, 31 init_clauses, 579 trans_clauses, 1 bad (trans/latch: 26.3x, constraint/latch: 0.0x, consec_verify: 18446744073709551615, crosscheck_disabled: false, predprop: false)
IC3 depth=1 lemmas=[0] total=0 inf=0
IC3 depth=1 blocked=0 natural_exit=true
IC3: 22 latches, 19 inputs, 1 constraints, 31 init_clauses, 579 trans_clauses, 1 bad (trans/latch: 26.3x, constraint/latch: 0.0x, consec_verify: 18446744073709551615, crosscheck_disabled: false, predprop: false)
IC3 depth=2 lemmas=[0, 0] total=0 inf=0
IC3 depth=1 lemmas=[0] total=0 inf=0
IC3 depth=1 blocked=0 natural_exit=true
IC3 depth=1 lemmas=[0] total=0 inf=0
IC3: 22 latches, 19 inputs, 1 constraints, 31 init_clauses, 579 trans_clauses, 1 bad (trans/latch: 26.3x, constraint/latch: 0.0x, consec_verify: 18446744073709551615, crosscheck_disabled: false, predprop: false)
IC3 depth=1 lemmas=[0] total=0 inf=0
IC3 depth=1 blocked=0 natural_exit=true
IC3 depth=2 lemmas=[0, 0] total=0 inf=0
IC3: 22 latches, 19 inputs, 1 constraints, 31 init_clauses, 579 trans_clauses, 1 bad (trans/latch: 26.3x, constraint/latch: 0.0x, consec_verify: 18446744073709551615, crosscheck_disabled: false, predprop: false)
IC3 depth=1 lemmas=[0] total=0 inf=0
IC3 depth=1 blocked=0 natural_exit=true
IC3 depth=2 lemmas=[0, 0] total=0 inf=0
IC3: 22 latches, 19 inputs, 1 constraints, 31 init_clauses, 579 trans_clauses, 1 bad (trans/latch: 26.3x, constraint/latch: 0.0x, consec_verify: 18446744073709551615, crosscheck_disabled: false, predprop: false)
IC3 depth=1 lemmas=[0] total=0 inf=0
IC3 depth=1 blocked=0 natural_exit=true
IC3 depth=2 lemmas=[0, 0] total=0 inf=0
IC3: 22 latches, 19 inputs, 1 constraints, 31 init_clauses, 579 trans_clauses, 1 bad (trans/latch: 26.3x, constraint/latch: 0.0x, consec_verify: 18446744073709551615, crosscheck_disabled: false, predprop: false)
IC3 depth=1 lemmas=[0] total=0 inf=0
IC3 depth=1 blocked=0 natural_exit=true
IC3 depth=2 lemmas=[0, 0] total=0 inf=0
IC3: 22 latches, 19 inputs, 1 constraints, 31 init_clauses, 579 trans_clauses, 1 bad (trans/latch: 26.3x, constraint/latch: 0.0x, consec_verify: 18446744073709551615, crosscheck_disabled: false, predprop: false)
IC3 depth=1 lemmas=[0] total=0 inf=0
IC3 depth=1 blocked=0 natural_exit=true
IC3 depth=2 lemmas=[0, 0] total=0 inf=0
IC3 depth=1 blocked=0 natural_exit=true
IC3 depth=2 lemmas=[0, 0] total=0 inf=0
IC3 depth=2 lemmas=[0, 0] total=0 inf=0
IC3: 22 latches, 19 inputs, 1 constraints, 31 init_clauses, 579 trans_clauses, 1 bad (trans/latch: 26.3x, constraint/latch: 0.0x, consec_verify: 18446744073709551615, crosscheck_disabled: false, predprop: false)
IC3 depth=1 lemmas=[0] total=0 inf=0
IC3 depth=1 blocked=0 natural_exit=true
IC3 depth=2 lemmas=[0, 0] total=0 inf=0
IC3 depth=2 bad cube repeated 11 times (cube_len=22) — advancing to next depth (#4139)
IC3 depth=2 blocked=23 natural_exit=false
IC3 depth=3 lemmas=[0, 15, 0] total=15 inf=0
lift: ternary prefilter removed 5/22 state lits
lift: ternary prefilter removed 5/22 state lits
lift: ternary prefilter removed 6/22 state lits
lift: ternary prefilter removed 6/22 state lits
lift: ternary prefilter removed 5/22 state lits
lift: ternary prefilter removed 7/22 state lits
lift: ternary prefilter removed 5/22 state lits
lift: ternary prefilter removed 5/22 state lits
lift: ternary prefilter removed 14/22 state lits
lift: ternary prefilter removed 14/22 state lits
lift: ternary prefilter removed 14/22 state lits
lift: ternary prefilter removed 14/22 state lits
lift: ternary prefilter removed 14/22 state lits
lift: ternary prefilter removed 14/22 state lits
ReachabilityDeadlock: AIGER phase exceeded 3s wall cap; abandoning
CAS parallel dedup folds u128 fingerprints to u64 without a payload guard; refusing exact observer dispatch
lift: ternary prefilter removed 14/22 state lits
lift: ternary prefilter removed 14/22 state lits
lift: ternary prefilter removed 14/22 state lits
lift: ternary prefilter removed 14/22 state lits
lift: ternary prefilter removed 14/22 state lits
lift: ternary prefilter removed 14/22 state lits
lift: ternary prefilter removed 14/22 state lits
lift: ternary prefilter removed 14/22 state lits
lift: ternary prefilter removed 14/22 state lits
lift: ternary prefilter removed 14/22 state lits
lift: ternary prefilter removed 14/22 state lits
lift: ternary prefilter removed 14/22 state lits
lift: ternary prefilter removed 14/22 state lits
IC3 depth=2 bad cube repeated 11 times (cube_len=22) — advancing to next depth (#4139)
IC3 depth=2 blocked=23 natural_exit=false
lift: ternary prefilter removed 14/22 state lits
IC3 depth=3 lemmas=[0, 15, 0] total=15 inf=0
lift: ternary prefilter removed 14/22 state lits
lift: ternary prefilter removed 14/22 state lits
lift: ternary prefilter removed 7/22 state lits
lift: ternary prefilter removed 5/22 state lits
lift: ternary prefilter removed 5/22 state lits
lift: ternary prefilter removed 14/22 state lits
lift: ternary prefilter removed 14/22 state lits
lift: ternary prefilter removed 14/22 state lits
lift: ternary prefilter removed 14/22 state lits
lift: ternary prefilter removed 14/22 state lits
lift: ternary prefilter removed 14/22 state lits
lift: ternary prefilter removed 14/22 state lits
lift: ternary prefilter removed 14/22 state lits
lift: ternary prefilter removed 14/22 state lits
lift: ternary prefilter removed 14/22 state lits
lift: ternary prefilter removed 14/22 state lits
lift: ternary prefilter removed 14/22 state lits
lift: ternary prefilter removed 14/22 state lits
lift: ternary prefilter removed 14/22 state lits
lift: ternary prefilter removed 14/22 state lits
lift: ternary prefilter removed 14/22 state lits
lift: ternary prefilter removed 14/22 state lits
lift: ternary prefilter removed 14/22 state lits
lift: ternary prefilter removed 14/22 state lits
lift: ternary prefilter removed 14/22 state lits
lift: ternary prefilter removed 14/22 state lits
lift: ternary prefilter removed 14/22 state lits
lift: ternary prefilter removed 7/22 state lits
lift: ternary prefilter removed 6/22 state lits
lift: ternary prefilter removed 6/22 state lits
lift: ternary prefilter removed 7/22 state lits
lift: ternary prefilter removed 5/22 state lits
lift: ternary prefilter removed 8/22 state lits
IC3 depth=2 bad cube repeated 11 times (cube_len=22) — advancing to next depth (#4139)
IC3 depth=2 blocked=11 natural_exit=false
IC3 depth=3 lemmas=[0, 32, 0] total=32 inf=0
lift: ternary prefilter removed 16/22 state lits
lift: ternary prefilter removed 17/22 state lits
lift: ternary prefilter removed 18/22 state lits
lift: ternary prefilter removed 16/22 state lits
lift: ternary prefilter removed 14/22 state lits
lift: ternary prefilter removed 14/22 state lits
lift: ternary prefilter removed 14/22 state lits
lift: ternary prefilter removed 14/22 state lits
lift: ternary prefilter removed 14/22 state lits
lift: ternary prefilter removed 14/22 state lits
lift: ternary prefilter removed 14/22 state lits
lift: ternary prefilter removed 14/22 state lits
lift: ternary prefilter removed 14/22 state lits
lift: ternary prefilter removed 14/22 state lits
lift: ternary prefilter removed 14/22 state lits
lift: ternary prefilter removed 14/22 state lits
lift: ternary prefilter removed 14/22 state lits
lift: ternary prefilter removed 14/22 state lits
lift: ternary prefilter removed 14/22 state lits
lift: ternary prefilter removed 14/22 state lits
lift: ternary prefilter removed 14/22 state lits
lift: ternary prefilter removed 14/22 state lits
lift: ternary prefilter removed 14/22 state lits
lift: ternary prefilter removed 14/22 state lits
lift: ternary prefilter removed 14/22 state lits
lift: ternary prefilter removed 14/22 state lits
lift: ternary prefilter removed 14/22 state lits
lift: ternary prefilter removed 5/22 state lits
lift: ternary prefilter removed 5/22 state lits
lift: ternary prefilter removed 6/22 state lits
lift: ternary prefilter removed 6/22 state lits
lift: ternary prefilter removed 5/22 state lits
BMC(step=10): depth=10/50000 vars=2584 latches=22 elapsed=2.7s rate=0depth/s
BMC(step=10): depth=10/50000 vars=2584 latches=22 elapsed=2.9s rate=0depth/s
IC3 domain stats: consecution(restricted=79 fallback=0 rate=100.0%) mic(restricted=85 fallback=0 rate=100.0%) avg_coverage=83.7%
IC3 consecution stats: queries=79 unsat=27 sat=51 unknown=1 verified=0 rejected=0 reject_rate=0.0% domain_restricted=79 full_solver=0
IC3 domain stats: consecution(restricted=124 fallback=0 rate=100.0%) mic(restricted=176 fallback=0 rate=100.0%) avg_coverage=76.3%
IC3 consecution stats: queries=124 unsat=64 sat=60 unknown=0 verified=0 rejected=0 reject_rate=0.0% domain_restricted=124 full_solver=0
IC3 domain stats: consecution(restricted=7 fallback=0 rate=100.0%) mic(restricted=44 fallback=0 rate=100.0%) avg_coverage=76.4%
IC3 consecution stats: queries=7 unsat=4 sat=3 unknown=0 verified=0 rejected=0 reject_rate=0.0% domain_restricted=7 full_solver=0
IC3 domain stats: consecution(restricted=122 fallback=0 rate=100.0%) mic(restricted=184 fallback=0 rate=100.0%) avg_coverage=76.4%
IC3 drop_po stats: 2 POs dropped (threshold=20.0)
IC3 consecution stats: queries=122 unsat=62 sat=60 unknown=0 verified=0 rejected=0 reject_rate=0.0% domain_restricted=122 full_solver=0
IC3 domain stats: consecution(restricted=161 fallback=0 rate=100.0%) mic(restricted=223 fallback=0 rate=100.0%) avg_coverage=75.9%
IC3 drop_po stats: 3 POs dropped (threshold=20.0)
IC3 consecution stats: queries=161 unsat=81 sat=80 unknown=0 verified=0 rejected=0 reject_rate=0.0% domain_restricted=161 full_solver=0
IC3 domain stats: consecution(restricted=58 fallback=0 rate=100.0%) mic(restricted=82 fallback=0 rate=100.0%) avg_coverage=75.8%
IC3 drop_po stats: 1 POs dropped (threshold=20.0)
IC3 consecution stats: queries=58 unsat=29 sat=29 unknown=0 verified=0 rejected=0 reject_rate=0.0% domain_restricted=58 full_solver=0
IC3 domain stats: consecution(restricted=264 fallback=0 rate=100.0%) mic(restricted=185 fallback=0 rate=100.0%) avg_coverage=75.2%
IC3 drop_po stats: 3 POs dropped (threshold=20.0)
IC3 consecution stats: queries=264 unsat=56 sat=208 unknown=0 verified=0 rejected=0 reject_rate=0.0% domain_restricted=264 full_solver=0
IC3 domain stats: consecution(restricted=44 fallback=0 rate=100.0%) mic(restricted=66 fallback=0 rate=100.0%) avg_coverage=81.2%
IC3 consecution stats: queries=44 unsat=19 sat=25 unknown=0 verified=0 rejected=0 reject_rate=0.0% domain_restricted=44 full_solver=0
IC3 domain stats: consecution(restricted=102 fallback=0 rate=100.0%) mic(restricted=150 fallback=0 rate=100.0%) avg_coverage=75.9%
IC3 drop_po stats: 1 POs dropped (threshold=20.0)
IC3 consecution stats: queries=102 unsat=52 sat=50 unknown=0 verified=0 rejected=0 reject_rate=0.0% domain_restricted=102 full_solver=0
IC3 domain stats: consecution(restricted=29 fallback=0 rate=100.0%) mic(restricted=60 fallback=0 rate=100.0%) avg_coverage=77.8%
IC3 consecution stats: queries=29 unsat=8 sat=21 unknown=0 verified=0 rejected=0 reject_rate=0.0% domain_restricted=29 full_solver=0
IC3 domain stats: consecution(restricted=63 fallback=0 rate=100.0%) mic(restricted=86 fallback=0 rate=100.0%) avg_coverage=82.2%
IC3 consecution stats: queries=63 unsat=25 sat=38 unknown=0 verified=0 rejected=0 reject_rate=0.0% domain_restricted=63 full_solver=0
IC3 domain stats: consecution(restricted=63 fallback=0 rate=100.0%) mic(restricted=94 fallback=0 rate=100.0%) avg_coverage=76.2%
IC3 drop_po stats: 1 POs dropped (threshold=20.0)
IC3 consecution stats: queries=63 unsat=32 sat=31 unknown=0 verified=0 rejected=0 reject_rate=0.0% domain_restricted=63 full_solver=0
IC3 domain stats: consecution(restricted=142 fallback=0 rate=100.0%) mic(restricted=85 fallback=0 rate=100.0%) avg_coverage=75.9%
IC3 drop_po stats: 2 POs dropped (threshold=20.0)
IC3 consecution stats: queries=142 unsat=72 sat=70 unknown=0 verified=0 rejected=0 reject_rate=0.0% domain_restricted=142 full_solver=0

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="SupplyChain-PT-00002"
export BK_EXAMINATION="ReachabilityDeadlock"
export BK_TOOL="TY"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="1800"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5973"
echo " Executing tool TY"
echo " Input is SupplyChain-PT-00002, examination is ReachabilityDeadlock"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r364-tall-178024404400101"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/SupplyChain-PT-00002.tgz
mv SupplyChain-PT-00002 execution
cd execution
if [ "ReachabilityDeadlock" = "ReachabilityDeadlock" ] || [ "ReachabilityDeadlock" = "UpperBounds" ] || [ "ReachabilityDeadlock" = "QuasiLiveness" ] || [ "ReachabilityDeadlock" = "StableMarking" ] || [ "ReachabilityDeadlock" = "Liveness" ] || [ "ReachabilityDeadlock" = "OneSafe" ] || [ "ReachabilityDeadlock" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityDeadlock" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityDeadlock" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityDeadlock.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityDeadlock.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "ReachabilityDeadlock" = "ReachabilityDeadlock" ] || [ "ReachabilityDeadlock" = "QuasiLiveness" ] || [ "ReachabilityDeadlock" = "StableMarking" ] || [ "ReachabilityDeadlock" = "Liveness" ] || [ "ReachabilityDeadlock" = "OneSafe" ] ; then
echo "FORMULA_NAME ReachabilityDeadlock"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;