Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2026-input.r198-tall-177969916700770.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2026-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5973
Executing tool TY
Input is PGCD-COL-D03N050, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r198-tall-177969916700770
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 436K
-rw-r--r-- 1 mcc users 7.1K Mar 8 14:38 CTLCardinality.txt
-rw-r--r-- 1 mcc users 79K Mar 8 14:38 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.9K Mar 8 14:37 CTLFireability.txt
-rw-r--r-- 1 mcc users 59K Mar 8 14:37 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.7K Mar 17 06:58 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K Mar 17 06:58 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.0K Mar 17 06:58 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Mar 17 06:58 LTLFireability.xml
-rw-r--r-- 1 mcc users 8.2K Mar 8 14:39 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 83K Mar 8 14:39 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.7K Mar 8 14:38 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 83K Mar 8 14:38 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Mar 17 06:58 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Mar 17 06:58 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 3 18:30 equiv_pt
-rw-r--r-- 1 mcc users 8 Mar 3 18:30 instance
-rw-r--r-- 1 mcc users 5 Mar 3 18:30 iscolored
-rw-r--r-- 1 mcc users 11K Mar 3 18:30 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

echo here is the order used to build the result vector(from xml file)
FORMULA_NAME PGCD-COL-D03N050-CTLFireability-2024-00
FORMULA_NAME PGCD-COL-D03N050-CTLFireability-2024-01
FORMULA_NAME PGCD-COL-D03N050-CTLFireability-2024-02
FORMULA_NAME PGCD-COL-D03N050-CTLFireability-2024-03
FORMULA_NAME PGCD-COL-D03N050-CTLFireability-2024-04
FORMULA_NAME PGCD-COL-D03N050-CTLFireability-2024-05
FORMULA_NAME PGCD-COL-D03N050-CTLFireability-2024-06
FORMULA_NAME PGCD-COL-D03N050-CTLFireability-2024-07
FORMULA_NAME PGCD-COL-D03N050-CTLFireability-2024-08
FORMULA_NAME PGCD-COL-D03N050-CTLFireability-2024-09
FORMULA_NAME PGCD-COL-D03N050-CTLFireability-2024-10
FORMULA_NAME PGCD-COL-D03N050-CTLFireability-2024-11
FORMULA_NAME PGCD-COL-D03N050-CTLFireability-2024-12
FORMULA_NAME PGCD-COL-D03N050-CTLFireability-2024-13
FORMULA_NAME PGCD-COL-D03N050-CTLFireability-2024-14
FORMULA_NAME PGCD-COL-D03N050-CTLFireability-2024-15

=== Now, execution of the tool begins

BK_START 1780332530527

CANNOT_COMPUTE

BK_STOP 1780332862525

--------------------
content from stderr:

TY MCC
Host: mcc2026
BK_TOOL: TY
Input: /home/mcc/execution
Examination: CTLFireability
Threads: 4
Storage: /tmp/ty-mcc-storage
Fingerprint set backend: cas
Backend evidence: /tmp/ty-mcc-storage/backend-capability.jsonl
CTL: MCC routing colored PNML net type `http://www.pnml.org/version-2009/grammar/symmetricnet` through uncollapsed source at /home/mcc/execution
auto-sized (FingerprintOnly): 12 places (11 packed, 11B exact) × 1B/place max = 59B/state → primary_capacity=360101862 state_limit=unbounded
CTL shallow routing: 1/16 properties routed to reachability
IntelligenceBus: LP seeded 12 place bounds
IntelligenceBus: published 16 P-invariant constraints
BMC: ay not found, skipping bounded model checking
MCC reachability_answer_lane_summary lane=post_smt_witness_bfs status=incomplete stop_reason=state_cap skip_reason=none property_count=1 residual_before=1 seeded=0 unresolved_after=1 visited_states=130051 configured_max_states=200000 effective_max_states=200000 phase_cap_ms=2000 completed=false elapsed_ms=385
AIGER encoding: 96 latches, 12 transitions, 12 constraints
preprocess: timeout (12.9s) — skipping remaining phases
preprocess: latches 96->96->93 inputs 12->12->12 gates 3152->3152->2576 clauses 9651->7728 const_elim=0 scorr_elim=3(iters=1) frts_elim=0 bve_elim=0 frts_bve_iters=0 rewrite_elim=0 dag_rewrite_elim=0 refactor_elim=0 synthesis(rounds=0,gates=-0,depth=-0) ternary=0 ternary_sim=0 renumber=653
Compaction: max_var 2681->2681 (0% reduction)
IC3: 93 latches, 12 inputs, 12 constraints, 96 init_clauses, 7728 trans_clauses, 1 bad (trans/latch: 83.1x, constraint/latch: 0.1x, consec_verify: 1, crosscheck_disabled: false, predprop: false)
IC3: 93 latches, 12 inputs, 12 constraints, 96 init_clauses, 7728 trans_clauses, 1 bad (trans/latch: 83.1x, constraint/latch: 0.1x, consec_verify: 1, crosscheck_disabled: false, predprop: false)
IC3: 93 latches, 12 inputs, 12 constraints, 96 init_clauses, 7728 trans_clauses, 1 bad (trans/latch: 83.1x, constraint/latch: 0.1x, consec_verify: 1, crosscheck_disabled: false, predprop: false)
IC3 depth=1 lemmas=[0] total=0 inf=0
IC3 depth=1 blocked=0 natural_exit=true
IC3 depth=2 lemmas=[0, 0] total=0 inf=0
IC3 depth=1 lemmas=[0] total=0 inf=0
IC3: 93 latches, 12 inputs, 12 constraints, 96 init_clauses, 7728 trans_clauses, 1 bad (trans/latch: 83.1x, constraint/latch: 0.1x, consec_verify: 1, crosscheck_disabled: false, predprop: false)
IC3: 93 latches, 12 inputs, 12 constraints, 96 init_clauses, 7728 trans_clauses, 1 bad (trans/latch: 83.1x, constraint/latch: 0.1x, consec_verify: 1, crosscheck_disabled: false, predprop: false)
IC3 depth=1 blocked=0 natural_exit=true
IC3 depth=2 lemmas=[0, 0] total=0 inf=0
IC3: 93 latches, 12 inputs, 12 constraints, 96 init_clauses, 7728 trans_clauses, 1 bad (trans/latch: 83.1x, constraint/latch: 0.1x, consec_verify: 1, crosscheck_disabled: false, predprop: false)
IC3: 93 latches, 12 inputs, 12 constraints, 96 init_clauses, 7728 trans_clauses, 1 bad (trans/latch: 83.1x, constraint/latch: 0.1x, consec_verify: 1, crosscheck_disabled: false, predprop: false)
IC3: 93 latches, 12 inputs, 12 constraints, 96 init_clauses, 7728 trans_clauses, 1 bad (trans/latch: 83.1x, constraint/latch: 0.1x, consec_verify: 1, crosscheck_disabled: false, predprop: false)
IC3: 93 latches, 12 inputs, 12 constraints, 96 init_clauses, 7728 trans_clauses, 1 bad (trans/latch: 83.1x, constraint/latch: 0.1x, consec_verify: 1, crosscheck_disabled: false, predprop: false)
IC3: 93 latches, 12 inputs, 12 constraints, 96 init_clauses, 7728 trans_clauses, 1 bad (trans/latch: 83.1x, constraint/latch: 0.1x, consec_verify: 1, crosscheck_disabled: false, predprop: false)
IC3 depth=1 lemmas=[0] total=0 inf=0
IC3: 93 latches, 12 inputs, 12 constraints, 96 init_clauses, 7728 trans_clauses, 1 bad (trans/latch: 83.1x, constraint/latch: 0.1x, consec_verify: 1, crosscheck_disabled: false, predprop: false)
IC3 depth=1 blocked=0 natural_exit=true
IC3 depth=1 lemmas=[0] total=0 inf=0
IC3 depth=1 blocked=0 natural_exit=true
IC3 depth=2 lemmas=[0, 0] total=0 inf=0
IC3: 93 latches, 12 inputs, 12 constraints, 96 init_clauses, 7728 trans_clauses, 1 bad (trans/latch: 83.1x, constraint/latch: 0.1x, consec_verify: 1, crosscheck_disabled: false, predprop: false)
IC3 depth=2 lemmas=[0, 0] total=0 inf=0
IC3 depth=1 lemmas=[0] total=0 inf=0
IC3 depth=1 blocked=0 natural_exit=true
IC3 depth=1 lemmas=[0] total=0 inf=0
IC3 depth=1 blocked=0 natural_exit=true
IC3 depth=1 lemmas=[0] total=0 inf=0
IC3 depth=1 blocked=0 natural_exit=true
IC3 depth=2 lemmas=[0, 0] total=0 inf=0
IC3 depth=2 lemmas=[0, 0] total=0 inf=0
IC3 depth=1 lemmas=[0] total=0 inf=0
IC3 depth=1 lemmas=[0] total=0 inf=0
IC3 depth=1 blocked=0 natural_exit=true
IC3 depth=1 blocked=0 natural_exit=true
IC3 depth=2 lemmas=[0, 0] total=0 inf=0
IC3: 93 latches, 12 inputs, 12 constraints, 96 init_clauses, 7728 trans_clauses, 1 bad (trans/latch: 83.1x, constraint/latch: 0.1x, consec_verify: 1, crosscheck_disabled: false, predprop: false)
IC3 depth=2 lemmas=[0, 0] total=0 inf=0
IC3 depth=1 lemmas=[0] total=0 inf=0
IC3 depth=1 blocked=0 natural_exit=true
IC3 depth=2 lemmas=[0, 0] total=0 inf=0
IC3 depth=1 lemmas=[0] total=0 inf=0
IC3 depth=1 blocked=0 natural_exit=true
IC3 depth=2 lemmas=[0, 0] total=0 inf=0
IC3 depth=1 lemmas=[0] total=0 inf=0
IC3 depth=1 blocked=0 natural_exit=true
IC3 depth=2 lemmas=[0, 0] total=0 inf=0
IC3 depth=2 lemmas=[0, 0] total=0 inf=0
IC3: 93 latches, 12 inputs, 12 constraints, 96 init_clauses, 7728 trans_clauses, 1 bad (trans/latch: 83.1x, constraint/latch: 0.1x, consec_verify: 1, crosscheck_disabled: false, predprop: false)
IC3 depth=1 lemmas=[0] total=0 inf=0
IC3 depth=1 blocked=0 natural_exit=true
IC3 depth=2 lemmas=[0, 0] total=0 inf=0
IC3 depth=1 lemmas=[0] total=0 inf=0
IC3 depth=1 blocked=0 natural_exit=true
IC3 depth=2 lemmas=[0, 0] total=0 inf=0
BMC(step=1): depth=4/50000 vars=13405 latches=93 elapsed=2.9s rate=1depth/s
BMC(geometric step=1): depth=4/50000 vars=13405 latches=93 elapsed=3.6s rate=1depth/s
IC3 domain stats: consecution(restricted=13 fallback=0 rate=100.0%) mic(restricted=21 fallback=0 rate=100.0%) avg_coverage=89.9%
IC3 consecution stats: queries=13 unsat=10 sat=2 unknown=1 verified=0 rejected=0 reject_rate=0.0% domain_restricted=13 full_solver=0
IC3 domain stats: consecution(restricted=6 fallback=0 rate=100.0%) mic(restricted=12 fallback=0 rate=100.0%) avg_coverage=78.3%
IC3 consecution stats: queries=6 unsat=4 sat=2 unknown=0 verified=0 rejected=0 reject_rate=0.0% domain_restricted=6 full_solver=0
IC3 domain stats: consecution(restricted=6 fallback=0 rate=100.0%) mic(restricted=10 fallback=0 rate=100.0%) avg_coverage=78.3%
IC3 consecution stats: queries=6 unsat=4 sat=2 unknown=0 verified=0 rejected=0 reject_rate=0.0% domain_restricted=6 full_solver=0
IC3 domain stats: consecution(restricted=22 fallback=0 rate=100.0%) mic(restricted=38 fallback=0 rate=100.0%) avg_coverage=73.1%
IC3 consecution stats: queries=22 unsat=12 sat=10 unknown=0 verified=0 rejected=0 reject_rate=0.0% domain_restricted=22 full_solver=0
IC3 domain stats: consecution(restricted=27 fallback=0 rate=100.0%) mic(restricted=43 fallback=0 rate=100.0%) avg_coverage=73.1%
IC3 consecution stats: queries=27 unsat=15 sat=12 unknown=0 verified=0 rejected=0 reject_rate=0.0% domain_restricted=27 full_solver=0
IC3 domain stats: consecution(restricted=3 fallback=0 rate=100.0%) mic(restricted=9 fallback=0 rate=100.0%) avg_coverage=79.4%
IC3 consecution stats: queries=3 unsat=2 sat=1 unknown=0 verified=0 rejected=0 reject_rate=0.0% domain_restricted=3 full_solver=0
IC3 domain stats: consecution(restricted=22 fallback=0 rate=100.0%) mic(restricted=38 fallback=0 rate=100.0%) avg_coverage=73.1%
IC3 consecution stats: queries=22 unsat=12 sat=10 unknown=0 verified=0 rejected=0 reject_rate=0.0% domain_restricted=22 full_solver=0
IC3 domain stats: consecution(restricted=22 fallback=0 rate=100.0%) mic(restricted=37 fallback=0 rate=100.0%) avg_coverage=73.1%
IC3 consecution stats: queries=22 unsat=12 sat=10 unknown=0 verified=0 rejected=0 reject_rate=0.0% domain_restricted=22 full_solver=0
IC3 domain stats: consecution(restricted=3 fallback=0 rate=100.0%) mic(restricted=9 fallback=0 rate=100.0%) avg_coverage=79.4%
IC3 consecution stats: queries=3 unsat=2 sat=1 unknown=0 verified=0 rejected=0 reject_rate=0.0% domain_restricted=3 full_solver=0
IC3 domain stats: consecution(restricted=3 fallback=0 rate=100.0%) mic(restricted=5 fallback=0 rate=100.0%) avg_coverage=79.4%
IC3 consecution stats: queries=3 unsat=2 sat=1 unknown=0 verified=0 rejected=0 reject_rate=0.0% domain_restricted=3 full_solver=0
IC3 domain stats: consecution(restricted=32 fallback=0 rate=100.0%) mic(restricted=61 fallback=0 rate=100.0%) avg_coverage=73.6%
IC3 consecution stats: queries=32 unsat=18 sat=14 unknown=0 verified=0 rejected=0 reject_rate=0.0% domain_restricted=32 full_solver=0
IC3 domain stats: consecution(restricted=3 fallback=0 rate=100.0%) mic(restricted=10 fallback=0 rate=100.0%) avg_coverage=79.4%
IC3 consecution stats: queries=3 unsat=2 sat=1 unknown=0 verified=0 rejected=0 reject_rate=0.0% domain_restricted=3 full_solver=0
IC3 domain stats: consecution(restricted=11 fallback=0 rate=100.0%) mic(restricted=28 fallback=0 rate=100.0%) avg_coverage=74.7%
IC3 consecution stats: queries=11 unsat=6 sat=5 unknown=0 verified=0 rejected=0 reject_rate=0.0% domain_restricted=11 full_solver=0
IC3 domain stats: consecution(restricted=11 fallback=0 rate=100.0%) mic(restricted=25 fallback=0 rate=100.0%) avg_coverage=74.7%
IC3 consecution stats: queries=11 unsat=6 sat=5 unknown=0 verified=0 rejected=0 reject_rate=0.0% domain_restricted=11 full_solver=0
Portfolio: 1 thread(s) still running after 3s grace period — detaching (#4096)
Random walk seeded 1/1 reachability verdicts
CTL suffix routing: 1/16 properties routed to suffix analysis
memory allocation of 128 bytes failed
note: run with `RUST_BACKTRACE=1` environment variable to display a backtrace
/home/mcc/BenchKit/BenchKit_head.sh: line 392: 561 Aborted "${cmd[@]}" > "$stdout_capture"
ty-mcc exited with status 134

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="PGCD-COL-D03N050"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="TY"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5973"
echo " Executing tool TY"
echo " Input is PGCD-COL-D03N050, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r198-tall-177969916700770"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/PGCD-COL-D03N050.tgz
mv PGCD-COL-D03N050 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;