Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/sdalzilio/mcc2026-input.r182-oct2-177969022300161.qcow2', fmt=qcow2 cluster_size=65536 extended_l2=off compression_type=zlib size=4294967296 backing_file=/data/sdalzilio/mcc2026-input.qcow2 backing_fmt=qcow2 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
..........................
=====================================================================
Generated by BenchKit 2-5973
Executing tool TY
Input is MedleyA-PT-09, examination is CTLCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r182-oct2-177969022300161
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 528K
-rw-r--r-- 1 mcc users 6.9K Mar 7 18:19 CTLCardinality.txt
-rw-r--r-- 1 mcc users 74K Mar 7 18:19 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.5K Mar 7 18:19 CTLFireability.txt
-rw-r--r-- 1 mcc users 66K Mar 7 18:19 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.5K Mar 15 11:27 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Mar 15 11:27 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Mar 15 11:27 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Mar 15 11:27 LTLFireability.xml
-rw-r--r-- 1 mcc users 11K Mar 7 18:19 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 114K Mar 7 18:19 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.0K Mar 7 18:19 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 56K Mar 7 18:19 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Mar 15 11:27 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Mar 15 11:27 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 3 18:30 equiv_col
-rw-r--r-- 1 mcc users 3 Mar 3 18:30 instance
-rw-r--r-- 1 mcc users 6 Mar 3 18:30 iscolored
-rw-r--r-- 1 mcc users 99K Mar 3 18:30 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

echo here is the order used to build the result vector(from xml file)
FORMULA_NAME MedleyA-PT-09-CTLCardinality-2024-00
FORMULA_NAME MedleyA-PT-09-CTLCardinality-2024-01
FORMULA_NAME MedleyA-PT-09-CTLCardinality-2024-02
FORMULA_NAME MedleyA-PT-09-CTLCardinality-2024-03
FORMULA_NAME MedleyA-PT-09-CTLCardinality-2024-04
FORMULA_NAME MedleyA-PT-09-CTLCardinality-2024-05
FORMULA_NAME MedleyA-PT-09-CTLCardinality-2024-06
FORMULA_NAME MedleyA-PT-09-CTLCardinality-2024-07
FORMULA_NAME MedleyA-PT-09-CTLCardinality-2024-08
FORMULA_NAME MedleyA-PT-09-CTLCardinality-2024-09
FORMULA_NAME MedleyA-PT-09-CTLCardinality-2024-10
FORMULA_NAME MedleyA-PT-09-CTLCardinality-2024-11
FORMULA_NAME MedleyA-PT-09-CTLCardinality-2024-12
FORMULA_NAME MedleyA-PT-09-CTLCardinality-2024-13
FORMULA_NAME MedleyA-PT-09-CTLCardinality-2024-14
FORMULA_NAME MedleyA-PT-09-CTLCardinality-2024-15

=== Now, execution of the tool begins

BK_START 1780169341988

CANNOT_COMPUTE

BK_STOP 1780169950887

--------------------
content from stderr:

TY MCC
Host: mcc2026
BK_TOOL: TY
Input: /home/mcc/execution
Examination: CTLCardinality
Threads: 4
Storage: /tmp/ty-mcc-storage
Fingerprint set backend: cas
Backend evidence: /tmp/ty-mcc-storage/backend-capability.jsonl
auto-sized (FingerprintOnly): 147 places (146 packed, 19B exact) × 1B/place max = 67B/state → primary_capacity=360104192 state_limit=unbounded
CTL shallow routing: 1/16 properties routed to reachability
IntelligenceBus: LP seeded 147 place bounds
IntelligenceBus: published 19 P-invariant constraints
BMC: ay not found, skipping bounded model checking
MCC reachability_answer_lane_summary lane=post_smt_witness_bfs status=incomplete stop_reason=state_cap skip_reason=none property_count=1 residual_before=1 seeded=0 unresolved_after=1 visited_states=29780 configured_max_states=200000 effective_max_states=38043 phase_cap_ms=2000 completed=false elapsed_ms=423
AIGER encoding: 148 latches, 315 transitions, 3 constraints
preprocess: latches 146->0->0 inputs 315->0->0 gates 6245->0->0 clauses 18787->0 const_elim=0 scorr_elim=0(iters=1) frts_elim=0 bve_elim=0 frts_bve_iters=1 rewrite_elim=0 dag_rewrite_elim=0 refactor_elim=0 synthesis(rounds=0,gates=-0,depth=-0) ternary=0 ternary_sim=96 renumber=0
Compaction: max_var 0->0 (0% reduction)
CEGAR(abs_all): initial abstraction 0/0 latches
CEGAR(abs_all): initial abstraction 0/0 latches
CEGAR: abstraction includes all latches, running full IC3
CEGAR(abs_cst): initial abstraction 0/0 latches
CEGAR: abstraction includes all latches, running full IC3
CEGAR: abstraction includes all latches, running full IC3
CEGAR(abs_cst): initial abstraction 0/0 latches
CEGAR: abstraction includes all latches, running full IC3
IC3: 0 latches, 0 inputs, 0 constraints, 0 init_clauses, 0 trans_clauses, 1 bad (trans/latch: 0.0x, constraint/latch: 0.0x, consec_verify: 1, crosscheck_disabled: false, predprop: false)
IC3: crosscheck disabled by config (#4163)
IC3: 0 latches, 0 inputs, 0 constraints, 0 init_clauses, 0 trans_clauses, 1 bad (trans/latch: 0.0x, constraint/latch: 0.0x, consec_verify: 1, crosscheck_disabled: true, predprop: false)
IC3: 0 latches, 0 inputs, 0 constraints, 0 init_clauses, 0 trans_clauses, 1 bad (trans/latch: 0.0x, constraint/latch: 0.0x, consec_verify: 1, crosscheck_disabled: false, predprop: false)
IC3: 0 latches, 0 inputs, 0 constraints, 0 init_clauses, 0 trans_clauses, 1 bad (trans/latch: 0.0x, constraint/latch: 0.0x, consec_verify: 1, crosscheck_disabled: false, predprop: false)
IC3: 0 latches, 0 inputs, 0 constraints, 0 init_clauses, 0 trans_clauses, 1 bad (trans/latch: 0.0x, constraint/latch: 0.0x, consec_verify: 1, crosscheck_disabled: false, predprop: false)
IC3: 0 latches, 0 inputs, 0 constraints, 0 init_clauses, 0 trans_clauses, 1 bad (trans/latch: 0.0x, constraint/latch: 0.0x, consec_verify: 1, crosscheck_disabled: false, predprop: true)
IC3: 0 latches, 0 inputs, 0 constraints, 0 init_clauses, 0 trans_clauses, 1 bad (trans/latch: 0.0x, constraint/latch: 0.0x, consec_verify: 1, crosscheck_disabled: false, predprop: false)
IC3: 0 latches, 0 inputs, 0 constraints, 0 init_clauses, 0 trans_clauses, 1 bad (trans/latch: 0.0x, constraint/latch: 0.0x, consec_verify: 1, crosscheck_disabled: false, predprop: false)
IC3: crosscheck disabled by config (#4163)
IC3: 0 latches, 0 inputs, 0 constraints, 0 init_clauses, 0 trans_clauses, 1 bad (trans/latch: 0.0x, constraint/latch: 0.0x, consec_verify: 1, crosscheck_disabled: false, predprop: false)
IC3: crosscheck disabled by config (#4163)
IC3: 0 latches, 0 inputs, 0 constraints, 0 init_clauses, 0 trans_clauses, 1 bad (trans/latch: 0.0x, constraint/latch: 0.0x, consec_verify: 1, crosscheck_disabled: true, predprop: false)
IC3: 0 latches, 0 inputs, 0 constraints, 0 init_clauses, 0 trans_clauses, 1 bad (trans/latch: 0.0x, constraint/latch: 0.0x, consec_verify: 1, crosscheck_disabled: false, predprop: false)
IC3: 0 latches, 0 inputs, 0 constraints, 0 init_clauses, 0 trans_clauses, 1 bad (trans/latch: 0.0x, constraint/latch: 0.0x, consec_verify: 1, crosscheck_disabled: false, predprop: false)
IC3: 0 latches, 0 inputs, 0 constraints, 0 init_clauses, 0 trans_clauses, 1 bad (trans/latch: 0.0x, constraint/latch: 0.0x, consec_verify: 1, crosscheck_disabled: false, predprop: false)
IC3: 0 latches, 0 inputs, 0 constraints, 0 init_clauses, 0 trans_clauses, 1 bad (trans/latch: 0.0x, constraint/latch: 0.0x, consec_verify: 1, crosscheck_disabled: false, predprop: false)
IC3: 0 latches, 0 inputs, 0 constraints, 0 init_clauses, 0 trans_clauses, 1 bad (trans/latch: 0.0x, constraint/latch: 0.0x, consec_verify: 1, crosscheck_disabled: true, predprop: false)
IC3: 0 latches, 0 inputs, 0 constraints, 0 init_clauses, 0 trans_clauses, 1 bad (trans/latch: 0.0x, constraint/latch: 0.0x, consec_verify: 1, crosscheck_disabled: false, predprop: false)
IC3: 0 latches, 0 inputs, 0 constraints, 0 init_clauses, 0 trans_clauses, 1 bad (trans/latch: 0.0x, constraint/latch: 0.0x, consec_verify: 1, crosscheck_disabled: false, predprop: false)
IC3: 0 latches, 0 inputs, 0 constraints, 0 init_clauses, 0 trans_clauses, 1 bad (trans/latch: 0.0x, constraint/latch: 0.0x, consec_verify: 1, crosscheck_disabled: false, predprop: false)
portfolio validate_safe: accepting cegar-ic3's internal safety proof without independent re-verification (no formal witness to check; #4315 logged)
IC3: 0 latches, 0 inputs, 0 constraints, 0 init_clauses, 0 trans_clauses, 1 bad (trans/latch: 0.0x, constraint/latch: 0.0x, consec_verify: 1, crosscheck_disabled: false, predprop: true)
Portfolio: INFO (#4315) — Safe result from ic3-abs-all (0.002s) independently confirmed by cegar-ic3-simple-solver (0.001s).
AIGER portfolio seeded 1/1 reachability verdicts
CTL suffix routing: 1/16 properties routed to suffix analysis
memory allocation of 1176 bytes failed
note: run with `RUST_BACKTRACE=1` environment variable to display a backtrace
/home/mcc/BenchKit/BenchKit_head.sh: line 392: 553 Aborted "${cmd[@]}" > "$stdout_capture"
ty-mcc exited with status 134

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="MedleyA-PT-09"
export BK_EXAMINATION="CTLCardinality"
export BK_TOOL="TY"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5973"
echo " Executing tool TY"
echo " Input is MedleyA-PT-09, examination is CTLCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r182-oct2-177969022300161"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/MedleyA-PT-09.tgz
mv MedleyA-PT-09 execution
cd execution
if [ "CTLCardinality" = "ReachabilityDeadlock" ] || [ "CTLCardinality" = "UpperBounds" ] || [ "CTLCardinality" = "QuasiLiveness" ] || [ "CTLCardinality" = "StableMarking" ] || [ "CTLCardinality" = "Liveness" ] || [ "CTLCardinality" = "OneSafe" ] || [ "CTLCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLCardinality" = "ReachabilityDeadlock" ] || [ "CTLCardinality" = "QuasiLiveness" ] || [ "CTLCardinality" = "StableMarking" ] || [ "CTLCardinality" = "Liveness" ] || [ "CTLCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;