About the Execution of TY for FMS-PT-02000
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 7379.292 | 1287089.00 | 5136794.00 | 145.30 | ??T???T?F??TF??? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2026-input.r134-smll-177955810600537.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2026-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5973
Executing tool TY
Input is FMS-PT-02000, examination is CTLCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r134-smll-177955810600537
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 408K
-rw-r--r-- 1 mcc users 6.5K Mar 7 05:13 CTLCardinality.txt
-rw-r--r-- 1 mcc users 66K Mar 7 05:13 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.1K Mar 7 05:13 CTLFireability.txt
-rw-r--r-- 1 mcc users 57K Mar 7 05:13 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Mar 3 18:30 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K Mar 3 18:30 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.5K Mar 15 10:19 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K Mar 15 10:19 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Mar 15 10:19 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Mar 15 10:19 LTLFireability.xml
-rw-r--r-- 1 mcc users 8.3K Mar 7 05:14 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 83K Mar 7 05:14 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 6.3K Mar 7 05:13 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 50K Mar 7 05:13 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.5K Mar 15 10:19 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Mar 15 10:19 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 3 18:30 equiv_col
-rw-r--r-- 1 mcc users 6 Mar 3 18:30 instance
-rw-r--r-- 1 mcc users 6 Mar 3 18:30 iscolored
-rw-r--r-- 1 mcc users 16K Mar 3 18:30 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
echo here is the order used to build the result vector(from xml file)
FORMULA_NAME FMS-PT-02000-CTLCardinality-2024-00
FORMULA_NAME FMS-PT-02000-CTLCardinality-2024-01
FORMULA_NAME FMS-PT-02000-CTLCardinality-2024-02
FORMULA_NAME FMS-PT-02000-CTLCardinality-2024-03
FORMULA_NAME FMS-PT-02000-CTLCardinality-2024-04
FORMULA_NAME FMS-PT-02000-CTLCardinality-2024-05
FORMULA_NAME FMS-PT-02000-CTLCardinality-2024-06
FORMULA_NAME FMS-PT-02000-CTLCardinality-2024-07
FORMULA_NAME FMS-PT-02000-CTLCardinality-2024-08
FORMULA_NAME FMS-PT-02000-CTLCardinality-2024-09
FORMULA_NAME FMS-PT-02000-CTLCardinality-2024-10
FORMULA_NAME FMS-PT-02000-CTLCardinality-2024-11
FORMULA_NAME FMS-PT-02000-CTLCardinality-2024-12
FORMULA_NAME FMS-PT-02000-CTLCardinality-2024-13
FORMULA_NAME FMS-PT-02000-CTLCardinality-2024-14
FORMULA_NAME FMS-PT-02000-CTLCardinality-2024-15
=== Now, execution of the tool begins
BK_START 1780477547303
FORMULA FMS-PT-02000-CTLCardinality-2024-06 TRUE TECHNIQUES EXPLICIT TEMPORAL_LOGIC BFS STRUCTURAL
FORMULA FMS-PT-02000-CTLCardinality-2024-11 TRUE TECHNIQUES EXPLICIT TEMPORAL_LOGIC BFS STRUCTURAL
FORMULA FMS-PT-02000-CTLCardinality-2024-00 CANNOT_COMPUTE TECHNIQUES EXPLICIT TEMPORAL_LOGIC BFS STRUCTURAL
FORMULA FMS-PT-02000-CTLCardinality-2024-01 CANNOT_COMPUTE TECHNIQUES EXPLICIT TEMPORAL_LOGIC BFS STRUCTURAL
FORMULA FMS-PT-02000-CTLCardinality-2024-02 TRUE TECHNIQUES EXPLICIT TEMPORAL_LOGIC BFS STRUCTURAL
FORMULA FMS-PT-02000-CTLCardinality-2024-03 CANNOT_COMPUTE TECHNIQUES EXPLICIT TEMPORAL_LOGIC BFS STRUCTURAL
FORMULA FMS-PT-02000-CTLCardinality-2024-04 CANNOT_COMPUTE TECHNIQUES EXPLICIT TEMPORAL_LOGIC BFS STRUCTURAL
FORMULA FMS-PT-02000-CTLCardinality-2024-05 CANNOT_COMPUTE TECHNIQUES EXPLICIT TEMPORAL_LOGIC BFS STRUCTURAL
FORMULA FMS-PT-02000-CTLCardinality-2024-07 CANNOT_COMPUTE TECHNIQUES EXPLICIT TEMPORAL_LOGIC BFS STRUCTURAL
FORMULA FMS-PT-02000-CTLCardinality-2024-08 FALSE TECHNIQUES EXPLICIT TEMPORAL_LOGIC BFS STRUCTURAL
FORMULA FMS-PT-02000-CTLCardinality-2024-09 CANNOT_COMPUTE TECHNIQUES EXPLICIT TEMPORAL_LOGIC BFS STRUCTURAL
FORMULA FMS-PT-02000-CTLCardinality-2024-10 CANNOT_COMPUTE TECHNIQUES EXPLICIT TEMPORAL_LOGIC BFS STRUCTURAL
FORMULA FMS-PT-02000-CTLCardinality-2024-12 FALSE TECHNIQUES EXPLICIT TEMPORAL_LOGIC BFS STRUCTURAL
FORMULA FMS-PT-02000-CTLCardinality-2024-13 CANNOT_COMPUTE TECHNIQUES EXPLICIT TEMPORAL_LOGIC BFS STRUCTURAL
FORMULA FMS-PT-02000-CTLCardinality-2024-14 CANNOT_COMPUTE TECHNIQUES EXPLICIT TEMPORAL_LOGIC BFS STRUCTURAL
FORMULA FMS-PT-02000-CTLCardinality-2024-15 CANNOT_COMPUTE TECHNIQUES EXPLICIT TEMPORAL_LOGIC BFS STRUCTURAL
BK_STOP 1780478834392
--------------------
content from stderr:
TY MCC
Host: mcc2026
BK_TOOL: TY
Input: /home/mcc/execution
Examination: CTLCardinality
Threads: 4
Storage: /tmp/ty-mcc-storage
Fingerprint set backend: cas
Backend evidence: /tmp/ty-mcc-storage/backend-capability.jsonl
auto-sized (FingerprintOnly): 22 places (18 packed, 31B exact) × 2B/place max = 79B/state → primary_capacity=360034841 state_limit=unbounded
CTL shallow routing: 2/16 properties routed to reachability
IntelligenceBus: LP seeded 22 place bounds
IntelligenceBus: published 6 P-invariant constraints
BMC: ay not found, skipping bounded model checking
MCC reachability_answer_lane_summary lane=post_smt_witness_bfs status=incomplete stop_reason=state_cap skip_reason=none property_count=2 residual_before=2 seeded=0 unresolved_after=2 visited_states=137803 configured_max_states=200000 effective_max_states=200000 phase_cap_ms=2000 completed=false elapsed_ms=719
AIGER encoding: 186 latches, 20 transitions, 18 constraints
preprocess: timeout (360.0s) — skipping remaining phases
preprocess: latches 186->186->186 inputs 20->20->20 gates 3509->3509->2818 clauses 10706->8454 const_elim=0 scorr_elim=0(iters=0) frts_elim=0 bve_elim=0 frts_bve_iters=0 rewrite_elim=0 dag_rewrite_elim=0 refactor_elim=0 synthesis(rounds=0,gates=-0,depth=-0) ternary=0 ternary_sim=0 renumber=759
Compaction: max_var 3024->3024 (0% reduction)
IC3: 186 latches, 20 inputs, 18 constraints, 186 init_clauses, 8454 trans_clauses, 1 bad (trans/latch: 45.5x, constraint/latch: 0.1x, consec_verify: 1, crosscheck_disabled: false, predprop: false)
IC3: 186 latches, 20 inputs, 18 constraints, 186 init_clauses, 8454 trans_clauses, 1 bad (trans/latch: 45.5x, constraint/latch: 0.1x, consec_verify: 1, crosscheck_disabled: false, predprop: false)
IC3 depth=1 lemmas=[0] total=0 inf=0
IC3 depth=1 lemmas=[0] total=0 inf=0
IC3 depth=1 blocked=0 natural_exit=true
IC3: 186 latches, 20 inputs, 18 constraints, 186 init_clauses, 8454 trans_clauses, 1 bad (trans/latch: 45.5x, constraint/latch: 0.1x, consec_verify: 1, crosscheck_disabled: false, predprop: false)
IC3: 186 latches, 20 inputs, 18 constraints, 186 init_clauses, 8454 trans_clauses, 1 bad (trans/latch: 45.5x, constraint/latch: 0.1x, consec_verify: 1, crosscheck_disabled: false, predprop: false)
IC3 depth=1 blocked=0 natural_exit=true
IC3: 186 latches, 20 inputs, 18 constraints, 186 init_clauses, 8454 trans_clauses, 1 bad (trans/latch: 45.5x, constraint/latch: 0.1x, consec_verify: 1, crosscheck_disabled: false, predprop: false)
IC3 depth=2 lemmas=[0, 0] total=0 inf=0
IC3: 186 latches, 20 inputs, 18 constraints, 186 init_clauses, 8454 trans_clauses, 1 bad (trans/latch: 45.5x, constraint/latch: 0.1x, consec_verify: 1, crosscheck_disabled: false, predprop: false)
IC3: 186 latches, 20 inputs, 18 constraints, 186 init_clauses, 8454 trans_clauses, 1 bad (trans/latch: 45.5x, constraint/latch: 0.1x, consec_verify: 1, crosscheck_disabled: false, predprop: false)
IC3 depth=2 lemmas=[0, 0] total=0 inf=0
IC3: 186 latches, 20 inputs, 18 constraints, 186 init_clauses, 8454 trans_clauses, 1 bad (trans/latch: 45.5x, constraint/latch: 0.1x, consec_verify: 1, crosscheck_disabled: false, predprop: false)
IC3 depth=1 lemmas=[0] total=0 inf=0
IC3 depth=1 blocked=0 natural_exit=true
IC3: 186 latches, 20 inputs, 18 constraints, 186 init_clauses, 8454 trans_clauses, 1 bad (trans/latch: 45.5x, constraint/latch: 0.1x, consec_verify: 1, crosscheck_disabled: false, predprop: false)
IC3: 186 latches, 20 inputs, 18 constraints, 186 init_clauses, 8454 trans_clauses, 1 bad (trans/latch: 45.5x, constraint/latch: 0.1x, consec_verify: 1, crosscheck_disabled: false, predprop: false)
IC3 depth=1 lemmas=[0] total=0 inf=0
IC3 depth=1 lemmas=[0] total=0 inf=0
IC3: 186 latches, 20 inputs, 18 constraints, 186 init_clauses, 8454 trans_clauses, 1 bad (trans/latch: 45.5x, constraint/latch: 0.1x, consec_verify: 1, crosscheck_disabled: false, predprop: false)
IC3 depth=1 lemmas=[0] total=0 inf=0
IC3: 186 latches, 20 inputs, 18 constraints, 186 init_clauses, 8454 trans_clauses, 1 bad (trans/latch: 45.5x, constraint/latch: 0.1x, consec_verify: 1, crosscheck_disabled: false, predprop: false)
IC3 depth=2 lemmas=[0, 0] total=0 inf=0
IC3 depth=1 lemmas=[0] total=0 inf=0
IC3 depth=1 blocked=0 natural_exit=true
IC3 depth=1 lemmas=[0] total=0 inf=0
IC3 depth=1 blocked=0 natural_exit=true
IC3: 186 latches, 20 inputs, 18 constraints, 186 init_clauses, 8454 trans_clauses, 1 bad (trans/latch: 45.5x, constraint/latch: 0.1x, consec_verify: 1, crosscheck_disabled: false, predprop: false)
IC3 depth=1 blocked=0 natural_exit=true
IC3 depth=1 blocked=0 natural_exit=true
IC3 depth=2 lemmas=[0, 0] total=0 inf=0
IC3: 186 latches, 20 inputs, 18 constraints, 186 init_clauses, 8454 trans_clauses, 1 bad (trans/latch: 45.5x, constraint/latch: 0.1x, consec_verify: 1, crosscheck_disabled: false, predprop: false)
IC3 depth=2 lemmas=[0, 0] total=0 inf=0
IC3 depth=1 blocked=0 natural_exit=true
IC3 depth=2 lemmas=[0, 0] total=0 inf=0
IC3 depth=1 lemmas=[0] total=0 inf=0
IC3 depth=1 blocked=0 natural_exit=true
IC3 depth=2 lemmas=[0, 0] total=0 inf=0
lift: ternary prefilter removed 125/186 state lits
IC3 depth=1 lemmas=[0] total=0 inf=0
IC3 depth=2 lemmas=[0, 0] total=0 inf=0
IC3 depth=1 blocked=0 natural_exit=true
IC3 depth=1 lemmas=[0] total=0 inf=0
IC3 depth=1 blocked=0 natural_exit=true
IC3 depth=1 lemmas=[0] total=0 inf=0
IC3 depth=1 blocked=0 natural_exit=true
IC3 depth=1 lemmas=[0] total=0 inf=0
IC3 depth=2 lemmas=[0, 0] total=0 inf=0
lift: ternary prefilter removed 125/186 state lits
lift: ternary prefilter removed 134/186 state lits
IC3 depth=1 lemmas=[0] total=0 inf=0
IC3 depth=1 blocked=0 natural_exit=true
IC3 depth=2 lemmas=[0, 0] total=0 inf=0
IC3 depth=2 lemmas=[0, 0] total=0 inf=0
IC3 depth=2 lemmas=[0, 0] total=0 inf=0
IC3 depth=1 blocked=0 natural_exit=true
IC3 depth=2 lemmas=[0, 0] total=0 inf=0
lift: ternary prefilter removed 134/186 state lits
IC3 depth=2 lemmas=[0, 0] total=0 inf=0
lift: ternary prefilter removed 125/186 state lits
lift: ternary prefilter removed 134/186 state lits
lift: ternary prefilter removed 125/186 state lits
lift: ternary prefilter removed 93/186 state lits
lift: ternary prefilter removed 90/186 state lits
lift: ternary prefilter removed 93/186 state lits
lift: ternary prefilter removed 90/186 state lits
lift: ternary prefilter removed 93/186 state lits
lift: ternary prefilter removed 90/186 state lits
lift: ternary prefilter removed 93/186 state lits
lift: ternary prefilter removed 80/186 state lits
lift: ternary prefilter removed 94/186 state lits
lift: ternary prefilter removed 161/186 state lits
lift: ternary prefilter removed 80/186 state lits
lift: ternary prefilter removed 94/186 state lits
lift: ternary prefilter removed 94/186 state lits
lift: ternary prefilter removed 94/186 state lits
lift: ternary prefilter removed 161/186 state lits
BMC(step=1): depth=10/50000 vars=33264 latches=186 elapsed=2.0s rate=5depth/s
lift: ternary prefilter removed 80/186 state lits
BMC(geometric step=1): depth=9/50000 vars=30240 latches=186 elapsed=2.0s rate=4depth/s
lift: ternary prefilter removed 171/186 state lits
lift: ternary prefilter removed 171/186 state lits
lift: ternary prefilter removed 156/186 state lits
lift: ternary prefilter removed 171/186 state lits
lift: ternary prefilter removed 161/186 state lits
lift: ternary prefilter removed 171/186 state lits
lift: ternary prefilter removed 155/186 state lits
lift: ternary prefilter removed 172/186 state lits
lift: ternary prefilter removed 172/186 state lits
IC3 domain stats: consecution(restricted=13 fallback=0 rate=100.0%) mic(restricted=0 fallback=0 rate=0.0%) avg_coverage=99.5%
IC3 consecution stats: queries=13 unsat=0 sat=13 unknown=0 verified=0 rejected=0 reject_rate=0.0% domain_restricted=13 full_solver=0
IC3 domain stats: consecution(restricted=6 fallback=0 rate=100.0%) mic(restricted=9 fallback=0 rate=100.0%) avg_coverage=43.1%
IC3 consecution stats: queries=6 unsat=3 sat=3 unknown=0 verified=0 rejected=0 reject_rate=0.0% domain_restricted=6 full_solver=0
IC3 domain stats: consecution(restricted=14 fallback=0 rate=100.0%) mic(restricted=0 fallback=0 rate=0.0%) avg_coverage=99.5%
IC3 consecution stats: queries=14 unsat=0 sat=13 unknown=1 verified=0 rejected=0 reject_rate=0.0% domain_restricted=14 full_solver=0
IC3 domain stats: consecution(restricted=10 fallback=0 rate=100.0%) mic(restricted=12 fallback=0 rate=100.0%) avg_coverage=36.9%
IC3 consecution stats: queries=10 unsat=4 sat=5 unknown=1 verified=0 rejected=0 reject_rate=0.0% domain_restricted=10 full_solver=0
IC3 domain stats: consecution(restricted=10 fallback=0 rate=100.0%) mic(restricted=12 fallback=0 rate=100.0%) avg_coverage=36.9%
IC3 consecution stats: queries=10 unsat=4 sat=5 unknown=1 verified=0 rejected=0 reject_rate=0.0% domain_restricted=10 full_solver=0
IC3 domain stats: consecution(restricted=14 fallback=0 rate=100.0%) mic(restricted=0 fallback=0 rate=0.0%) avg_coverage=99.5%
IC3 consecution stats: queries=14 unsat=0 sat=14 unknown=0 verified=0 rejected=0 reject_rate=0.0% domain_restricted=14 full_solver=0
IC3 domain stats: consecution(restricted=8 fallback=0 rate=100.0%) mic(restricted=12 fallback=0 rate=100.0%) avg_coverage=38.9%
IC3 consecution stats: queries=8 unsat=4 sat=4 unknown=0 verified=0 rejected=0 reject_rate=0.0% domain_restricted=8 full_solver=0
IC3 domain stats: consecution(restricted=14 fallback=0 rate=100.0%) mic(restricted=7 fallback=0 rate=100.0%) avg_coverage=36.1%
IC3 consecution stats: queries=14 unsat=7 sat=7 unknown=0 verified=0 rejected=0 reject_rate=0.0% domain_restricted=14 full_solver=0
IC3 domain stats: consecution(restricted=8 fallback=0 rate=100.0%) mic(restricted=12 fallback=0 rate=100.0%) avg_coverage=65.3%
IC3 consecution stats: queries=8 unsat=4 sat=4 unknown=0 verified=0 rejected=0 reject_rate=0.0% domain_restricted=8 full_solver=0
IC3 domain stats: consecution(restricted=8 fallback=0 rate=100.0%) mic(restricted=12 fallback=0 rate=100.0%) avg_coverage=65.3%
IC3 consecution stats: queries=8 unsat=4 sat=4 unknown=0 verified=0 rejected=0 reject_rate=0.0% domain_restricted=8 full_solver=0
IC3 domain stats: consecution(restricted=8 fallback=0 rate=100.0%) mic(restricted=12 fallback=0 rate=100.0%) avg_coverage=40.0%
IC3 consecution stats: queries=8 unsat=4 sat=4 unknown=0 verified=0 rejected=0 reject_rate=0.0% domain_restricted=8 full_solver=0
IC3 domain stats: consecution(restricted=11 fallback=0 rate=100.0%) mic(restricted=17 fallback=0 rate=100.0%) avg_coverage=67.5%
IC3 consecution stats: queries=11 unsat=6 sat=5 unknown=0 verified=0 rejected=0 reject_rate=0.0% domain_restricted=11 full_solver=0
IC3 domain stats: consecution(restricted=8 fallback=0 rate=100.0%) mic(restricted=12 fallback=0 rate=100.0%) avg_coverage=38.9%
IC3 consecution stats: queries=8 unsat=4 sat=4 unknown=0 verified=0 rejected=0 reject_rate=0.0% domain_restricted=8 full_solver=0
IC3 domain stats: consecution(restricted=9 fallback=0 rate=100.0%) mic(restricted=15 fallback=0 rate=100.0%) avg_coverage=69.1%
IC3 consecution stats: queries=9 unsat=5 sat=4 unknown=0 verified=0 rejected=0 reject_rate=0.0% domain_restricted=9 full_solver=0
Portfolio: 4 thread(s) still running after 3s grace period — detaching (#4096)
Random walk seeded 1/2 reachability verdicts
Heuristic search seeded 1/2 reachability verdicts
CTL local fallback: FMS-PT-02000-CTLCardinality-2024-00 -> CANNOT_COMPUTE (EDG: local EDG exceeded node cap; recursive: local CTL checker exceeded recursion depth)
CTL local fallback: FMS-PT-02000-CTLCardinality-2024-01 -> CANNOT_COMPUTE (EDG: local EDG exceeded node cap; recursive: local CTL checker exceeded recursion depth)
CTL local fallback: FMS-PT-02000-CTLCardinality-2024-03 -> CANNOT_COMPUTE (EDG: local EDG exceeded node cap; recursive: local CTL checker exceeded recursion depth)
CTL local fallback: FMS-PT-02000-CTLCardinality-2024-04 -> CANNOT_COMPUTE (EDG: local EDG exceeded node cap; recursive: local CTL checker exceeded recursion depth)
CTL local fallback: FMS-PT-02000-CTLCardinality-2024-05 -> CANNOT_COMPUTE (EDG: local EDG exceeded node cap; recursive: local CTL checker exceeded recursion depth)
CTL local fallback: FMS-PT-02000-CTLCardinality-2024-07 -> CANNOT_COMPUTE (EDG: local EDG exceeded node cap; recursive: local CTL checker exceeded recursion depth)
CTL local fallback: FMS-PT-02000-CTLCardinality-2024-09 -> CANNOT_COMPUTE (EDG: local EDG exceeded node cap; recursive: local CTL checker exceeded recursion depth)
CTL local fallback: FMS-PT-02000-CTLCardinality-2024-10 -> CANNOT_COMPUTE (EDG: local EDG exceeded node cap; recursive: local CTL checker exceeded recursion depth)
CTL local fallback: FMS-PT-02000-CTLCardinality-2024-13 -> CANNOT_COMPUTE (EDG: local EDG exceeded node cap; recursive: local CTL checker exceeded recursion depth)
CTL local fallback: FMS-PT-02000-CTLCardinality-2024-14 -> CANNOT_COMPUTE (EDG: local EDG exceeded node cap; recursive: local CTL checker exceeded recursion depth)
CTL local fallback: FMS-PT-02000-CTLCardinality-2024-15 -> CANNOT_COMPUTE (EDG: local EDG exceeded node cap; recursive: local CTL checker exceeded recursion depth)
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="FMS-PT-02000"
export BK_EXAMINATION="CTLCardinality"
export BK_TOOL="TY"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5973"
echo " Executing tool TY"
echo " Input is FMS-PT-02000, examination is CTLCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r134-smll-177955810600537"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/FMS-PT-02000.tgz
mv FMS-PT-02000 execution
cd execution
if [ "CTLCardinality" = "ReachabilityDeadlock" ] || [ "CTLCardinality" = "UpperBounds" ] || [ "CTLCardinality" = "QuasiLiveness" ] || [ "CTLCardinality" = "StableMarking" ] || [ "CTLCardinality" = "Liveness" ] || [ "CTLCardinality" = "OneSafe" ] || [ "CTLCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLCardinality" = "ReachabilityDeadlock" ] || [ "CTLCardinality" = "QuasiLiveness" ] || [ "CTLCardinality" = "StableMarking" ] || [ "CTLCardinality" = "Liveness" ] || [ "CTLCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;