Execution Chart

Sorry, for this execution, no execution chart could be reported.

Trace from the execution

Formatting '/data/fkordon/mcc2025-input.r086-smll-174860102400366.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2025-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5832
Executing tool itstools
Input is FireWire-PT-16, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r086-smll-174860102400366
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 580K
-rw-r--r-- 1 mcc users 6.8K May 29 14:47 CTLCardinality.txt
-rw-r--r-- 1 mcc users 74K May 29 14:47 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.5K May 29 14:47 CTLFireability.txt
-rw-r--r-- 1 mcc users 37K May 29 14:47 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.7K May 29 14:47 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K May 29 14:47 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K May 29 14:47 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K May 29 14:47 LTLFireability.xml
-rw-r--r-- 1 mcc users 15K May 29 14:47 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 173K May 29 14:47 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.4K May 29 14:47 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 84K May 29 14:47 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K May 29 14:47 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K May 29 14:47 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 29 14:32 equiv_col
-rw-r--r-- 1 mcc users 3 May 29 14:32 instance
-rw-r--r-- 1 mcc users 6 May 29 14:32 iscolored
-rw-r--r-- 1 mcc users 84K May 29 14:32 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

echo here is the order used to build the result vector(from xml file)
FORMULA_NAME FireWire-PT-16-ReachabilityCardinality-2025-00
FORMULA_NAME FireWire-PT-16-ReachabilityCardinality-2025-01
FORMULA_NAME FireWire-PT-16-ReachabilityCardinality-2025-02
FORMULA_NAME FireWire-PT-16-ReachabilityCardinality-2025-03
FORMULA_NAME FireWire-PT-16-ReachabilityCardinality-2025-04
FORMULA_NAME FireWire-PT-16-ReachabilityCardinality-2025-05
FORMULA_NAME FireWire-PT-16-ReachabilityCardinality-2025-06
FORMULA_NAME FireWire-PT-16-ReachabilityCardinality-2025-07
FORMULA_NAME FireWire-PT-16-ReachabilityCardinality-2025-08
FORMULA_NAME FireWire-PT-16-ReachabilityCardinality-2025-09
FORMULA_NAME FireWire-PT-16-ReachabilityCardinality-2025-10
FORMULA_NAME FireWire-PT-16-ReachabilityCardinality-2025-11
FORMULA_NAME FireWire-PT-16-ReachabilityCardinality-2025-12
FORMULA_NAME FireWire-PT-16-ReachabilityCardinality-2025-13
FORMULA_NAME FireWire-PT-16-ReachabilityCardinality-2025-14
FORMULA_NAME FireWire-PT-16-ReachabilityCardinality-2025-15

=== Now, execution of the tool begins

BK_START 1748888598104

Invoking MCC driver with
BK_TOOL=itstools
BK_EXAMINATION=ReachabilityCardinality
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=FireWire-PT-16
BK_MEMORY_CONFINEMENT=16384
Not applying reductions.
Model is PT
ReachabilityCardinality PT
Running Version 202505121319
[2025-06-02 18:23:20] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityCardinality, -its, -ltsmin, -greatspnpath, /home/mcc/BenchKit/bin//../itstools/bin//..//greatspn/, -order, META, -manyOrder, -smt, -timeout, 3600]
[2025-06-02 18:23:20] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2025-06-02 18:23:21] [INFO ] Load time of PNML (sax parser for PT used): 189 ms
[2025-06-02 18:23:21] [INFO ] Transformed 254 places.
[2025-06-02 18:23:21] [INFO ] Transformed 368 transitions.
[2025-06-02 18:23:21] [INFO ] Found NUPN structural information;
[2025-06-02 18:23:21] [INFO ] Parsed PT model containing 254 places and 368 transitions and 1032 arcs in 427 ms.
Parsed 16 properties from file /home/mcc/execution/ReachabilityCardinality.xml in 55 ms.
Working with output stream class java.io.PrintStream
FORMULA FireWire-PT-16-ReachabilityCardinality-2025-07 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
RANDOM walk for 40000 steps (9 resets) in 3012 ms. (13 steps per ms) remains 13/15 properties
FORMULA FireWire-PT-16-ReachabilityCardinality-2025-10 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA FireWire-PT-16-ReachabilityCardinality-2025-03 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
[2025-06-02 18:23:22] [INFO ] Flatten gal took : 232 ms
[2025-06-02 18:23:22] [INFO ] Flatten gal took : 86 ms
[2025-06-02 18:23:22] [INFO ] Time to serialize gal into /tmp/ReachabilityCardinality10579503490810690696.gal : 62 ms
BEST_FIRST walk for 40000 steps (9 resets) in 1352 ms. (29 steps per ms) remains 13/13 properties
[2025-06-02 18:23:22] [INFO ] Time to serialize properties into /tmp/ReachabilityCardinality11030490462934462691.prop : 21 ms
Invoking ITS tools like this :cd /home/mcc/execution;'/home/mcc/BenchKit/itstools/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.202505121319/bin/its-reach-linux64' '--gc-threshold' '2000000' '--quiet' '-i' '/tmp/ReachabilityCardinality10579503490810690696.gal' '-t' 'CGAL' '-reachable-file' '/tmp/ReachabilityCardinality11030490462934462691.prop' '--nowitness' '--gen-order' 'FOLLOW'

its-reach command run as :

/home/mcc/BenchKit/itstools/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.202505121319/bin/its-reach-linux64 --gc-threshold 2000000 --quiet ...330
Loading property file /tmp/ReachabilityCardinality11030490462934462691.prop.
BEST_FIRST walk for 40000 steps (10 resets) in 943 ms. (42 steps per ms) remains 13/13 properties
SDD proceeding with computation,13 properties remain. new max is 4
SDD size :1 after 5
SDD proceeding with computation,13 properties remain. new max is 8
SDD size :5 after 7
SDD proceeding with computation,13 properties remain. new max is 16
BEST_FIRST walk for 40000 steps (10 resets) in 380 ms. (104 steps per ms) remains 13/13 properties
SDD size :7 after 13
SDD proceeding with computation,13 properties remain. new max is 32
SDD size :13 after 45
SDD proceeding with computation,13 properties remain. new max is 64
SDD size :45 after 60
SDD proceeding with computation,13 properties remain. new max is 128
SDD size :60 after 71
SDD proceeding with computation,13 properties remain. new max is 256
SDD size :71 after 139
Invariant property FireWire-PT-16-ReachabilityCardinality-2025-15 does not hold.
FORMULA FireWire-PT-16-ReachabilityCardinality-2025-15 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING
Invariant property FireWire-PT-16-ReachabilityCardinality-2025-14 does not hold.
FORMULA FireWire-PT-16-ReachabilityCardinality-2025-14 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING
Invariant property FireWire-PT-16-ReachabilityCardinality-2025-13 does not hold.
FORMULA FireWire-PT-16-ReachabilityCardinality-2025-13 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING
SDD proceeding with computation,10 properties remain. new max is 256
SDD size :139 after 530
SDD proceeding with computation,10 properties remain. new max is 512
SDD size :530 after 643
Invariant property FireWire-PT-16-ReachabilityCardinality-2025-09 does not hold.
FORMULA FireWire-PT-16-ReachabilityCardinality-2025-09 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING
BEST_FIRST walk for 40004 steps (8 resets) in 808 ms. (49 steps per ms) remains 13/13 properties
BEST_FIRST walk for 40000 steps (14 resets) in 402 ms. (99 steps per ms) remains 13/13 properties
BEST_FIRST walk for 40000 steps (11 resets) in 334 ms. (119 steps per ms) remains 13/13 properties
BEST_FIRST walk for 40001 steps (8 resets) in 377 ms. (105 steps per ms) remains 13/13 properties
SDD proceeding with computation,9 properties remain. new max is 512
SDD size :643 after 181064
BEST_FIRST walk for 40000 steps (15 resets) in 337 ms. (118 steps per ms) remains 13/13 properties
BEST_FIRST walk for 40000 steps (10 resets) in 326 ms. (122 steps per ms) remains 13/13 properties
BEST_FIRST walk for 40004 steps (11 resets) in 311 ms. (128 steps per ms) remains 13/13 properties
Invariant property FireWire-PT-16-ReachabilityCardinality-2025-01 does not hold.
FORMULA FireWire-PT-16-ReachabilityCardinality-2025-01 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING
BEST_FIRST walk for 40002 steps (8 resets) in 307 ms. (129 steps per ms) remains 13/13 properties
BEST_FIRST walk for 40000 steps (10 resets) in 345 ms. (115 steps per ms) remains 13/13 properties
BEST_FIRST walk for 40000 steps (11 resets) in 451 ms. (88 steps per ms) remains 13/13 properties
// Phase 1: matrix 368 rows 254 cols
[2025-06-02 18:23:24] [INFO ] Computed 5 invariants in 17 ms
Excessive predecessor constraint size, skipping predecessor.
Starting Z3 with timeout 5.0 s and query timeout 500.0 ms
All remaining problems are real, not stopping.
At refinement iteration 0 (INCLUDED_ONLY) 0/114 variables, 114/114 constraints. Problems are: Problem set: 0 solved, 8 unsolved
At refinement iteration 1 (INCLUDED_ONLY) 0/114 variables, 0/114 constraints. Problems are: Problem set: 0 solved, 8 unsolved
Problem FireWire-PT-16-ReachabilityCardinality-2025-00 is UNSAT
FORMULA FireWire-PT-16-ReachabilityCardinality-2025-00 FALSE TECHNIQUES SMT_REFINEMENT
At refinement iteration 2 (OVERLAPS) 140/254 variables, 5/119 constraints. Problems are: Problem set: 1 solved, 7 unsolved
SDD proceeding with computation,8 properties remain. new max is 512
SDD size :181064 after 182536
Invariant property FireWire-PT-16-ReachabilityCardinality-2025-11 does not hold.
FORMULA FireWire-PT-16-ReachabilityCardinality-2025-11 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING
At refinement iteration 3 (INCLUDED_ONLY) 0/254 variables, 140/259 constraints. Problems are: Problem set: 2 solved, 6 unsolved
At refinement iteration 4 (INCLUDED_ONLY) 0/254 variables, 0/259 constraints. Problems are: Problem set: 2 solved, 6 unsolved
Invariant property FireWire-PT-16-ReachabilityCardinality-2025-06 does not hold.
FORMULA FireWire-PT-16-ReachabilityCardinality-2025-06 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING
At refinement iteration 5 (OVERLAPS) 368/622 variables, 254/513 constraints. Problems are: Problem set: 3 solved, 5 unsolved
At refinement iteration 6 (INCLUDED_ONLY) 0/622 variables, 0/513 constraints. Problems are: Problem set: 3 solved, 5 unsolved
At refinement iteration 7 (OVERLAPS) 0/622 variables, 0/513 constraints. Problems are: Problem set: 3 solved, 5 unsolved
No progress, stopping.
After SMT solving in domain Real declared 622/622 variables, and 513 constraints, problems are : Problem set: 3 solved, 5 unsolved in 1532 ms.
Refiners :[Domain max(s): 254/254 constraints, Positive P Invariants (semi-flows): 5/5 constraints, State Equation: 254/254 constraints, PredecessorRefiner: 8/5 constraints, Known Traps: 0/0 constraints, Known Traps Along Path: 0/0 constraints]
Escalating to Integer solving :Problem set: 3 solved, 5 unsolved
Starting Z3 with timeout 5.0 s and query timeout 500.0 ms
At refinement iteration 0 (INCLUDED_ONLY) 0/78 variables, 78/78 constraints. Problems are: Problem set: 3 solved, 5 unsolved
At refinement iteration 1 (INCLUDED_ONLY) 0/78 variables, 0/78 constraints. Problems are: Problem set: 3 solved, 5 unsolved
Problem FireWire-PT-16-ReachabilityCardinality-2025-08 is UNSAT
FORMULA FireWire-PT-16-ReachabilityCardinality-2025-08 TRUE TECHNIQUES SMT_REFINEMENT
Problem FireWire-PT-16-ReachabilityCardinality-2025-12 is UNSAT
FORMULA FireWire-PT-16-ReachabilityCardinality-2025-12 TRUE TECHNIQUES SMT_REFINEMENT
At refinement iteration 2 (OVERLAPS) 176/254 variables, 5/83 constraints. Problems are: Problem set: 5 solved, 3 unsolved
At refinement iteration 3 (INCLUDED_ONLY) 0/254 variables, 176/259 constraints. Problems are: Problem set: 5 solved, 3 unsolved
Starting Z3 with timeout 120.0 s and query timeout 12000.0 ms
SDD proceeding with computation,6 properties remain. new max is 512
SDD size :182536 after 184478
[2025-06-02 18:23:26] [INFO ] Deduced a trap composed of 16 places in 314 ms of which 31 ms to minimize.
Starting Z3 with timeout 120.0 s and query timeout 12000.0 ms
[2025-06-02 18:23:27] [INFO ] Deduced a trap composed of 101 places in 239 ms of which 31 ms to minimize.
Starting Z3 with timeout 120.0 s and query timeout 12000.0 ms
[2025-06-02 18:23:27] [INFO ] Deduced a trap composed of 114 places in 189 ms of which 17 ms to minimize.
Starting Z3 with timeout 120.0 s and query timeout 12000.0 ms
[2025-06-02 18:23:27] [INFO ] Deduced a trap composed of 103 places in 207 ms of which 31 ms to minimize.
Starting Z3 with timeout 120.0 s and query timeout 12000.0 ms
[2025-06-02 18:23:27] [INFO ] Deduced a trap composed of 104 places in 187 ms of which 25 ms to minimize.
At refinement iteration 4 (INCLUDED_ONLY) 0/254 variables, 5/264 constraints. Problems are: Problem set: 5 solved, 3 unsolved
Starting Z3 with timeout 120.0 s and query timeout 12000.0 ms
[2025-06-02 18:23:28] [INFO ] Deduced a trap composed of 76 places in 288 ms of which 56 ms to minimize.
At refinement iteration 5 (INCLUDED_ONLY) 0/254 variables, 1/265 constraints. Problems are: Problem set: 5 solved, 3 unsolved
Starting Z3 with timeout 120.0 s and query timeout 12000.0 ms
SDD proceeding with computation,6 properties remain. new max is 1024
SDD size :184478 after 186291
[2025-06-02 18:23:28] [INFO ] Deduced a trap composed of 85 places in 286 ms of which 71 ms to minimize.
At refinement iteration 6 (INCLUDED_ONLY) 0/254 variables, 1/266 constraints. Problems are: Problem set: 5 solved, 3 unsolved
At refinement iteration 7 (INCLUDED_ONLY) 0/254 variables, 0/266 constraints. Problems are: Problem set: 5 solved, 3 unsolved
Invariant property FireWire-PT-16-ReachabilityCardinality-2025-05 does not hold.
FORMULA FireWire-PT-16-ReachabilityCardinality-2025-05 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING
At refinement iteration 8 (OVERLAPS) 368/622 variables, 254/520 constraints. Problems are: Problem set: 6 solved, 2 unsolved
At refinement iteration 9 (INCLUDED_ONLY) 0/622 variables, 1/521 constraints. Problems are: Problem set: 6 solved, 2 unsolved
At refinement iteration 10 (INCLUDED_ONLY) 0/622 variables, 0/521 constraints. Problems are: Problem set: 6 solved, 2 unsolved
At refinement iteration 11 (OVERLAPS) 0/622 variables, 0/521 constraints. Problems are: Problem set: 6 solved, 2 unsolved
No progress, stopping.
After SMT solving in domain Int declared 622/622 variables, and 521 constraints, problems are : Problem set: 6 solved, 2 unsolved in 3606 ms.
Refiners :[Domain max(s): 254/254 constraints, Positive P Invariants (semi-flows): 5/5 constraints, State Equation: 254/254 constraints, PredecessorRefiner: 3/5 constraints, Known Traps: 7/7 constraints, Known Traps Along Path: 0/0 constraints]
After SMT, in 5276ms problems are : Problem set: 6 solved, 2 unsolved
Fused 2 Parikh solutions to 1 different solutions.
Parikh walk visited 0 properties in 183 ms.
Support contains 40 out of 254 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 254/254 places, 368/368 transitions.
Graph (trivial) has 156 edges and 254 vertex of which 6 / 254 are part of one of the 1 SCC in 5 ms
Free SCC test removed 5 places
Drop transitions (Empty/Sink Transition effects.) removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Graph (complete) has 595 edges and 249 vertex of which 246 are kept as prefixes of interest. Removing 3 places using SCC suffix rule.2 ms
Discarding 3 places :
Also discarding 0 output transitions
Drop transitions (Empty/Sink Transition effects.) removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Drop transitions (Trivial Post-Agglo cleanup.) removed 41 transitions
Trivial Post-agglo rules discarded 41 transitions
Performed 41 trivial Post agglomeration. Transition count delta: 41
Iterating post reduction 0 with 42 rules applied. Total rules applied 44 place count 246 transition count 320
Reduce places removed 41 places and 0 transitions.
Performed 15 Post agglomeration using F-continuation condition.Transition count delta: 15
Iterating post reduction 1 with 56 rules applied. Total rules applied 100 place count 205 transition count 305
Reduce places removed 15 places and 0 transitions.
Iterating post reduction 2 with 15 rules applied. Total rules applied 115 place count 190 transition count 305
Performed 4 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 4 Pre rules applied. Total rules applied 115 place count 190 transition count 301
Deduced a syphon composed of 4 places in 4 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 3 with 8 rules applied. Total rules applied 123 place count 186 transition count 301
Discarding 21 places :
Symmetric choice reduction at 3 with 21 rule applications. Total rules 144 place count 165 transition count 280
Iterating global reduction 3 with 21 rules applied. Total rules applied 165 place count 165 transition count 280
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 3 with 1 rules applied. Total rules applied 166 place count 165 transition count 279
Performed 4 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 4 with 4 Pre rules applied. Total rules applied 166 place count 165 transition count 275
Deduced a syphon composed of 4 places in 1 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 4 with 8 rules applied. Total rules applied 174 place count 161 transition count 275
Discarding 4 places :
Symmetric choice reduction at 4 with 4 rule applications. Total rules 178 place count 157 transition count 259
Iterating global reduction 4 with 4 rules applied. Total rules applied 182 place count 157 transition count 259
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Drop transitions (Trivial Post-Agglo cleanup.) removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 4 with 2 rules applied. Total rules applied 184 place count 157 transition count 257
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 5 with 1 rules applied. Total rules applied 185 place count 156 transition count 257
Performed 19 Post agglomeration using F-continuation condition.Transition count delta: 19
Deduced a syphon composed of 19 places in 1 ms
Reduce places removed 19 places and 0 transitions.
Iterating global reduction 6 with 38 rules applied. Total rules applied 223 place count 137 transition count 238
Performed 10 Post agglomeration using F-continuation condition.Transition count delta: -27
Deduced a syphon composed of 10 places in 0 ms
Reduce places removed 10 places and 0 transitions.
Iterating global reduction 6 with 20 rules applied. Total rules applied 243 place count 127 transition count 265
Drop transitions (Redundant composition of simpler transitions.) removed 2 transitions
Redundant transition composition rules discarded 2 transitions
Iterating global reduction 6 with 2 rules applied. Total rules applied 245 place count 127 transition count 263
Free-agglomeration rule applied 16 times.
Iterating global reduction 6 with 16 rules applied. Total rules applied 261 place count 127 transition count 247
Reduce places removed 16 places and 0 transitions.
Drop transitions (Empty/Sink Transition effects.) removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 6 with 17 rules applied. Total rules applied 278 place count 111 transition count 246
Drop transitions (Redundant composition of simpler transitions.) removed 3 transitions
Redundant transition composition rules discarded 3 transitions
Iterating global reduction 7 with 3 rules applied. Total rules applied 281 place count 111 transition count 243
Partial Free-agglomeration rule applied 2 times.
Drop transitions (Partial Free agglomeration) removed 2 transitions
Iterating global reduction 7 with 2 rules applied. Total rules applied 283 place count 111 transition count 243
Reduce places removed 1 places and 1 transitions.
Iterating global reduction 7 with 1 rules applied. Total rules applied 284 place count 110 transition count 242
Applied a total of 284 rules in 219 ms. Remains 110 /254 variables (removed 144) and now considering 242/368 (removed 126) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 229 ms. Remains : 110/254 places, 242/368 transitions.
RANDOM walk for 40000 steps (11 resets) in 468 ms. (85 steps per ms) remains 2/2 properties
BEST_FIRST walk for 40000 steps (10 resets) in 278 ms. (143 steps per ms) remains 2/2 properties
BEST_FIRST walk for 40004 steps (8 resets) in 297 ms. (134 steps per ms) remains 2/2 properties
SDD proceeding with computation,5 properties remain. new max is 1024
SDD size :186291 after 204279
Finished probabilistic random walk after 71172 steps, run visited all 2 properties in 526 ms. (steps per millisecond=135 )
Probabilistic random walk after 71172 steps, saw 18383 distinct states, run finished after 533 ms. (steps per millisecond=133 ) properties seen :2
FORMULA FireWire-PT-16-ReachabilityCardinality-2025-04 TRUE TECHNIQUES TOPOLOGICAL PROBABILISTIC_WALK
FORMULA FireWire-PT-16-ReachabilityCardinality-2025-02 TRUE TECHNIQUES TOPOLOGICAL PROBABILISTIC_WALK
ITS runner timed out or was interrupted.
ITS tools runner thread asked to quit. Dying gracefully.
All properties solved without resorting to model-checking.
Total runtime 10395 ms.

BK_STOP 1748888611155

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/bin//../itstools/bin//../
+ BINDIR=/home/mcc/BenchKit/bin//../itstools/bin//../
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ [[ ReachabilityCardinality = StateSpace ]]
+ /home/mcc/BenchKit/bin//../itstools/bin//..//runeclipse.sh /home/mcc/execution ReachabilityCardinality -its -ltsmin -greatspnpath /home/mcc/BenchKit/bin//../itstools/bin//..//greatspn/ -order META -manyOrder -smt -timeout 3600
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../itstools/bin//..//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202505121319.jar
+ VERSION=202505121319
+ echo 'Running Version 202505121319'
+ /home/mcc/BenchKit/bin//../itstools/bin//..//itstools/its-tools -pnfolder /home/mcc/execution -examination ReachabilityCardinality -its -ltsmin -greatspnpath /home/mcc/BenchKit/bin//../itstools/bin//..//greatspn/ -order META -manyOrder -smt -timeout 3600

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="FireWire-PT-16"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5832"
echo " Executing tool itstools"
echo " Input is FireWire-PT-16, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r086-smll-174860102400366"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/FireWire-PT-16.tgz
mv FireWire-PT-16 execution
cd execution
if [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "UpperBounds" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] || [ "ReachabilityCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME ReachabilityCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;