About the Execution of LoLA for ResIsolation-PT-N09P5
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 9991.235 | 3600000.00 | 3662125.00 | 12933.00 | [undef] | Time out reached |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r629-smll-171774446300076.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is ResIsolation-PT-N09P5, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r629-smll-171774446300076
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 211M
-rw-r--r-- 1 mcc users 5.7K Jun 7 06:38 CTLCardinality.txt
-rw-r--r-- 1 mcc users 59K Jun 7 06:38 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.3K Jun 7 06:38 CTLFireability.txt
-rw-r--r-- 1 mcc users 57K Jun 7 06:38 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.7K Jun 7 06:44 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K Jun 7 06:44 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K Jun 7 06:44 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Jun 7 06:44 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 Jun 7 06:26 NewModel
-rw-r--r-- 1 mcc users 12K Jun 7 06:39 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 127K Jun 7 06:39 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.9K Jun 7 06:39 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 62K Jun 7 06:39 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Jun 7 06:43 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Jun 7 06:43 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Jun 7 06:26 equiv_col
-rw-r--r-- 1 mcc users 6 Jun 7 06:26 instance
-rw-r--r-- 1 mcc users 6 Jun 7 06:26 iscolored
-rw-r--r-- 1 mcc users 211M Jun 7 06:26 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME ResIsolation-PT-N09P5-LTLFireability-00
FORMULA_NAME ResIsolation-PT-N09P5-LTLFireability-01
FORMULA_NAME ResIsolation-PT-N09P5-LTLFireability-02
FORMULA_NAME ResIsolation-PT-N09P5-LTLFireability-03
FORMULA_NAME ResIsolation-PT-N09P5-LTLFireability-04
FORMULA_NAME ResIsolation-PT-N09P5-LTLFireability-05
FORMULA_NAME ResIsolation-PT-N09P5-LTLFireability-06
FORMULA_NAME ResIsolation-PT-N09P5-LTLFireability-07
FORMULA_NAME ResIsolation-PT-N09P5-LTLFireability-08
FORMULA_NAME ResIsolation-PT-N09P5-LTLFireability-09
FORMULA_NAME ResIsolation-PT-N09P5-LTLFireability-10
FORMULA_NAME ResIsolation-PT-N09P5-LTLFireability-11
FORMULA_NAME ResIsolation-PT-N09P5-LTLFireability-12
FORMULA_NAME ResIsolation-PT-N09P5-LTLFireability-13
FORMULA_NAME ResIsolation-PT-N09P5-LTLFireability-14
FORMULA_NAME ResIsolation-PT-N09P5-LTLFireability-15
=== Now, execution of the tool begins
BK_START 1717801351319
starting LoLA
BK_EXAMINATION: LTLFireability
BK_TIME_CONFINEMENT: 3600
BK_MEMORY_CONFINEMENT: 16384
BK_BIN_PATH: /home/mcc/BenchKit/bin/
current directory: /home/mcc/execution
BK_TIME_CONFINEMENT_REACHED
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mLTLFireability.xml[0m
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 32 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 37 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 42 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 47 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 52 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 57 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 62 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 67 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 72 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 77 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 82 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 87 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 92 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 97 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 102 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 107 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 112 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 117 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 122 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 127 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 132 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 137 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 142 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 147 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 152 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 157 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 162 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 167 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 172 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 177 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 182 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 187 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 192 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 197 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 202 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 207 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 212 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 217 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 222 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 227 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 232 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 237 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 242 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 247 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 252 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 257 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 262 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 267 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 272 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 277 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 282 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 287 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 292 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 297 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 302 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 307 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 312 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 317 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 322 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 327 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 332 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 337 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 342 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 347 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 352 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 357 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 362 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 367 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 372 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 377 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 382 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 387 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 392 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 397 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 402 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 407 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 412 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 417 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 422 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 427 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 432 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 437 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 442 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 447 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 452 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 457 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 462 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 467 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 472 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 477 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 482 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 487 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 492 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 497 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 502 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 507 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 512 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 517 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 522 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 527 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 532 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 537 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 542 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 547 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 552 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 557 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 562 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 567 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 572 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 577 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 582 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 587 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 592 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 597 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 602 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 607 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 612 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 617 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 622 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 627 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 632 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 637 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 642 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 647 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 652 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 657 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 662 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 667 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 672 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 677 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 682 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 687 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 692 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 697 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 702 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 707 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 712 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 717 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 722 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 727 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 732 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 737 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 742 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 747 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 752 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 757 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 762 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 767 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 772 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 777 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 782 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 787 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 792 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 797 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 802 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 807 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 812 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 817 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 822 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 827 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 832 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 837 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 842 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 847 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 852 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 857 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 862 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 867 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 872 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 877 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 882 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 887 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 892 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 897 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 902 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 907 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 912 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 917 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 922 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 927 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 932 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 937 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 942 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 947 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 952 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 957 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 962 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 967 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 972 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 977 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 982 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 987 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 992 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 997 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1002 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1007 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1012 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1017 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1022 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1027 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1032 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1037 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1042 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1047 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1052 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1057 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1062 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1067 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1072 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1077 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1082 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1087 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1092 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1097 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1102 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1107 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1112 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1117 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1122 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1127 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1132 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1137 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1142 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1147 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1152 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1157 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1162 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1167 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1172 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1177 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1182 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1187 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1192 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1197 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1202 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1207 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1212 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1217 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1222 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1227 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1232 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1237 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1242 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1247 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1252 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1257 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1262 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1267 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1272 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1277 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1282 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1287 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1292 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1297 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1302 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1307 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1312 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1317 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1322 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1327 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1332 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1337 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1342 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1347 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1352 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1357 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1362 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1367 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1372 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1377 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1382 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1387 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1392 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1397 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1402 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1407 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1412 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1417 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1422 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1427 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1432 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1437 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1442 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1447 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1452 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1457 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1462 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1467 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1472 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1477 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1482 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1487 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1492 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1497 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1502 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1507 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1512 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1517 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1522 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1527 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1532 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1537 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1542 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1547 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1552 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1557 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1562 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1567 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1572 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1577 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1582 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1587 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1592 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1597 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1602 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1607 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1612 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1617 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1622 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1627 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1632 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1637 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1642 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1647 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1652 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1657 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1662 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1667 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1672 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1677 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1682 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1687 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1692 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1697 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1702 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1707 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1712 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1717 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1722 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1727 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1732 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1737 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1742 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1747 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1752 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1757 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1762 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1767 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1772 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1777 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1782 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1787 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1792 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1797 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1802 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1807 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-03: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
========== file over 1MB has been truncated ======
retrieve it from the run archives if needed
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ResIsolation-PT-N09P5"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is ResIsolation-PT-N09P5, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r629-smll-171774446300076"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/ResIsolation-PT-N09P5.tgz
mv ResIsolation-PT-N09P5 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;