About the Execution of LoLA for ResIsolation-PT-N09P5
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
8598.771 | 3600000.00 | 3639547.00 | 13194.70 | [undef] | Time out reached |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r629-smll-171774446300074.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
...............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is ResIsolation-PT-N09P5, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r629-smll-171774446300074
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 211M
-rw-r--r-- 1 mcc users 5.7K Jun 7 06:38 CTLCardinality.txt
-rw-r--r-- 1 mcc users 59K Jun 7 06:38 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.3K Jun 7 06:38 CTLFireability.txt
-rw-r--r-- 1 mcc users 57K Jun 7 06:38 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.7K Jun 7 06:44 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K Jun 7 06:44 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K Jun 7 06:44 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Jun 7 06:44 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 Jun 7 06:26 NewModel
-rw-r--r-- 1 mcc users 12K Jun 7 06:39 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 127K Jun 7 06:39 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.9K Jun 7 06:39 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 62K Jun 7 06:39 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Jun 7 06:43 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Jun 7 06:43 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Jun 7 06:26 equiv_col
-rw-r--r-- 1 mcc users 6 Jun 7 06:26 instance
-rw-r--r-- 1 mcc users 6 Jun 7 06:26 iscolored
-rw-r--r-- 1 mcc users 211M Jun 7 06:26 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME ResIsolation-PT-N09P5-CTLFireability-2024-00
FORMULA_NAME ResIsolation-PT-N09P5-CTLFireability-2024-01
FORMULA_NAME ResIsolation-PT-N09P5-CTLFireability-2024-02
FORMULA_NAME ResIsolation-PT-N09P5-CTLFireability-2024-03
FORMULA_NAME ResIsolation-PT-N09P5-CTLFireability-2024-04
FORMULA_NAME ResIsolation-PT-N09P5-CTLFireability-2024-05
FORMULA_NAME ResIsolation-PT-N09P5-CTLFireability-2024-06
FORMULA_NAME ResIsolation-PT-N09P5-CTLFireability-2024-07
FORMULA_NAME ResIsolation-PT-N09P5-CTLFireability-2024-08
FORMULA_NAME ResIsolation-PT-N09P5-CTLFireability-2024-09
FORMULA_NAME ResIsolation-PT-N09P5-CTLFireability-2024-10
FORMULA_NAME ResIsolation-PT-N09P5-CTLFireability-2024-11
FORMULA_NAME ResIsolation-PT-N09P5-CTLFireability-2024-12
FORMULA_NAME ResIsolation-PT-N09P5-CTLFireability-2024-13
FORMULA_NAME ResIsolation-PT-N09P5-CTLFireability-2024-14
FORMULA_NAME ResIsolation-PT-N09P5-CTLFireability-2024-15
=== Now, execution of the tool begins
BK_START 1717797729606
starting LoLA
BK_EXAMINATION: CTLFireability
BK_TIME_CONFINEMENT: 3600
BK_MEMORY_CONFINEMENT: 16384
BK_BIN_PATH: /home/mcc/BenchKit/bin/
current directory: /home/mcc/execution
BK_TIME_CONFINEMENT_REACHED
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 119 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 124 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 129 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 134 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 139 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 144 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 149 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 154 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 159 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 164 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 169 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 174 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 179 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 184 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 189 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 194 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 199 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 204 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 209 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 214 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 219 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 224 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 229 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 234 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 239 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 244 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 249 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 254 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 259 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 264 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 269 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 274 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 279 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 284 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 289 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 294 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 299 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 304 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 309 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 314 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 319 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 324 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 329 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 334 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 339 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 344 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 349 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 354 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 359 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 364 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 369 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 374 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 379 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 384 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 389 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 394 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 399 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 404 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 409 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 414 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 419 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 424 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 429 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 434 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 439 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 444 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 449 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 454 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 459 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 464 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 469 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 474 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 479 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 484 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 489 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 494 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 499 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 504 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 509 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 514 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 519 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 524 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 529 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 534 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 539 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 544 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 549 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 554 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 559 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 564 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 569 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 574 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 579 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 584 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 589 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 594 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 599 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 604 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 609 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 614 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 619 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 624 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 629 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 634 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 639 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 644 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 649 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 654 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 659 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 664 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 669 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 674 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 679 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 684 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 689 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 694 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 699 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 704 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 709 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 714 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 719 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 724 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 729 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 734 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 739 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 744 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 749 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 754 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 759 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 764 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 769 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 774 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 779 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 784 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 789 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 794 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 799 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 804 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 809 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 814 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 819 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 824 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 829 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 834 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 839 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 844 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 849 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 854 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 859 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 864 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 869 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 874 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 879 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 884 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 889 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 894 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 899 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 904 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 909 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 914 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 919 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 924 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 929 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 934 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 939 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 944 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 949 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 954 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 959 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 964 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 969 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 974 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 979 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 984 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 989 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 994 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 999 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1004 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1009 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1014 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1019 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1024 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1029 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1034 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1039 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1044 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1049 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1054 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1059 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1064 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1069 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1074 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1079 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1084 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1089 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1094 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1099 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1104 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1109 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1114 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1119 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1124 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1129 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1134 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1139 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1144 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1149 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1154 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1159 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1164 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1169 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1174 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1179 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1184 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1189 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1194 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1199 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1204 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1209 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1214 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1219 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1224 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1229 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1234 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1239 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1244 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1249 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1254 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1259 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1264 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1269 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1274 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1279 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1284 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1289 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1294 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1299 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1304 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1309 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1314 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1319 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1324 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1329 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1334 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1339 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1344 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1349 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1354 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1359 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1364 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1369 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1374 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1379 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1384 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1389 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1394 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1399 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1404 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1409 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1414 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1419 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1424 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1429 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1434 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1439 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1444 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1449 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1454 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1459 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1464 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1469 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1474 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1479 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1484 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1489 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1494 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1499 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1504 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1509 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1514 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1519 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1524 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1529 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1534 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1539 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1544 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1549 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1554 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1559 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1564 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1569 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1574 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1579 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1584 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1589 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1594 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1599 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1604 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1609 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1614 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1619 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1624 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1629 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1634 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1639 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1644 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1649 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1654 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1659 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1664 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1669 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1674 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1679 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1684 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1689 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1694 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1699 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1704 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1709 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1714 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1719 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1724 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1729 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1734 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1739 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1744 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1749 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1754 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1759 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1764 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1769 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1774 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1779 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1784 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1789 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1794 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1799 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1804 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1809 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1814 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1819 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1824 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1829 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1834 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1839 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1844 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1849 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1854 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1859 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-06: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N09P5-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
========== file over 1MB has been truncated ======
retrieve it from the run archives if needed
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ResIsolation-PT-N09P5"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is ResIsolation-PT-N09P5, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r629-smll-171774446300074"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/ResIsolation-PT-N09P5.tgz
mv ResIsolation-PT-N09P5 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;