About the Execution of LoLA for ResIsolation-PT-N08P2
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 8739.096 | 456088.00 | 728938.00 | 1204.70 | TFFFFFTF?FFFTTFT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r629-smll-171774446200012.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is ResIsolation-PT-N08P2, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r629-smll-171774446200012
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 9.5M
-rw-r--r-- 1 mcc users 5.6K Jun 7 06:38 CTLCardinality.txt
-rw-r--r-- 1 mcc users 55K Jun 7 06:38 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.9K Jun 7 06:38 CTLFireability.txt
-rw-r--r-- 1 mcc users 56K Jun 7 06:38 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.7K Jun 7 06:44 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Jun 7 06:44 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K Jun 7 06:44 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Jun 7 06:44 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 Jun 7 06:26 NewModel
-rw-r--r-- 1 mcc users 11K Jun 7 06:39 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 110K Jun 7 06:39 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 6.9K Jun 7 06:39 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 53K Jun 7 06:39 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Jun 7 06:43 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Jun 7 06:43 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Jun 7 06:26 equiv_col
-rw-r--r-- 1 mcc users 6 Jun 7 06:26 instance
-rw-r--r-- 1 mcc users 6 Jun 7 06:26 iscolored
-rw-r--r-- 1 mcc users 9.2M Jun 7 06:26 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME ResIsolation-PT-N08P2-LTLFireability-00
FORMULA_NAME ResIsolation-PT-N08P2-LTLFireability-01
FORMULA_NAME ResIsolation-PT-N08P2-LTLFireability-02
FORMULA_NAME ResIsolation-PT-N08P2-LTLFireability-03
FORMULA_NAME ResIsolation-PT-N08P2-LTLFireability-04
FORMULA_NAME ResIsolation-PT-N08P2-LTLFireability-05
FORMULA_NAME ResIsolation-PT-N08P2-LTLFireability-06
FORMULA_NAME ResIsolation-PT-N08P2-LTLFireability-07
FORMULA_NAME ResIsolation-PT-N08P2-LTLFireability-08
FORMULA_NAME ResIsolation-PT-N08P2-LTLFireability-09
FORMULA_NAME ResIsolation-PT-N08P2-LTLFireability-10
FORMULA_NAME ResIsolation-PT-N08P2-LTLFireability-11
FORMULA_NAME ResIsolation-PT-N08P2-LTLFireability-12
FORMULA_NAME ResIsolation-PT-N08P2-LTLFireability-13
FORMULA_NAME ResIsolation-PT-N08P2-LTLFireability-14
FORMULA_NAME ResIsolation-PT-N08P2-LTLFireability-15
=== Now, execution of the tool begins
BK_START 1717755712458
starting LoLA
BK_EXAMINATION: LTLFireability
BK_TIME_CONFINEMENT: 3600
BK_MEMORY_CONFINEMENT: 16384
BK_BIN_PATH: /home/mcc/BenchKit/bin/
current directory: /home/mcc/execution
FORMULA ResIsolation-PT-N08P2-LTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ResIsolation-PT-N08P2-LTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ResIsolation-PT-N08P2-LTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ResIsolation-PT-N08P2-LTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ResIsolation-PT-N08P2-LTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ResIsolation-PT-N08P2-LTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ResIsolation-PT-N08P2-LTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ResIsolation-PT-N08P2-LTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ResIsolation-PT-N08P2-LTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ResIsolation-PT-N08P2-LTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ResIsolation-PT-N08P2-LTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ResIsolation-PT-N08P2-LTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ResIsolation-PT-N08P2-LTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ResIsolation-PT-N08P2-LTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ResIsolation-PT-N08P2-LTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[[35mlola[0m] [1mFINAL RESULTS[0m
[[35mlola[0m] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m] [1m[32mResIsolation-PT-N08P2-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m] [1m[31mResIsolation-PT-N08P2-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mResIsolation-PT-N08P2-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mResIsolation-PT-N08P2-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mResIsolation-PT-N08P2-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m] [1m[32mResIsolation-PT-N08P2-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m] [1m[31mResIsolation-PT-N08P2-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m] [1m[33mResIsolation-PT-N08P2-LTLFireability-08: LTL unknown AGGR[0m
[[35mlola[0m] [1m[31mResIsolation-PT-N08P2-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mResIsolation-PT-N08P2-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m] [1m[32mResIsolation-PT-N08P2-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m] [1m[32mResIsolation-PT-N08P2-LTLFireability-15: LTL true LTL model checker[0m
[[35mlola[0m]
[[35mlola[0m] Time elapsed: 456 secs. Pages in use: 24
BK_STOP 1717756168546
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mLTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-11: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-12: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-11: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-12: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 15 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-11: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-12: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 20 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-11: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-12: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 25 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-11: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-12: F 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 30 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-11: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-12: F 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 35 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-11: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-12: F 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 40 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-11: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-12: F 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 45 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-11: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-12: F 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 50 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-11: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-12: F 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 55 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 42 (type EXCL) for 33 ResIsolation-PT-N08P2-LTLFireability-11
[[35mlola[0m][I] time limit : 196 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 60 (type EQUN) for 44 ResIsolation-PT-N08P2-LTLFireability-12
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 42 (type EXCL) for ResIsolation-PT-N08P2-LTLFireability-11
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 11
[[35mlola[0m][I] fired transitions : 11
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 57 (type EXCL) for 44 ResIsolation-PT-N08P2-LTLFireability-12
[[35mlola[0m][I] time limit : 236 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 57 (type EXCL) for ResIsolation-PT-N08P2-LTLFireability-12
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 60 (type EQUN) for ResIsolation-PT-N08P2-LTLFireability-12 (obsolete)
[[35mlola[0m][I] LAUNCH task # 51 (type EXCL) for 50 ResIsolation-PT-N08P2-LTLFireability-14
[[35mlola[0m][I] time limit : 253 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 51 (type EXCL) for ResIsolation-PT-N08P2-LTLFireability-14
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 14
[[35mlola[0m][I] fired transitions : 15
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 60 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 65 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 70 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 60 (type EQUN) for ResIsolation-PT-N08P2-LTLFireability-12
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] LAUNCH task # 10 (type EXCL) for 9 ResIsolation-PT-N08P2-LTLFireability-03
[[35mlola[0m][I] time limit : 271 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 10 (type EXCL) for ResIsolation-PT-N08P2-LTLFireability-03
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 13
[[35mlola[0m][I] fired transitions : 14
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 75 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 25 (type EXCL) for 24 ResIsolation-PT-N08P2-LTLFireability-08
[[35mlola[0m][I] time limit : 293 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 4/293 1/2000 ResIsolation-PT-N08P2-LTLFireability-08 30910 m, 6182 m/sec, 172269 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 80 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 9/293 1/2000 ResIsolation-PT-N08P2-LTLFireability-08 69721 m, 7762 m/sec, 406029 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 85 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 1 0 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 14/293 1/2000 ResIsolation-PT-N08P2-LTLFireability-08 104040 m, 6863 m/sec, 635620 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 90 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 19/293 2/2000 ResIsolation-PT-N08P2-LTLFireability-08 149698 m, 9131 m/sec, 946464 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 95 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 24/293 2/2000 ResIsolation-PT-N08P2-LTLFireability-08 194072 m, 8874 m/sec, 1221702 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 100 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 29/293 2/2000 ResIsolation-PT-N08P2-LTLFireability-08 243438 m, 9873 m/sec, 1767014 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 105 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 34/293 2/2000 ResIsolation-PT-N08P2-LTLFireability-08 288050 m, 8922 m/sec, 2340546 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 110 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 39/293 3/2000 ResIsolation-PT-N08P2-LTLFireability-08 331444 m, 8678 m/sec, 2975023 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 115 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 44/293 3/2000 ResIsolation-PT-N08P2-LTLFireability-08 378131 m, 9337 m/sec, 3505106 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 120 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 49/293 3/2000 ResIsolation-PT-N08P2-LTLFireability-08 427908 m, 9955 m/sec, 3925625 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 125 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 54/293 4/2000 ResIsolation-PT-N08P2-LTLFireability-08 478964 m, 10211 m/sec, 4256573 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 130 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 59/293 4/2000 ResIsolation-PT-N08P2-LTLFireability-08 527503 m, 9707 m/sec, 4579613 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 135 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 64/293 4/2000 ResIsolation-PT-N08P2-LTLFireability-08 574089 m, 9317 m/sec, 4912502 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 140 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 69/293 5/2000 ResIsolation-PT-N08P2-LTLFireability-08 619349 m, 9052 m/sec, 5247322 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 145 secs. Pages in use: 5
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[*** LOG ERROR #0001 ***] [2024-06-07 10:24:18] [status_logger] string pointer is null
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 74/293 5/2000 ResIsolation-PT-N08P2-LTLFireability-08 665111 m, 9152 m/sec, 5641045 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 150 secs. Pages in use: 5
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 79/293 5/2000 ResIsolation-PT-N08P2-LTLFireability-08 710619 m, 9101 m/sec, 6056038 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 155 secs. Pages in use: 5
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 84/293 6/2000 ResIsolation-PT-N08P2-LTLFireability-08 755905 m, 9057 m/sec, 6482908 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 160 secs. Pages in use: 6
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 89/293 6/2000 ResIsolation-PT-N08P2-LTLFireability-08 804952 m, 9809 m/sec, 6936152 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 165 secs. Pages in use: 6
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 94/293 6/2000 ResIsolation-PT-N08P2-LTLFireability-08 852762 m, 9562 m/sec, 7356632 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 170 secs. Pages in use: 6
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 99/293 6/2000 ResIsolation-PT-N08P2-LTLFireability-08 900482 m, 9544 m/sec, 7774480 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 175 secs. Pages in use: 6
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 104/293 7/2000 ResIsolation-PT-N08P2-LTLFireability-08 948334 m, 9570 m/sec, 8204476 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 180 secs. Pages in use: 7
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 109/293 7/2000 ResIsolation-PT-N08P2-LTLFireability-08 994734 m, 9280 m/sec, 8605527 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 185 secs. Pages in use: 7
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 114/293 7/2000 ResIsolation-PT-N08P2-LTLFireability-08 1041400 m, 9333 m/sec, 8985407 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 190 secs. Pages in use: 7
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 119/293 8/2000 ResIsolation-PT-N08P2-LTLFireability-08 1087909 m, 9301 m/sec, 9350814 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 195 secs. Pages in use: 8
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 124/293 8/2000 ResIsolation-PT-N08P2-LTLFireability-08 1135119 m, 9442 m/sec, 9723225 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 200 secs. Pages in use: 8
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 129/293 8/2000 ResIsolation-PT-N08P2-LTLFireability-08 1180261 m, 9028 m/sec, 10131803 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 205 secs. Pages in use: 8
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 134/293 9/2000 ResIsolation-PT-N08P2-LTLFireability-08 1226399 m, 9227 m/sec, 10556162 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 210 secs. Pages in use: 9
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 139/293 9/2000 ResIsolation-PT-N08P2-LTLFireability-08 1274065 m, 9533 m/sec, 10972729 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 215 secs. Pages in use: 9
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 144/293 9/2000 ResIsolation-PT-N08P2-LTLFireability-08 1321349 m, 9456 m/sec, 11340686 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 220 secs. Pages in use: 9
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 149/293 10/2000 ResIsolation-PT-N08P2-LTLFireability-08 1367475 m, 9225 m/sec, 11718228 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 225 secs. Pages in use: 10
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 154/293 10/2000 ResIsolation-PT-N08P2-LTLFireability-08 1415093 m, 9523 m/sec, 12114241 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 230 secs. Pages in use: 10
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 159/293 10/2000 ResIsolation-PT-N08P2-LTLFireability-08 1462213 m, 9424 m/sec, 12481493 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 235 secs. Pages in use: 10
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 164/293 11/2000 ResIsolation-PT-N08P2-LTLFireability-08 1509555 m, 9468 m/sec, 12846283 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 240 secs. Pages in use: 11
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 169/293 11/2000 ResIsolation-PT-N08P2-LTLFireability-08 1556374 m, 9363 m/sec, 13220368 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 245 secs. Pages in use: 11
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 174/293 11/2000 ResIsolation-PT-N08P2-LTLFireability-08 1602808 m, 9286 m/sec, 13584679 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 250 secs. Pages in use: 11
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 179/293 11/2000 ResIsolation-PT-N08P2-LTLFireability-08 1647714 m, 8981 m/sec, 13968470 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 255 secs. Pages in use: 11
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 184/293 12/2000 ResIsolation-PT-N08P2-LTLFireability-08 1693875 m, 9232 m/sec, 14354936 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 260 secs. Pages in use: 12
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 189/293 12/2000 ResIsolation-PT-N08P2-LTLFireability-08 1741177 m, 9460 m/sec, 14706069 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 265 secs. Pages in use: 12
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 194/293 12/2000 ResIsolation-PT-N08P2-LTLFireability-08 1787355 m, 9235 m/sec, 15049166 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 270 secs. Pages in use: 12
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 199/293 13/2000 ResIsolation-PT-N08P2-LTLFireability-08 1832330 m, 8995 m/sec, 15439454 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 275 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 204/293 13/2000 ResIsolation-PT-N08P2-LTLFireability-08 1877478 m, 9029 m/sec, 15851595 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 280 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 209/293 13/2000 ResIsolation-PT-N08P2-LTLFireability-08 1922840 m, 9072 m/sec, 16267084 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 285 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 214/293 14/2000 ResIsolation-PT-N08P2-LTLFireability-08 1969404 m, 9312 m/sec, 16684903 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 290 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 219/293 14/2000 ResIsolation-PT-N08P2-LTLFireability-08 2015429 m, 9205 m/sec, 17094899 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 295 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 224/293 14/2000 ResIsolation-PT-N08P2-LTLFireability-08 2060988 m, 9111 m/sec, 17510488 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 300 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 229/293 15/2000 ResIsolation-PT-N08P2-LTLFireability-08 2106420 m, 9086 m/sec, 17935725 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 305 secs. Pages in use: 15
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 234/293 15/2000 ResIsolation-PT-N08P2-LTLFireability-08 2152882 m, 9292 m/sec, 18359436 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 310 secs. Pages in use: 15
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 239/293 15/2000 ResIsolation-PT-N08P2-LTLFireability-08 2200730 m, 9569 m/sec, 18792229 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 315 secs. Pages in use: 15
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 244/293 16/2000 ResIsolation-PT-N08P2-LTLFireability-08 2247301 m, 9314 m/sec, 19212365 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 320 secs. Pages in use: 16
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 249/293 16/2000 ResIsolation-PT-N08P2-LTLFireability-08 2293416 m, 9223 m/sec, 19628557 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 325 secs. Pages in use: 16
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 254/293 16/2000 ResIsolation-PT-N08P2-LTLFireability-08 2342309 m, 9778 m/sec, 20049028 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 330 secs. Pages in use: 16
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 259/293 16/2000 ResIsolation-PT-N08P2-LTLFireability-08 2389126 m, 9363 m/sec, 20441096 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 335 secs. Pages in use: 16
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 264/293 17/2000 ResIsolation-PT-N08P2-LTLFireability-08 2435045 m, 9183 m/sec, 20841344 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 340 secs. Pages in use: 17
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 269/293 17/2000 ResIsolation-PT-N08P2-LTLFireability-08 2482792 m, 9549 m/sec, 21237081 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 345 secs. Pages in use: 17
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 274/293 17/2000 ResIsolation-PT-N08P2-LTLFireability-08 2530018 m, 9445 m/sec, 21619703 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 350 secs. Pages in use: 17
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 279/293 18/2000 ResIsolation-PT-N08P2-LTLFireability-08 2576208 m, 9238 m/sec, 21973504 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 355 secs. Pages in use: 18
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 284/293 18/2000 ResIsolation-PT-N08P2-LTLFireability-08 2622209 m, 9200 m/sec, 22345788 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 360 secs. Pages in use: 18
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 289/293 18/2000 ResIsolation-PT-N08P2-LTLFireability-08 2668175 m, 9193 m/sec, 22751515 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 365 secs. Pages in use: 18
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 25 (type EXCL) for ResIsolation-PT-N08P2-LTLFireability-08 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 370 secs. Pages in use: 19
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 54 (type EXCL) for 53 ResIsolation-PT-N08P2-LTLFireability-15
[[35mlola[0m][I] time limit : 293 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 25 (type EXCL) for 24 ResIsolation-PT-N08P2-LTLFireability-08
[[35mlola[0m][I] time limit : 3230 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 54 (type EXCL) for ResIsolation-PT-N08P2-LTLFireability-15
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 2
[[35mlola[0m][I] fired transitions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 5/293 1/5 ResIsolation-PT-N08P2-LTLFireability-08 52206 m, -523193 m/sec, 296923 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 375 secs. Pages in use: 20
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 10/293 1/5 ResIsolation-PT-N08P2-LTLFireability-08 98286 m, 9216 m/sec, 595158 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 380 secs. Pages in use: 20
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 15/293 2/5 ResIsolation-PT-N08P2-LTLFireability-08 146908 m, 9724 m/sec, 932138 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 385 secs. Pages in use: 21
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 20/293 2/5 ResIsolation-PT-N08P2-LTLFireability-08 194910 m, 9600 m/sec, 1228437 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 390 secs. Pages in use: 21
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 25/293 2/5 ResIsolation-PT-N08P2-LTLFireability-08 244576 m, 9933 m/sec, 1781360 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 395 secs. Pages in use: 21
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 30/293 2/5 ResIsolation-PT-N08P2-LTLFireability-08 289606 m, 9006 m/sec, 2360318 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 400 secs. Pages in use: 21
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 35/293 3/5 ResIsolation-PT-N08P2-LTLFireability-08 332663 m, 8611 m/sec, 2988544 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 405 secs. Pages in use: 22
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 40/293 3/5 ResIsolation-PT-N08P2-LTLFireability-08 376776 m, 8822 m/sec, 3485504 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 410 secs. Pages in use: 22
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 45/293 3/5 ResIsolation-PT-N08P2-LTLFireability-08 422763 m, 9197 m/sec, 3897582 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 415 secs. Pages in use: 22
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 50/293 4/5 ResIsolation-PT-N08P2-LTLFireability-08 470915 m, 9630 m/sec, 4209158 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 420 secs. Pages in use: 23
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 55/293 4/5 ResIsolation-PT-N08P2-LTLFireability-08 517047 m, 9226 m/sec, 4513454 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 425 secs. Pages in use: 23
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 60/293 4/5 ResIsolation-PT-N08P2-LTLFireability-08 561200 m, 8830 m/sec, 4813692 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 430 secs. Pages in use: 23
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 65/293 4/5 ResIsolation-PT-N08P2-LTLFireability-08 604553 m, 8670 m/sec, 5131869 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 435 secs. Pages in use: 23
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 70/293 5/5 ResIsolation-PT-N08P2-LTLFireability-08 647451 m, 8579 m/sec, 5483465 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 440 secs. Pages in use: 24
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 75/293 5/5 ResIsolation-PT-N08P2-LTLFireability-08 689655 m, 8440 m/sec, 5863077 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 445 secs. Pages in use: 24
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 80/293 5/5 ResIsolation-PT-N08P2-LTLFireability-08 731863 m, 8441 m/sec, 6258005 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 450 secs. Pages in use: 24
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 25 (type EXCL) for ResIsolation-PT-N08P2-LTLFireability-08 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-12: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mResIsolation-PT-N08P2-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResIsolation-PT-N08P2-LTLFireability-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResIsolation-PT-N08P2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 455 secs. Pages in use: 24
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 48 (type EXCL) for 47 ResIsolation-PT-N08P2-LTLFireability-13
[[35mlola[0m][I] time limit : 314 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 48 (type EXCL) for ResIsolation-PT-N08P2-LTLFireability-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 3
[[35mlola[0m][I] fired transitions : 2
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 31 (type EXCL) for 30 ResIsolation-PT-N08P2-LTLFireability-10
[[35mlola[0m][I] time limit : 349 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 31 (type EXCL) for ResIsolation-PT-N08P2-LTLFireability-10
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 34
[[35mlola[0m][I] fired transitions : 34
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 28 (type EXCL) for 27 ResIsolation-PT-N08P2-LTLFireability-09
[[35mlola[0m][I] time limit : 393 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 28 (type EXCL) for ResIsolation-PT-N08P2-LTLFireability-09
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 34
[[35mlola[0m][I] fired transitions : 34
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 22 (type EXCL) for 21 ResIsolation-PT-N08P2-LTLFireability-07
[[35mlola[0m][I] time limit : 449 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 22 (type EXCL) for ResIsolation-PT-N08P2-LTLFireability-07
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 34
[[35mlola[0m][I] fired transitions : 34
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 19 (type EXCL) for 18 ResIsolation-PT-N08P2-LTLFireability-06
[[35mlola[0m][I] time limit : 524 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 19 (type EXCL) for ResIsolation-PT-N08P2-LTLFireability-06
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 16 (type EXCL) for 15 ResIsolation-PT-N08P2-LTLFireability-05
[[35mlola[0m][I] time limit : 629 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 16 (type EXCL) for ResIsolation-PT-N08P2-LTLFireability-05
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 34
[[35mlola[0m][I] fired transitions : 34
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 13 (type EXCL) for 12 ResIsolation-PT-N08P2-LTLFireability-04
[[35mlola[0m][I] time limit : 786 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 13 (type EXCL) for ResIsolation-PT-N08P2-LTLFireability-04
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 34
[[35mlola[0m][I] fired transitions : 34
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 7 (type EXCL) for 6 ResIsolation-PT-N08P2-LTLFireability-02
[[35mlola[0m][I] time limit : 1048 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 7 (type EXCL) for ResIsolation-PT-N08P2-LTLFireability-02
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 34
[[35mlola[0m][I] fired transitions : 34
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 4 (type EXCL) for 3 ResIsolation-PT-N08P2-LTLFireability-01
[[35mlola[0m][I] time limit : 1572 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 4 (type EXCL) for ResIsolation-PT-N08P2-LTLFireability-01
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 3245
[[35mlola[0m][I] fired transitions : 6865
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 1 (type EXCL) for 0 ResIsolation-PT-N08P2-LTLFireability-00
[[35mlola[0m][I] time limit : 3144 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 1 (type EXCL) for ResIsolation-PT-N08P2-LTLFireability-00
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 2
[[35mlola[0m][I] fired transitions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] Portfolio finished: no open tasks 16
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ResIsolation-PT-N08P2"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is ResIsolation-PT-N08P2, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r629-smll-171774446200012"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/ResIsolation-PT-N08P2.tgz
mv ResIsolation-PT-N08P2 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;