Execution Chart

Sorry, for this execution, no execution chart could be reported.

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r616-tall-171774433100186.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool ltsminxred
Input is BlocksWorld-PT-18, examination is ReachabilityDeadlock
Time confinement is 1800 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r616-tall-171774433100186
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 125M
-rw-r--r-- 1 mcc users 3.1M Jun 7 06:38 CTLCardinality.txt
-rw-r--r-- 1 mcc users 15M Jun 7 06:38 CTLCardinality.xml
-rw-r--r-- 1 mcc users 1.9M Jun 7 06:38 CTLFireability.txt
-rw-r--r-- 1 mcc users 8.9M Jun 7 06:38 CTLFireability.xml
-rw-r--r-- 1 mcc users 58K Jun 7 06:44 LTLCardinality.txt
-rw-r--r-- 1 mcc users 172K Jun 7 06:44 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2M Jun 7 06:44 LTLFireability.txt
-rw-r--r-- 1 mcc users 8.4M Jun 7 06:44 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 Jun 7 06:26 NewModel
-rw-r--r-- 1 mcc users 8.3M Jun 7 06:39 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 38M Jun 7 06:39 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 5.1M Jun 7 06:39 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 27M Jun 7 06:39 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 135K Jun 7 06:43 UpperBounds.txt
-rw-r--r-- 1 mcc users 321K Jun 7 06:43 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Jun 7 06:26 equiv_col
-rw-r--r-- 1 mcc users 3 Jun 7 06:26 instance
-rw-r--r-- 1 mcc users 6 Jun 7 06:26 iscolored
-rw-r--r-- 1 mcc users 8.3M Jun 7 06:26 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

FORMULA_NAME ReachabilityDeadlock

=== Now, execution of the tool begins

BK_START 1717778546768

Invoking MCC driver with
BK_TOOL=ltsminxred
BK_EXAMINATION=ReachabilityDeadlock
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=1800
BK_INPUT=BlocksWorld-PT-18
BK_MEMORY_CONFINEMENT=16384
Applying reductions before tool ltsmin
Invoking reducer
Running Version 202405141337
[2024-06-07 16:42:27] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityDeadlock, -timeout, 180, -rebuildPNML]
[2024-06-07 16:42:27] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2024-06-07 16:42:28] [INFO ] Load time of PNML (sax parser for PT used): 537 ms
[2024-06-07 16:42:28] [INFO ] Transformed 8741 places.
[2024-06-07 16:42:28] [INFO ] Transformed 17113 transitions.
[2024-06-07 16:42:28] [INFO ] Found NUPN structural information;
[2024-06-07 16:42:28] [INFO ] Completing missing partition info from NUPN : creating a component with [pred_on_table_0, pred_arm_empty_0, pred_on_table_1, pred_on_table_2, pred_on_table_3, pred_on_table_4, pred_on_table_5, pred_on_table_6, pred_on_table_7, pred_on_table_8, pred_on_table_9, pred_on_table_10, pred_on_table_11, pred_on_table_12, pred_on_table_13, pred_on_table_14, pred_on_table_15, pred_on_table_16, pred_on_table_17, pred_on_table_18, pred_on_table_19, pred_on_table_20, pred_on_table_21, pred_on_table_22, pred_on_table_23, pred_on_table_24, pred_on_table_25, pred_on_table_26, pred_on_table_27, pred_on_table_28, pred_on_table_29, pred_on_table_30, pred_on_table_31, pred_on_table_32, pred_on_table_33, pred_on_table_34, pred_on_table_35, pred_on_table_36, pred_on_table_37, pred_on_table_38, pred_on_table_39, pred_on_table_40, pred_on_table_41, pred_on_table_42, pred_on_table_43, pred_on_table_44, pred_on_table_45, pred_on_table_46, pred_on_table_47, pred_on_table_48, pred_on_table_49, pred_on_table_50, pred_on_table_51, pred_on_table_52, pred_on_table_53, pred_on_table_54, pred_on_table_55, pred_on_table_56, pred_on_table_57, pred_on_table_58, pred_on_table_59, pred_on_table_60, pred_on_table_61, pred_on_table_62, pred_on_table_63, pred_on_table_64, pred_on_table_65, pred_on_table_66, pred_on_table_67, pred_on_table_68, pred_on_table_69, pred_on_table_70, pred_on_table_71, pred_on_table_72, pred_on_table_73, pred_on_table_74, pred_on_table_75, pred_on_table_76, pred_on_table_77, pred_on_table_78, pred_on_table_79, pred_on_table_80, pred_on_table_81, pred_on_table_82, pred_on_table_83, pred_on_table_84, pred_on_table_85, pred_on_table_86, pred_on_table_87, pred_on_table_88, pred_on_table_89, pred_on_table_90, pred_on_table_91]
[2024-06-07 16:42:28] [INFO ] Parsed PT model containing 8741 places and 17113 transitions and 85538 arcs in 750 ms.
Parsed 1 properties from file /home/mcc/execution/ReachabilityDeadlock.xml in 4 ms.
Working with output stream class java.io.PrintStream
Built sparse matrix representations for Structural reductions in 13 ms.63689KB memory used
Starting structural reductions in DEADLOCK mode, iteration 0 : 8741/8741 places, 17113/17113 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Computed a total of 0 stabilizing places and 0 stable transitions
Computed a total of 0 stabilizing places and 0 stable transitions
Applied a total of 0 rules in 6894 ms. Remains 8741 /8741 variables (removed 0) and now considering 17113/17113 (removed 0) transitions.
Finished structural reductions in DEADLOCK mode , in 1 iterations and 6914 ms. Remains : 8741/8741 places, 17113/17113 transitions.
Starting structural reductions in DEADLOCK mode, iteration 0 : 8741/8741 places, 17113/17113 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Computed a total of 0 stabilizing places and 0 stable transitions
Computed a total of 0 stabilizing places and 0 stable transitions
Applied a total of 0 rules in 6473 ms. Remains 8741 /8741 variables (removed 0) and now considering 17113/17113 (removed 0) transitions.
// Phase 1: matrix 17113 rows 8741 cols
[2024-06-07 16:42:42] [INFO ] Computed 185 invariants in 205 ms
[2024-06-07 16:42:55] [INFO ] Implicit Places using invariants in 13495 ms returned []
Implicit Place search using SMT only with invariants took 13532 ms to find 0 implicit places.
Running 17102 sub problems to find dead transitions.
[2024-06-07 16:42:56] [INFO ] Invariant cache hit.
[2024-06-07 16:42:56] [INFO ] State equation strengthened by 163 read => feed constraints.
Problem TDEAD1 is UNSAT
Problem TDEAD93 is UNSAT
Problem TDEAD277 is UNSAT
Problem TDEAD370 is UNSAT
Problem TDEAD463 is UNSAT
Problem TDEAD556 is UNSAT
Problem TDEAD649 is UNSAT
Problem TDEAD742 is UNSAT
Problem TDEAD928 is UNSAT
Problem TDEAD1021 is UNSAT
Problem TDEAD1114 is UNSAT
Problem TDEAD1207 is UNSAT
Problem TDEAD1393 is UNSAT
Problem TDEAD1486 is UNSAT
Problem TDEAD1579 is UNSAT
Problem TDEAD1672 is UNSAT
Problem TDEAD1765 is UNSAT
Problem TDEAD1858 is UNSAT
Problem TDEAD1951 is UNSAT
Problem TDEAD2044 is UNSAT
Problem TDEAD2137 is UNSAT
Problem TDEAD2230 is UNSAT
Problem TDEAD2416 is UNSAT
Problem TDEAD2509 is UNSAT
Problem TDEAD2602 is UNSAT
Problem TDEAD2695 is UNSAT
Problem TDEAD2788 is UNSAT
Problem TDEAD2881 is UNSAT
Problem TDEAD2974 is UNSAT
Problem TDEAD3067 is UNSAT
Problem TDEAD3160 is UNSAT
Problem TDEAD3253 is UNSAT
Problem TDEAD3439 is UNSAT
Problem TDEAD3532 is UNSAT
Problem TDEAD3625 is UNSAT
Problem TDEAD3718 is UNSAT
Problem TDEAD3811 is UNSAT
Problem TDEAD3904 is UNSAT
Problem TDEAD3997 is UNSAT
Problem TDEAD4090 is UNSAT
Problem TDEAD4183 is UNSAT
Problem TDEAD4276 is UNSAT
Problem TDEAD4369 is UNSAT
Problem TDEAD4462 is UNSAT
Problem TDEAD4555 is UNSAT
Problem TDEAD4741 is UNSAT
Problem TDEAD4834 is UNSAT
Problem TDEAD4927 is UNSAT
Problem TDEAD5020 is UNSAT
Problem TDEAD5113 is UNSAT
Problem TDEAD5206 is UNSAT
Problem TDEAD5299 is UNSAT
Problem TDEAD5485 is UNSAT
Problem TDEAD5578 is UNSAT
Problem TDEAD5671 is UNSAT
Problem TDEAD5764 is UNSAT
Problem TDEAD5857 is UNSAT
Problem TDEAD5950 is UNSAT
Problem TDEAD6136 is UNSAT
Problem TDEAD6229 is UNSAT
Problem TDEAD6322 is UNSAT
Problem TDEAD6415 is UNSAT
Problem TDEAD6508 is UNSAT
Problem TDEAD6601 is UNSAT
Problem TDEAD6694 is UNSAT
Problem TDEAD6787 is UNSAT
Problem TDEAD6880 is UNSAT
Problem TDEAD6973 is UNSAT
Problem TDEAD7066 is UNSAT
Problem TDEAD7159 is UNSAT
Problem TDEAD7252 is UNSAT
Problem TDEAD7345 is UNSAT
Problem TDEAD7438 is UNSAT
Problem TDEAD7531 is UNSAT
Problem TDEAD7624 is UNSAT
Problem TDEAD7717 is UNSAT
Problem TDEAD7810 is UNSAT
Problem TDEAD8182 is UNSAT
Problem TDEAD8275 is UNSAT
Problem TDEAD8461 is UNSAT
Problem TDEAD8554 is UNSAT
Problem TDEAD8647 is UNSAT
Problem TDEAD8740 is UNSAT
Problem TDEAD8922 is UNSAT
Problem TDEAD9102 is UNSAT
Problem TDEAD9280 is UNSAT
Problem TDEAD9456 is UNSAT
Problem TDEAD9630 is UNSAT
Problem TDEAD9972 is UNSAT
Problem TDEAD10140 is UNSAT
Problem TDEAD10306 is UNSAT
Problem TDEAD10470 is UNSAT
Problem TDEAD10792 is UNSAT
Problem TDEAD10950 is UNSAT
Problem TDEAD11106 is UNSAT
Problem TDEAD11260 is UNSAT
Problem TDEAD11412 is UNSAT
Problem TDEAD11562 is UNSAT
Problem TDEAD11710 is UNSAT
Problem TDEAD11856 is UNSAT
Problem TDEAD12000 is UNSAT
Problem TDEAD12142 is UNSAT
Problem TDEAD12420 is UNSAT
Problem TDEAD12556 is UNSAT
Problem TDEAD12690 is UNSAT
Problem TDEAD12822 is UNSAT
Problem TDEAD12952 is UNSAT
Problem TDEAD13080 is UNSAT
Problem TDEAD13206 is UNSAT
Problem TDEAD13330 is UNSAT
Problem TDEAD13452 is UNSAT
Problem TDEAD13572 is UNSAT
Problem TDEAD13806 is UNSAT
Problem TDEAD13920 is UNSAT
Problem TDEAD14032 is UNSAT
Problem TDEAD14142 is UNSAT
Problem TDEAD14250 is UNSAT
Problem TDEAD14356 is UNSAT
Problem TDEAD14460 is UNSAT
Problem TDEAD14562 is UNSAT
Problem TDEAD14662 is UNSAT
Problem TDEAD14760 is UNSAT
Problem TDEAD14856 is UNSAT
Problem TDEAD14950 is UNSAT
Problem TDEAD15042 is UNSAT
Problem TDEAD15220 is UNSAT
Problem TDEAD15306 is UNSAT
Problem TDEAD15390 is UNSAT
Problem TDEAD15472 is UNSAT
Problem TDEAD15552 is UNSAT
Problem TDEAD15630 is UNSAT
Problem TDEAD15706 is UNSAT
Problem TDEAD15852 is UNSAT
Problem TDEAD15922 is UNSAT
Problem TDEAD15990 is UNSAT
Problem TDEAD16056 is UNSAT
Problem TDEAD16120 is UNSAT
Problem TDEAD16182 is UNSAT
Problem TDEAD16300 is UNSAT
Problem TDEAD16356 is UNSAT
Problem TDEAD16410 is UNSAT
Problem TDEAD16462 is UNSAT
Problem TDEAD16512 is UNSAT
Problem TDEAD16560 is UNSAT
Problem TDEAD16606 is UNSAT
Problem TDEAD16650 is UNSAT
Problem TDEAD16692 is UNSAT
Problem TDEAD16732 is UNSAT
Problem TDEAD16770 is UNSAT
Problem TDEAD16806 is UNSAT
Problem TDEAD16840 is UNSAT
Problem TDEAD16872 is UNSAT
Problem TDEAD16902 is UNSAT
Problem TDEAD16930 is UNSAT
Problem TDEAD16956 is UNSAT
Problem TDEAD16980 is UNSAT
Problem TDEAD17002 is UNSAT
Problem TDEAD17070 is UNSAT
Problem TDEAD17082 is UNSAT
Problem TDEAD17100 is UNSAT
Problem TDEAD17106 is UNSAT
Problem TDEAD17110 is UNSAT
Error getting values : (error "ParserException while parsing response: (timeout
org.smtlib.IParser$ParserException: Unbalanced parentheses at end of input")
At refinement iteration 0 (INCLUDED_ONLY) 0/8730 variables, 163/163 constraints. Problems are: Problem set: 162 solved, 16940 unsolved
Solver is answering 'unknown', stopping.
After SMT solving in domain Real declared 8730/25854 variables, and 163 constraints, problems are : Problem set: 162 solved, 16940 unsolved in 30286 ms.
Refiners :[Positive P Invariants (semi-flows): 163/185 constraints, State Equation: 0/8741 constraints, ReadFeed: 0/163 constraints, PredecessorRefiner: 17021/8557 constraints, Known Traps: 0/0 constraints]
Escalating to Integer solving :Problem set: 162 solved, 16940 unsolved
At refinement iteration 0 (INCLUDED_ONLY) 0/8649 variables, 12/12 constraints. Problems are: Problem set: 162 solved, 16940 unsolved
Error getting values : (error "ParserException while parsing response: (timeout
org.smtlib.IParser$ParserException: Unbalanced parentheses at end of input")
Solver is answering 'unknown', stopping.
After SMT solving in domain Int declared 8649/25854 variables, and 12 constraints, problems are : Problem set: 162 solved, 16940 unsolved in 30209 ms.
Refiners :[Positive P Invariants (semi-flows): 12/185 constraints, State Equation: 0/8741 constraints, ReadFeed: 0/163 constraints, PredecessorRefiner: 8464/8557 constraints, Known Traps: 0/0 constraints]
After SMT, in 265087ms problems are : Problem set: 162 solved, 16940 unsolved
Search for dead transitions found 162 dead transitions in 265299ms
Found 162 dead transitions using SMT.
Drop transitions (Dead Transitions using SMT only with invariants) removed 162 transitions
Dead transitions reduction (with SMT) removed 162 transitions
Starting structural reductions in DEADLOCK mode, iteration 1 : 8741/8741 places, 16951/17113 transitions.
Computed a total of 81 stabilizing places and 0 stable transitions
Graph (complete) has 49212 edges and 8741 vertex of which 8660 are kept as prefixes of interest. Removing 81 places using SCC suffix rule.42 ms
Discarding 81 places :
Also discarding 0 output transitions
Computed a total of 0 stabilizing places and 0 stable transitions
Computed a total of 0 stabilizing places and 0 stable transitions
Applied a total of 1 rules in 7372 ms. Remains 8660 /8741 variables (removed 81) and now considering 16951/16951 (removed 0) transitions.
// Phase 1: matrix 16951 rows 8660 cols
[2024-06-07 16:47:28] [INFO ] Computed 185 invariants in 128 ms
[2024-06-07 16:47:41] [INFO ] Implicit Places using invariants in 12515 ms returned []
Implicit Place search using SMT only with invariants took 12516 ms to find 0 implicit places.
Starting structural reductions in DEADLOCK mode, iteration 2 : 8660/8741 places, 16951/17113 transitions.
Finished structural reductions in DEADLOCK mode , in 2 iterations and 305274 ms. Remains : 8660/8741 places, 16951/17113 transitions.
Interrupted Random walk after 176156 steps, including 0 resets, run timeout after 30001 ms. (steps per millisecond=5 )
Interrupted Random directed walk after 232014 steps, including 0 resets, run timeout after 30001 ms. (steps per millisecond=7 )
[2024-06-07 16:48:41] [INFO ] Invariant cache hit.
[2024-06-07 16:49:05] [INFO ] [Real]Absence check using 185 positive place invariants in 11948 ms returned sat
[2024-06-07 16:53:41] [INFO ] [Real]Absence check using state equation in 275923 ms returned unknown
Interrupted Random directed walk after 226203 steps, including 0 resets, run timeout after 30001 ms. (steps per millisecond=7 )
Interrupted Random walk after 182508 steps, including 0 resets, run timeout after 30001 ms. (steps per millisecond=6 )
Interrupted Random directed walk after 228127 steps, including 0 resets, run timeout after 30002 ms. (steps per millisecond=7 )
Interrupted Random walk after 168078 steps, including 0 resets, run timeout after 30001 ms. (steps per millisecond=5 )
Starting structural reductions in DEADLOCK mode, iteration 0 : 8660/8660 places, 16951/16951 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Computed a total of 0 stabilizing places and 0 stable transitions
Computed a total of 0 stabilizing places and 0 stable transitions
Applied a total of 0 rules in 7582 ms. Remains 8660 /8660 variables (removed 0) and now considering 16951/16951 (removed 0) transitions.
[2024-06-07 16:55:48] [INFO ] Invariant cache hit.
[2024-06-07 16:56:01] [INFO ] Implicit Places using invariants in 12647 ms returned []
Implicit Place search using SMT only with invariants took 12650 ms to find 0 implicit places.
Running 16940 sub problems to find dead transitions.
[2024-06-07 16:56:01] [INFO ] Invariant cache hit.
[2024-06-07 16:56:01] [INFO ] State equation strengthened by 23 read => feed constraints.
Usage: pnml2lts-sym [-gvqh] [--order=]
[--mu-opt] [--saturation=]
[--sat-granularity=] [--save-sat-levels]
[--guidance=] [-d|--deadlock]
[--action=] [-i|--invariant=STRING] [-n|--no-exit]
[--trace=] [--type=]
[--mu=.mu] [--ctl-star=.ctl]
[--ctl=.ctl] [--ltl=.ltl] [--dot=STRING]
[--save-levels=STRING] [--pg-solve] [--attr=]
[--saturating-attractor] [--write-strategy=.spg]
[--check-strategy] [--interactive-play] [--player]
[--pg-write=.spg] [--no-matrix] [--noack=<1|2>]
[--edge-label=] [--labels] [-m|--matrix]
[--mucalc=.mcf|] [-c|--cache]
[--allow-undefined-edges] [--allow-undefined-values]
[-p|--por= (default: heur)]
[--weak=[valmari] (default: uses stronger left-commutativity)]
[--leap] [-r|--regroup=<(T,)+>] [--sloan-w1=] [--sloan-w2=]
[--cw-max-cols=] [--cw-max-rows=] [--col-ins=<(C.C',)+>]
[--mh-timeout=] [--row-perm=<(R,)+>] [--col-perm=<(C,)+>]
[--graph-metrics] [--regroup-exit] [--regroup-time]
[-g|--pins-guards] [--vset=] [--ldd32-step=]
[--ldd32-cache=] [--ldd-step=] [--ldd-cache=]
[--cache-ratio=] [--max-increase=]
[--min-free-nodes=] [--fdd-bits=]
[--fdd-reorder=]
[--vset-cache-diff=] [--no-soundness-check] [--precise]
[--next-union] [--peak-nodes] [--maxsum=]
[--block-size=] [--cluster-size=] [-v] [-q]
[--debug=] [--stats] [--where] [--when]
[--timeout=INT] [--version] [-h|--help] [--usage]
[OPTIONS] []
Could not compute solution for formula : ReachabilityDeadlock

BK_STOP 1717779517890

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202405141337.jar
+ VERSION=202405141337
+ echo 'Running Version 202405141337'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination ReachabilityDeadlock -timeout 180 -rebuildPNML
mcc2024
property name is ReachabilityDeadlock
pnml2lts-sym, ** error **: unknown vector set implementation lddmc

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="BlocksWorld-PT-18"
export BK_EXAMINATION="ReachabilityDeadlock"
export BK_TOOL="ltsminxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="1800"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool ltsminxred"
echo " Input is BlocksWorld-PT-18, examination is ReachabilityDeadlock"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r616-tall-171774433100186"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/BlocksWorld-PT-18.tgz
mv BlocksWorld-PT-18 execution
cd execution
if [ "ReachabilityDeadlock" = "ReachabilityDeadlock" ] || [ "ReachabilityDeadlock" = "UpperBounds" ] || [ "ReachabilityDeadlock" = "QuasiLiveness" ] || [ "ReachabilityDeadlock" = "StableMarking" ] || [ "ReachabilityDeadlock" = "Liveness" ] || [ "ReachabilityDeadlock" = "OneSafe" ] || [ "ReachabilityDeadlock" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityDeadlock" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityDeadlock" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityDeadlock.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityDeadlock.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityDeadlock.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityDeadlock.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "ReachabilityDeadlock" = "ReachabilityDeadlock" ] || [ "ReachabilityDeadlock" = "QuasiLiveness" ] || [ "ReachabilityDeadlock" = "StableMarking" ] || [ "ReachabilityDeadlock" = "Liveness" ] || [ "ReachabilityDeadlock" = "OneSafe" ] ; then
echo "FORMULA_NAME ReachabilityDeadlock"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;