About the Execution of LoLA for MedleyA-PT-17
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
4896.039 | 3600000.00 | 446906.00 | 12991.00 | ??F?FFFFFF?????F | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r577-smll-171734920500132.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
..............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is MedleyA-PT-17, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r577-smll-171734920500132
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 580K
-rw-r--r-- 1 mcc users 6.7K Jun 2 17:16 CTLCardinality.txt
-rw-r--r-- 1 mcc users 77K Jun 2 17:16 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.2K Jun 2 17:16 CTLFireability.txt
-rw-r--r-- 1 mcc users 59K Jun 2 17:16 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.3K Jun 2 17:12 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Jun 2 17:12 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Jun 2 17:12 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Jun 2 17:12 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 Jun 2 16:33 NewModel
-rw-r--r-- 1 mcc users 9.8K Jun 2 17:16 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 104K Jun 2 17:16 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 6.2K Jun 2 17:16 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 49K Jun 2 17:16 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Jun 2 17:12 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Jun 2 17:12 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Jun 2 16:33 equiv_col
-rw-r--r-- 1 mcc users 3 Jun 2 16:33 instance
-rw-r--r-- 1 mcc users 6 Jun 2 16:33 iscolored
-rw-r--r-- 1 mcc users 175K Jun 2 16:33 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME MedleyA-PT-17-LTLFireability-00
FORMULA_NAME MedleyA-PT-17-LTLFireability-01
FORMULA_NAME MedleyA-PT-17-LTLFireability-02
FORMULA_NAME MedleyA-PT-17-LTLFireability-03
FORMULA_NAME MedleyA-PT-17-LTLFireability-04
FORMULA_NAME MedleyA-PT-17-LTLFireability-05
FORMULA_NAME MedleyA-PT-17-LTLFireability-06
FORMULA_NAME MedleyA-PT-17-LTLFireability-07
FORMULA_NAME MedleyA-PT-17-LTLFireability-08
FORMULA_NAME MedleyA-PT-17-LTLFireability-09
FORMULA_NAME MedleyA-PT-17-LTLFireability-10
FORMULA_NAME MedleyA-PT-17-LTLFireability-11
FORMULA_NAME MedleyA-PT-17-LTLFireability-12
FORMULA_NAME MedleyA-PT-17-LTLFireability-13
FORMULA_NAME MedleyA-PT-17-LTLFireability-14
FORMULA_NAME MedleyA-PT-17-LTLFireability-15
=== Now, execution of the tool begins
BK_START 1717396158451
FORMULA MedleyA-PT-17-LTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA MedleyA-PT-17-LTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA MedleyA-PT-17-LTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA MedleyA-PT-17-LTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA MedleyA-PT-17-LTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA MedleyA-PT-17-LTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA MedleyA-PT-17-LTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA MedleyA-PT-17-LTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_TIME_CONFINEMENT_REACHED
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mLTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 27 (type CNST) for 26 MedleyA-PT-17-LTLFireability-06
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 27 (type CNST) for MedleyA-PT-17-LTLFireability-06
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 21 (type CNST) for 20 MedleyA-PT-17-LTLFireability-04
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 21 (type CNST) for MedleyA-PT-17-LTLFireability-04
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 9 (type EXCL) for 6 MedleyA-PT-17-LTLFireability-02
[[35mlola[0m][I] time limit : 163 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 9 (type EXCL) for MedleyA-PT-17-LTLFireability-02
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 6
[[35mlola[0m][I] fired transitions : 6
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 18 (type EXCL) for 13 MedleyA-PT-17-LTLFireability-03
[[35mlola[0m][I] time limit : 188 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 18 (type EXCL) for MedleyA-PT-17-LTLFireability-03
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 67 (type EXCL) for 32 MedleyA-PT-17-LTLFireability-08
[[35mlola[0m][I] time limit : 211 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 65 (type FNDP) for 32 MedleyA-PT-17-LTLFireability-08
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 66 (type EQUN) for 32 MedleyA-PT-17-LTLFireability-08
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 65 (type FNDP) for MedleyA-PT-17-LTLFireability-08
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 66 (type EQUN) for MedleyA-PT-17-LTLFireability-08 (obsolete)
[[35mlola[0m][W] CANCELED task # 67 (type EXCL) for MedleyA-PT-17-LTLFireability-08 (obsolete)
[[35mlola[0m][I] FINISHED task # 67 (type EXCL) for MedleyA-PT-17-LTLFireability-08
[[35mlola[0m][I] result : true
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 30 (type EXCL) for 29 MedleyA-PT-17-LTLFireability-07
[[35mlola[0m][I] time limit : 239 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 30 (type EXCL) for MedleyA-PT-17-LTLFireability-07
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 5
[[35mlola[0m][I] fired transitions : 5
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 36 (type EXCL) for 35 MedleyA-PT-17-LTLFireability-09
[[35mlola[0m][I] time limit : 256 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 36 (type EXCL) for MedleyA-PT-17-LTLFireability-09
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 29
[[35mlola[0m][I] fired transitions : 29
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 24 (type EXCL) for 23 MedleyA-PT-17-LTLFireability-05
[[35mlola[0m][I] time limit : 298 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 69 (type FNDP) for 57 MedleyA-PT-17-LTLFireability-15
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 70 (type EQUN) for 57 MedleyA-PT-17-LTLFireability-15
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 76 (type EQUN) for 13 MedleyA-PT-17-LTLFireability-03
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 24 (type EXCL) for MedleyA-PT-17-LTLFireability-05
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 29
[[35mlola[0m][I] fired transitions : 29
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 4 (type EXCL) for 3 MedleyA-PT-17-LTLFireability-01
[[35mlola[0m][I] time limit : 326 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 69 (type FNDP) for MedleyA-PT-17-LTLFireability-15
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 70 (type EQUN) for MedleyA-PT-17-LTLFireability-15 (obsolete)
[[35mlola[0m][I] FINISHED task # 66 (type EQUN) for MedleyA-PT-17-LTLFireability-08
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] FINISHED task # 70 (type EQUN) for MedleyA-PT-17-LTLFireability-15
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] FINISHED task # 76 (type EQUN) for MedleyA-PT-17-LTLFireability-03
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 4/398 4/2000 MedleyA-PT-17-LTLFireability-01 509090 m, 101818 m/sec, 2585131 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 17 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 9/398 8/2000 MedleyA-PT-17-LTLFireability-01 1064138 m, 111009 m/sec, 5549329 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 22 secs. Pages in use: 8
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 14/398 11/2000 MedleyA-PT-17-LTLFireability-01 1522659 m, 91704 m/sec, 8210935 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 27 secs. Pages in use: 11
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 19/398 14/2000 MedleyA-PT-17-LTLFireability-01 2071288 m, 109725 m/sec, 11136758 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 32 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 24/398 18/2000 MedleyA-PT-17-LTLFireability-01 2573127 m, 100367 m/sec, 14046198 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 37 secs. Pages in use: 18
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 29/398 21/2000 MedleyA-PT-17-LTLFireability-01 3079916 m, 101357 m/sec, 16923944 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 42 secs. Pages in use: 21
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 34/398 24/2000 MedleyA-PT-17-LTLFireability-01 3544344 m, 92885 m/sec, 19840023 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 47 secs. Pages in use: 24
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 39/398 27/2000 MedleyA-PT-17-LTLFireability-01 3972787 m, 85688 m/sec, 22616726 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 52 secs. Pages in use: 27
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 44/398 30/2000 MedleyA-PT-17-LTLFireability-01 4440609 m, 93564 m/sec, 25353443 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 57 secs. Pages in use: 30
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 49/398 33/2000 MedleyA-PT-17-LTLFireability-01 4865846 m, 85047 m/sec, 28091903 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 62 secs. Pages in use: 33
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 54/398 36/2000 MedleyA-PT-17-LTLFireability-01 5318356 m, 90502 m/sec, 30807889 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 67 secs. Pages in use: 36
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 59/398 39/2000 MedleyA-PT-17-LTLFireability-01 5721338 m, 80596 m/sec, 33428939 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 72 secs. Pages in use: 39
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 64/398 42/2000 MedleyA-PT-17-LTLFireability-01 6153077 m, 86347 m/sec, 36059224 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 77 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 69/398 44/2000 MedleyA-PT-17-LTLFireability-01 6499715 m, 69327 m/sec, 38464843 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 82 secs. Pages in use: 44
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 74/398 47/2000 MedleyA-PT-17-LTLFireability-01 6965775 m, 93212 m/sec, 41193965 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 87 secs. Pages in use: 47
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 79/398 50/2000 MedleyA-PT-17-LTLFireability-01 7418173 m, 90479 m/sec, 43905117 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 92 secs. Pages in use: 50
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 84/398 53/2000 MedleyA-PT-17-LTLFireability-01 7829449 m, 82255 m/sec, 46404178 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 97 secs. Pages in use: 53
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 89/398 55/2000 MedleyA-PT-17-LTLFireability-01 8229557 m, 80021 m/sec, 48892842 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 102 secs. Pages in use: 55
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 94/398 58/2000 MedleyA-PT-17-LTLFireability-01 8637135 m, 81515 m/sec, 51436673 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 107 secs. Pages in use: 58
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 99/398 61/2000 MedleyA-PT-17-LTLFireability-01 9061954 m, 84963 m/sec, 54047820 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 112 secs. Pages in use: 61
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 104/398 64/2000 MedleyA-PT-17-LTLFireability-01 9475211 m, 82651 m/sec, 56624811 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 117 secs. Pages in use: 64
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 109/398 66/2000 MedleyA-PT-17-LTLFireability-01 9885089 m, 81975 m/sec, 59231663 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 122 secs. Pages in use: 66
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 114/398 69/2000 MedleyA-PT-17-LTLFireability-01 10273512 m, 77684 m/sec, 61850858 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 127 secs. Pages in use: 69
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 119/398 72/2000 MedleyA-PT-17-LTLFireability-01 10675371 m, 80371 m/sec, 64475179 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 132 secs. Pages in use: 72
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 124/398 74/2000 MedleyA-PT-17-LTLFireability-01 11095723 m, 84070 m/sec, 67085070 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 137 secs. Pages in use: 74
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 129/398 77/2000 MedleyA-PT-17-LTLFireability-01 11516587 m, 84172 m/sec, 69691761 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 142 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 134/398 79/2000 MedleyA-PT-17-LTLFireability-01 11859627 m, 68608 m/sec, 72081867 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 147 secs. Pages in use: 79
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 139/398 82/2000 MedleyA-PT-17-LTLFireability-01 12240809 m, 76236 m/sec, 74633905 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 152 secs. Pages in use: 82
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 144/398 84/2000 MedleyA-PT-17-LTLFireability-01 12617043 m, 75246 m/sec, 77120164 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 157 secs. Pages in use: 84
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 149/398 87/2000 MedleyA-PT-17-LTLFireability-01 12996204 m, 75832 m/sec, 79663190 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 162 secs. Pages in use: 87
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 154/398 89/2000 MedleyA-PT-17-LTLFireability-01 13353795 m, 71518 m/sec, 82016039 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 167 secs. Pages in use: 89
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 159/398 92/2000 MedleyA-PT-17-LTLFireability-01 13739744 m, 77189 m/sec, 84542809 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 172 secs. Pages in use: 92
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 164/398 94/2000 MedleyA-PT-17-LTLFireability-01 14124788 m, 77008 m/sec, 87109595 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 177 secs. Pages in use: 94
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 169/398 97/2000 MedleyA-PT-17-LTLFireability-01 14511471 m, 77336 m/sec, 89704438 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 182 secs. Pages in use: 97
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 174/398 99/2000 MedleyA-PT-17-LTLFireability-01 14907848 m, 79275 m/sec, 92164667 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 187 secs. Pages in use: 99
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 179/398 102/2000 MedleyA-PT-17-LTLFireability-01 15332074 m, 84845 m/sec, 94705662 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 192 secs. Pages in use: 102
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 184/398 105/2000 MedleyA-PT-17-LTLFireability-01 15734759 m, 80537 m/sec, 97226173 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 197 secs. Pages in use: 105
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 189/398 107/2000 MedleyA-PT-17-LTLFireability-01 16076391 m, 68326 m/sec, 99657888 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 202 secs. Pages in use: 107
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 194/398 110/2000 MedleyA-PT-17-LTLFireability-01 16463009 m, 77323 m/sec, 102206414 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 207 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 199/398 112/2000 MedleyA-PT-17-LTLFireability-01 16850662 m, 77530 m/sec, 104675063 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 212 secs. Pages in use: 112
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 204/398 115/2000 MedleyA-PT-17-LTLFireability-01 17231796 m, 76226 m/sec, 107122256 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 217 secs. Pages in use: 115
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 209/398 117/2000 MedleyA-PT-17-LTLFireability-01 17618333 m, 77307 m/sec, 109572514 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 222 secs. Pages in use: 117
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 214/398 120/2000 MedleyA-PT-17-LTLFireability-01 18024819 m, 81297 m/sec, 112108037 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 227 secs. Pages in use: 120
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 219/398 122/2000 MedleyA-PT-17-LTLFireability-01 18392871 m, 73610 m/sec, 114478304 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 232 secs. Pages in use: 122
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 224/398 125/2000 MedleyA-PT-17-LTLFireability-01 18728734 m, 67172 m/sec, 116880819 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 237 secs. Pages in use: 125
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 229/398 127/2000 MedleyA-PT-17-LTLFireability-01 19081314 m, 70516 m/sec, 119171562 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 242 secs. Pages in use: 127
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 234/398 129/2000 MedleyA-PT-17-LTLFireability-01 19438576 m, 71452 m/sec, 121604759 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 247 secs. Pages in use: 129
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 239/398 132/2000 MedleyA-PT-17-LTLFireability-01 19800342 m, 72353 m/sec, 124011310 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 252 secs. Pages in use: 132
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 244/398 134/2000 MedleyA-PT-17-LTLFireability-01 20152729 m, 70477 m/sec, 126489664 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 257 secs. Pages in use: 134
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 249/398 136/2000 MedleyA-PT-17-LTLFireability-01 20488323 m, 67118 m/sec, 128877812 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 262 secs. Pages in use: 136
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 254/398 138/2000 MedleyA-PT-17-LTLFireability-01 20859228 m, 74181 m/sec, 131399529 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 267 secs. Pages in use: 138
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 259/398 141/2000 MedleyA-PT-17-LTLFireability-01 21235541 m, 75262 m/sec, 133922713 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 272 secs. Pages in use: 141
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 264/398 143/2000 MedleyA-PT-17-LTLFireability-01 21572586 m, 67409 m/sec, 136365929 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 277 secs. Pages in use: 143
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 269/398 145/2000 MedleyA-PT-17-LTLFireability-01 21911846 m, 67852 m/sec, 138873045 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 282 secs. Pages in use: 145
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 274/398 147/2000 MedleyA-PT-17-LTLFireability-01 22205100 m, 58650 m/sec, 141200277 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 287 secs. Pages in use: 147
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 279/398 150/2000 MedleyA-PT-17-LTLFireability-01 22560983 m, 71176 m/sec, 143578699 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 292 secs. Pages in use: 150
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 284/398 152/2000 MedleyA-PT-17-LTLFireability-01 22906966 m, 69196 m/sec, 146053822 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 297 secs. Pages in use: 152
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 289/398 154/2000 MedleyA-PT-17-LTLFireability-01 23264947 m, 71596 m/sec, 148443226 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 302 secs. Pages in use: 154
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 294/398 157/2000 MedleyA-PT-17-LTLFireability-01 23628485 m, 72707 m/sec, 150916502 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 307 secs. Pages in use: 157
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 299/398 159/2000 MedleyA-PT-17-LTLFireability-01 24006653 m, 75633 m/sec, 153365216 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 312 secs. Pages in use: 159
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 304/398 161/2000 MedleyA-PT-17-LTLFireability-01 24360654 m, 70800 m/sec, 155647238 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 317 secs. Pages in use: 161
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 309/398 164/2000 MedleyA-PT-17-LTLFireability-01 24673732 m, 62615 m/sec, 158024427 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 322 secs. Pages in use: 164
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 314/398 166/2000 MedleyA-PT-17-LTLFireability-01 25033326 m, 71918 m/sec, 160475395 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 327 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 319/398 168/2000 MedleyA-PT-17-LTLFireability-01 25388212 m, 70977 m/sec, 162933380 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 332 secs. Pages in use: 168
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 324/398 171/2000 MedleyA-PT-17-LTLFireability-01 25747712 m, 71900 m/sec, 165321770 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 337 secs. Pages in use: 171
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 329/398 173/2000 MedleyA-PT-17-LTLFireability-01 26078549 m, 66167 m/sec, 167622114 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 342 secs. Pages in use: 173
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 334/398 175/2000 MedleyA-PT-17-LTLFireability-01 26363057 m, 56901 m/sec, 169960194 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 347 secs. Pages in use: 175
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 339/398 177/2000 MedleyA-PT-17-LTLFireability-01 26701491 m, 67686 m/sec, 172353265 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 352 secs. Pages in use: 177
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 344/398 179/2000 MedleyA-PT-17-LTLFireability-01 27013964 m, 62494 m/sec, 174753549 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 357 secs. Pages in use: 179
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 349/398 181/2000 MedleyA-PT-17-LTLFireability-01 27376467 m, 72500 m/sec, 177226248 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 362 secs. Pages in use: 181
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 354/398 183/2000 MedleyA-PT-17-LTLFireability-01 27678735 m, 60453 m/sec, 179556635 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 367 secs. Pages in use: 183
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 359/398 185/2000 MedleyA-PT-17-LTLFireability-01 27981743 m, 60601 m/sec, 181879806 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 372 secs. Pages in use: 185
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 364/398 187/2000 MedleyA-PT-17-LTLFireability-01 28310093 m, 65670 m/sec, 184211211 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 377 secs. Pages in use: 187
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 369/398 190/2000 MedleyA-PT-17-LTLFireability-01 28683392 m, 74659 m/sec, 186667438 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 382 secs. Pages in use: 190
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 374/398 192/2000 MedleyA-PT-17-LTLFireability-01 29017847 m, 66891 m/sec, 189088383 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 387 secs. Pages in use: 192
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 379/398 194/2000 MedleyA-PT-17-LTLFireability-01 29369687 m, 70368 m/sec, 191555096 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 392 secs. Pages in use: 194
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 384/398 197/2000 MedleyA-PT-17-LTLFireability-01 29716492 m, 69361 m/sec, 193996584 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 397 secs. Pages in use: 197
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 389/398 199/2000 MedleyA-PT-17-LTLFireability-01 30068873 m, 70476 m/sec, 196355012 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 402 secs. Pages in use: 199
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 394/398 201/2000 MedleyA-PT-17-LTLFireability-01 30422290 m, 70683 m/sec, 198760284 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 407 secs. Pages in use: 201
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 4 (type EXCL) for MedleyA-PT-17-LTLFireability-01 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 412 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 52 (type EXCL) for 51 MedleyA-PT-17-LTLFireability-13
[[35mlola[0m][I] time limit : 398 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 4 (type EXCL) for 3 MedleyA-PT-17-LTLFireability-01
[[35mlola[0m][I] time limit : 3188 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 52 (type EXCL) for MedleyA-PT-17-LTLFireability-13
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 102468
[[35mlola[0m][I] fired transitions : 504887
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 5/398 4/5 MedleyA-PT-17-LTLFireability-01 590374 m, -5966383 m/sec, 2998181 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 417 secs. Pages in use: 208
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 4 (type EXCL) for MedleyA-PT-17-LTLFireability-01 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 422 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 47 (type EXCL) for 44 MedleyA-PT-17-LTLFireability-12
[[35mlola[0m][I] time limit : 454 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 47 (type EXCL) for MedleyA-PT-17-LTLFireability-12
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 29
[[35mlola[0m][I] fired transitions : 29
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 39 (type EXCL) for 38 MedleyA-PT-17-LTLFireability-10
[[35mlola[0m][I] time limit : 635 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 LTL EXCL 5/635 3/2000 MedleyA-PT-17-LTLFireability-10 332571 m, 66514 m/sec, 3280968 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 427 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 39 (type EXCL) for MedleyA-PT-17-LTLFireability-10
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 451331
[[35mlola[0m][I] fired transitions : 4542429
[[35mlola[0m][I] time used : 7
[[35mlola[0m][I] memory pages used : 3
[[35mlola[0m][I] LAUNCH task # 73 (type EXCL) for 13 MedleyA-PT-17-LTLFireability-03
[[35mlola[0m][I] time limit : 792 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 73 (type EXCL) for MedleyA-PT-17-LTLFireability-03
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 5
[[35mlola[0m][I] fired transitions : 4
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 55 (type EXCL) for 54 MedleyA-PT-17-LTLFireability-14
[[35mlola[0m][I] time limit : 1057 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 55 (type EXCL) for MedleyA-PT-17-LTLFireability-14
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 224
[[35mlola[0m][I] fired transitions : 368
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 42 (type EXCL) for 41 MedleyA-PT-17-LTLFireability-11
[[35mlola[0m][I] time limit : 1585 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 42 (type EXCL) for MedleyA-PT-17-LTLFireability-11
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 7
[[35mlola[0m][I] fired transitions : 7
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 1 (type EXCL) for 0 MedleyA-PT-17-LTLFireability-00
[[35mlola[0m][I] time limit : 3171 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 1 (type EXCL) for MedleyA-PT-17-LTLFireability-00
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 432 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 437 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 442 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 447 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 452 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 457 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 462 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 467 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 472 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 477 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 482 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 487 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 492 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 497 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 502 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 507 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 512 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 517 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 522 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 527 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 532 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 537 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 542 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 547 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 552 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 557 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 562 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 567 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 572 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 577 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 582 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 587 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 592 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 597 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 602 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 607 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 612 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 617 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 622 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 627 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 632 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 637 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 642 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 647 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 652 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 657 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 662 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 667 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 672 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 677 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 682 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 687 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 692 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 697 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 702 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 707 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 712 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 717 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 722 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 727 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 732 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 737 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 742 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 747 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 752 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 757 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 762 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 767 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 772 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 777 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 782 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 787 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 792 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 797 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 802 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 807 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 812 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 817 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 822 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 827 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 832 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 837 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 842 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 847 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 852 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 857 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 862 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 867 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 872 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 877 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 882 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 887 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 892 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 897 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 902 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 907 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 912 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 917 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 922 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 927 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 932 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 937 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 942 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 947 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 952 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 957 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 962 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 967 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 972 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 977 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 982 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 987 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 992 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 997 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1002 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1007 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1012 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1017 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1022 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1027 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1032 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1037 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1042 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1047 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1052 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1057 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1062 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1067 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1072 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1077 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1082 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1087 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1092 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1097 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1102 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1107 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1112 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1117 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1122 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1127 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1132 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1137 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1142 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1147 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1152 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1157 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1162 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1167 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1172 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1177 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1182 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1187 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1192 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1197 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1202 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1207 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1212 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1217 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1222 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1227 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1232 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1237 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1242 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1247 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1252 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1257 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1262 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1267 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1272 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1277 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1282 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1287 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1292 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1297 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1302 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1307 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1312 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1317 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1322 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1327 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1332 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1337 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1342 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1347 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1352 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1357 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1362 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1367 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1372 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1377 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1382 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1387 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1392 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1397 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1402 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1407 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1412 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1417 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1422 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1427 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1432 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1437 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1442 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1447 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1452 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1457 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1462 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1467 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1472 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1477 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1482 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1487 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1492 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1497 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1502 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1507 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1512 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1517 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1522 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1527 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1532 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1537 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1542 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1547 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1552 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1557 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1562 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1567 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1572 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1577 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1582 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1587 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1592 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1597 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1602 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1607 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1612 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1617 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1622 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1627 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1632 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1637 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1642 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1647 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1652 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1657 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1662 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1667 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1672 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1677 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1682 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1687 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1692 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1697 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1702 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1707 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1712 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1717 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1722 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1727 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1732 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1737 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1742 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1747 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1752 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1757 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1762 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1767 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1772 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1777 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1782 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1787 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1792 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1797 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1802 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1807 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1812 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1817 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1822 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1827 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1832 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1837 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1842 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1847 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1852 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1857 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1862 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1867 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1872 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1877 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1882 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1887 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1892 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1897 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1902 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1907 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1912 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1917 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1922 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1927 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1932 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1937 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1942 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1947 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1952 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1957 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1962 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1967 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1972 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1977 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1982 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1987 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1992 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1997 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-17-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2002 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-17-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-08: AG false findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-17-LTLFireability-11: LTL false LTL model checker[0m
========== file over 1MB has been truncated ======
retrieve it from the run archives if needed
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="MedleyA-PT-17"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is MedleyA-PT-17, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r577-smll-171734920500132"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/MedleyA-PT-17.tgz
mv MedleyA-PT-17 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;