About the Execution of LoLA for MedleyA-PT-10
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 8688.355 | 803519.00 | 804116.00 | 2227.10 | TTFTTFTT?T?FFTTT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r577-smll-171734920400074.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
..............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is MedleyA-PT-10, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r577-smll-171734920400074
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 552K
-rw-r--r-- 1 mcc users 6.8K Jun 2 17:16 CTLCardinality.txt
-rw-r--r-- 1 mcc users 76K Jun 2 17:16 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.6K Jun 2 17:16 CTLFireability.txt
-rw-r--r-- 1 mcc users 41K Jun 2 17:16 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.4K Jun 2 17:12 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Jun 2 17:12 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Jun 2 17:12 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K Jun 2 17:12 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 Jun 2 16:33 NewModel
-rw-r--r-- 1 mcc users 9.9K Jun 2 17:16 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 108K Jun 2 17:16 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Jun 2 17:16 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 94K Jun 2 17:16 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Jun 2 17:12 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Jun 2 17:12 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Jun 2 16:33 equiv_col
-rw-r--r-- 1 mcc users 3 Jun 2 16:33 instance
-rw-r--r-- 1 mcc users 6 Jun 2 16:33 iscolored
-rw-r--r-- 1 mcc users 107K Jun 2 16:33 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME MedleyA-PT-10-CTLFireability-2024-00
FORMULA_NAME MedleyA-PT-10-CTLFireability-2024-01
FORMULA_NAME MedleyA-PT-10-CTLFireability-2024-02
FORMULA_NAME MedleyA-PT-10-CTLFireability-2024-03
FORMULA_NAME MedleyA-PT-10-CTLFireability-2024-04
FORMULA_NAME MedleyA-PT-10-CTLFireability-2024-05
FORMULA_NAME MedleyA-PT-10-CTLFireability-2024-06
FORMULA_NAME MedleyA-PT-10-CTLFireability-2024-07
FORMULA_NAME MedleyA-PT-10-CTLFireability-2024-08
FORMULA_NAME MedleyA-PT-10-CTLFireability-2024-09
FORMULA_NAME MedleyA-PT-10-CTLFireability-2024-10
FORMULA_NAME MedleyA-PT-10-CTLFireability-2024-11
FORMULA_NAME MedleyA-PT-10-CTLFireability-2024-12
FORMULA_NAME MedleyA-PT-10-CTLFireability-2024-13
FORMULA_NAME MedleyA-PT-10-CTLFireability-2024-14
FORMULA_NAME MedleyA-PT-10-CTLFireability-2024-15
=== Now, execution of the tool begins
BK_START 1717373614131
FORMULA MedleyA-PT-10-CTLFireability-2024-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA MedleyA-PT-10-CTLFireability-2024-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA MedleyA-PT-10-CTLFireability-2024-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA MedleyA-PT-10-CTLFireability-2024-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA MedleyA-PT-10-CTLFireability-2024-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA MedleyA-PT-10-CTLFireability-2024-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA MedleyA-PT-10-CTLFireability-2024-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA MedleyA-PT-10-CTLFireability-2024-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA MedleyA-PT-10-CTLFireability-2024-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA MedleyA-PT-10-CTLFireability-2024-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA MedleyA-PT-10-CTLFireability-2024-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA MedleyA-PT-10-CTLFireability-2024-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA MedleyA-PT-10-CTLFireability-2024-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA MedleyA-PT-10-CTLFireability-2024-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[[35mlola[0m] [1mFINAL RESULTS[0m
[[35mlola[0m] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m] [1m[32mMedleyA-PT-10-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mMedleyA-PT-10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mMedleyA-PT-10-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mMedleyA-PT-10-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m] [1m[32mMedleyA-PT-10-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m] [1m[33mMedleyA-PT-10-CTLFireability-2024-08: CTL unknown AGGR[0m
[[35mlola[0m] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m] [1m[33mMedleyA-PT-10-CTLFireability-2024-10: CTL unknown AGGR[0m
[[35mlola[0m] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mMedleyA-PT-10-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mMedleyA-PT-10-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m]
[[35mlola[0m] Time elapsed: 803 secs. Pages in use: 383
BK_STOP 1717374417650
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 13 (type EXCL) for 12 MedleyA-PT-10-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 119 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 64 (type FNDP) for 18 MedleyA-PT-10-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 65 (type EQUN) for 18 MedleyA-PT-10-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 64 (type FNDP) for MedleyA-PT-10-CTLFireability-2024-06
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 34
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 65 (type EQUN) for MedleyA-PT-10-CTLFireability-2024-06 (obsolete)
[*** LOG ERROR #0001 ***] [2024-06-03 00:13:36] [status_logger] string pointer is null
[[35mlola[0m][I] FINISHED task # 13 (type EXCL) for MedleyA-PT-10-CTLFireability-2024-04
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 15052
[[35mlola[0m][I] fired transitions : 64289
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 56 (type EXCL) for 55 MedleyA-PT-10-CTLFireability-2024-13
[[35mlola[0m][I] time limit : 179 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 69 (type EQUN) for 0 MedleyA-PT-10-CTLFireability-2024-00
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 65 (type EQUN) for MedleyA-PT-10-CTLFireability-2024-06
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] FINISHED task # 69 (type EQUN) for MedleyA-PT-10-CTLFireability-2024-00
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 56 (type EXCL) for MedleyA-PT-10-CTLFireability-2024-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 428972
[[35mlola[0m][I] fired transitions : 2141385
[[35mlola[0m][I] time used : 4
[[35mlola[0m][I] memory pages used : 2
[[35mlola[0m][I] LAUNCH task # 67 (type EXCL) for 0 MedleyA-PT-10-CTLFireability-2024-00
[[35mlola[0m][I] time limit : 276 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 67 (type EXCL) for MedleyA-PT-10-CTLFireability-2024-00
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 262
[[35mlola[0m][I] fired transitions : 308
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 59 (type EXCL) for 58 MedleyA-PT-10-CTLFireability-2024-14
[[35mlola[0m][I] time limit : 299 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 59 (type EXCL) for MedleyA-PT-10-CTLFireability-2024-14
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 30
[[35mlola[0m][I] fired transitions : 60
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 50 (type EXCL) for 49 MedleyA-PT-10-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 326 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 CTL EXCL 1/326 1/2000 MedleyA-PT-10-CTLFireability-2024-11 150590 m, 30118 m/sec, 801215 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 7 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 CTL EXCL 6/326 4/2000 MedleyA-PT-10-CTLFireability-2024-11 757828 m, 121447 m/sec, 4508890 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 12 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 50 (type EXCL) for MedleyA-PT-10-CTLFireability-2024-11
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1309704
[[35mlola[0m][I] fired transitions : 7464306
[[35mlola[0m][I] time used : 10
[[35mlola[0m][I] memory pages used : 6
[[35mlola[0m][I] LAUNCH task # 47 (type EXCL) for 46 MedleyA-PT-10-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 358 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 1/358 1/2000 MedleyA-PT-10-CTLFireability-2024-10 156537 m, 31307 m/sec, 520022 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 17 secs. Pages in use: 6
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 6/358 5/2000 MedleyA-PT-10-CTLFireability-2024-10 1021368 m, 172966 m/sec, 4024243 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 22 secs. Pages in use: 6
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 11/358 8/2000 MedleyA-PT-10-CTLFireability-2024-10 1804974 m, 156721 m/sec, 7778476 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 27 secs. Pages in use: 8
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 16/358 11/2000 MedleyA-PT-10-CTLFireability-2024-10 2565830 m, 152171 m/sec, 11269496 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 32 secs. Pages in use: 11
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 21/358 15/2000 MedleyA-PT-10-CTLFireability-2024-10 3408670 m, 168568 m/sec, 14850649 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 37 secs. Pages in use: 15
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 26/358 18/2000 MedleyA-PT-10-CTLFireability-2024-10 4146520 m, 147570 m/sec, 18500204 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 42 secs. Pages in use: 18
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 31/358 21/2000 MedleyA-PT-10-CTLFireability-2024-10 4890280 m, 148752 m/sec, 22147972 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 47 secs. Pages in use: 21
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 36/358 24/2000 MedleyA-PT-10-CTLFireability-2024-10 5631125 m, 148169 m/sec, 25686851 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 52 secs. Pages in use: 24
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 41/358 28/2000 MedleyA-PT-10-CTLFireability-2024-10 6371684 m, 148111 m/sec, 29153144 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 57 secs. Pages in use: 28
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 46/358 31/2000 MedleyA-PT-10-CTLFireability-2024-10 7125234 m, 150710 m/sec, 32604828 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 62 secs. Pages in use: 31
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 51/358 34/2000 MedleyA-PT-10-CTLFireability-2024-10 7826316 m, 140216 m/sec, 35982671 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 67 secs. Pages in use: 34
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 56/358 36/2000 MedleyA-PT-10-CTLFireability-2024-10 8451077 m, 124952 m/sec, 39396061 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 72 secs. Pages in use: 36
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 61/358 39/2000 MedleyA-PT-10-CTLFireability-2024-10 9147669 m, 139318 m/sec, 42801032 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 77 secs. Pages in use: 39
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 66/358 42/2000 MedleyA-PT-10-CTLFireability-2024-10 9764124 m, 123291 m/sec, 46189335 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 82 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 71/358 45/2000 MedleyA-PT-10-CTLFireability-2024-10 10397583 m, 126691 m/sec, 49540178 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 87 secs. Pages in use: 45
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 76/358 47/2000 MedleyA-PT-10-CTLFireability-2024-10 11035643 m, 127612 m/sec, 52952368 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 92 secs. Pages in use: 47
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 81/358 50/2000 MedleyA-PT-10-CTLFireability-2024-10 11678377 m, 128546 m/sec, 56245829 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 97 secs. Pages in use: 50
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 86/358 53/2000 MedleyA-PT-10-CTLFireability-2024-10 12343970 m, 133118 m/sec, 59590604 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 102 secs. Pages in use: 53
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 91/358 56/2000 MedleyA-PT-10-CTLFireability-2024-10 12980649 m, 127335 m/sec, 62957138 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 107 secs. Pages in use: 56
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 96/358 58/2000 MedleyA-PT-10-CTLFireability-2024-10 13493299 m, 102530 m/sec, 66460034 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 112 secs. Pages in use: 58
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 101/358 60/2000 MedleyA-PT-10-CTLFireability-2024-10 14109857 m, 123311 m/sec, 69799722 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 117 secs. Pages in use: 60
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 106/358 63/2000 MedleyA-PT-10-CTLFireability-2024-10 14679359 m, 113900 m/sec, 73212454 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 122 secs. Pages in use: 63
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 111/358 66/2000 MedleyA-PT-10-CTLFireability-2024-10 15332900 m, 130708 m/sec, 76509731 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 127 secs. Pages in use: 66
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 116/358 68/2000 MedleyA-PT-10-CTLFireability-2024-10 15889567 m, 111333 m/sec, 79865913 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 132 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 121/358 71/2000 MedleyA-PT-10-CTLFireability-2024-10 16509564 m, 123999 m/sec, 83246726 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 137 secs. Pages in use: 71
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 126/358 73/2000 MedleyA-PT-10-CTLFireability-2024-10 17069100 m, 111907 m/sec, 86573701 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 142 secs. Pages in use: 73
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 131/358 75/2000 MedleyA-PT-10-CTLFireability-2024-10 17649874 m, 116154 m/sec, 89873319 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 147 secs. Pages in use: 75
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 136/358 78/2000 MedleyA-PT-10-CTLFireability-2024-10 18259533 m, 121931 m/sec, 93181226 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 152 secs. Pages in use: 78
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 141/358 81/2000 MedleyA-PT-10-CTLFireability-2024-10 18891824 m, 126458 m/sec, 96485624 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 157 secs. Pages in use: 81
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 146/358 83/2000 MedleyA-PT-10-CTLFireability-2024-10 19447922 m, 111219 m/sec, 99888245 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 162 secs. Pages in use: 83
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 151/358 85/2000 MedleyA-PT-10-CTLFireability-2024-10 19959323 m, 102280 m/sec, 103343497 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 167 secs. Pages in use: 85
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 156/358 87/2000 MedleyA-PT-10-CTLFireability-2024-10 20480953 m, 104326 m/sec, 106797400 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 172 secs. Pages in use: 87
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 161/358 90/2000 MedleyA-PT-10-CTLFireability-2024-10 21084621 m, 120733 m/sec, 110047460 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 177 secs. Pages in use: 90
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 166/358 92/2000 MedleyA-PT-10-CTLFireability-2024-10 21674677 m, 118011 m/sec, 113278261 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 182 secs. Pages in use: 92
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 171/358 95/2000 MedleyA-PT-10-CTLFireability-2024-10 22225036 m, 110071 m/sec, 116710856 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 187 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 176/358 97/2000 MedleyA-PT-10-CTLFireability-2024-10 22820776 m, 119148 m/sec, 119952402 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 192 secs. Pages in use: 97
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 181/358 100/2000 MedleyA-PT-10-CTLFireability-2024-10 23391681 m, 114181 m/sec, 123223203 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 197 secs. Pages in use: 100
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 186/358 102/2000 MedleyA-PT-10-CTLFireability-2024-10 23980014 m, 117666 m/sec, 126401834 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 202 secs. Pages in use: 102
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 191/358 105/2000 MedleyA-PT-10-CTLFireability-2024-10 24552822 m, 114561 m/sec, 129768508 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 207 secs. Pages in use: 105
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 196/358 107/2000 MedleyA-PT-10-CTLFireability-2024-10 25151283 m, 119692 m/sec, 133078395 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 212 secs. Pages in use: 107
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 201/358 109/2000 MedleyA-PT-10-CTLFireability-2024-10 25705162 m, 110775 m/sec, 136368442 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 217 secs. Pages in use: 109
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 206/358 112/2000 MedleyA-PT-10-CTLFireability-2024-10 26321487 m, 123265 m/sec, 139616062 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 222 secs. Pages in use: 112
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 211/358 114/2000 MedleyA-PT-10-CTLFireability-2024-10 26909463 m, 117595 m/sec, 142899376 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 227 secs. Pages in use: 114
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 216/358 117/2000 MedleyA-PT-10-CTLFireability-2024-10 27478041 m, 113715 m/sec, 146140152 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 232 secs. Pages in use: 117
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 221/358 119/2000 MedleyA-PT-10-CTLFireability-2024-10 27964391 m, 97270 m/sec, 149494878 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 237 secs. Pages in use: 119
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 226/358 121/2000 MedleyA-PT-10-CTLFireability-2024-10 28431364 m, 93394 m/sec, 152820890 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 242 secs. Pages in use: 121
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 231/358 123/2000 MedleyA-PT-10-CTLFireability-2024-10 28986360 m, 110999 m/sec, 156107288 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 247 secs. Pages in use: 123
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 236/358 126/2000 MedleyA-PT-10-CTLFireability-2024-10 29549371 m, 112602 m/sec, 159460940 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 252 secs. Pages in use: 126
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 241/358 128/2000 MedleyA-PT-10-CTLFireability-2024-10 30121338 m, 114393 m/sec, 162759546 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 257 secs. Pages in use: 128
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 246/358 130/2000 MedleyA-PT-10-CTLFireability-2024-10 30627003 m, 101133 m/sec, 166286168 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 262 secs. Pages in use: 130
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 251/358 132/2000 MedleyA-PT-10-CTLFireability-2024-10 31110792 m, 96757 m/sec, 169674164 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 267 secs. Pages in use: 132
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 256/358 134/2000 MedleyA-PT-10-CTLFireability-2024-10 31628471 m, 103535 m/sec, 173001189 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 272 secs. Pages in use: 134
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 261/358 137/2000 MedleyA-PT-10-CTLFireability-2024-10 32178679 m, 110041 m/sec, 176157534 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 277 secs. Pages in use: 137
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 266/358 139/2000 MedleyA-PT-10-CTLFireability-2024-10 32758639 m, 115992 m/sec, 179444577 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 282 secs. Pages in use: 139
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 271/358 142/2000 MedleyA-PT-10-CTLFireability-2024-10 33325393 m, 113350 m/sec, 182666549 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 287 secs. Pages in use: 142
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 276/358 144/2000 MedleyA-PT-10-CTLFireability-2024-10 33820399 m, 99001 m/sec, 186139927 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 292 secs. Pages in use: 144
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 281/358 146/2000 MedleyA-PT-10-CTLFireability-2024-10 34357361 m, 107392 m/sec, 189609124 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 297 secs. Pages in use: 146
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 286/358 148/2000 MedleyA-PT-10-CTLFireability-2024-10 34852423 m, 99012 m/sec, 193101278 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 302 secs. Pages in use: 148
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 291/358 150/2000 MedleyA-PT-10-CTLFireability-2024-10 35377444 m, 105004 m/sec, 196570626 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 307 secs. Pages in use: 150
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 296/358 153/2000 MedleyA-PT-10-CTLFireability-2024-10 35910039 m, 106519 m/sec, 199767991 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 312 secs. Pages in use: 153
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 301/358 155/2000 MedleyA-PT-10-CTLFireability-2024-10 36451026 m, 108197 m/sec, 202994147 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 317 secs. Pages in use: 155
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 306/358 157/2000 MedleyA-PT-10-CTLFireability-2024-10 37013742 m, 112543 m/sec, 206187572 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 322 secs. Pages in use: 157
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 311/358 159/2000 MedleyA-PT-10-CTLFireability-2024-10 37540048 m, 105261 m/sec, 209420010 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 327 secs. Pages in use: 159
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 316/358 162/2000 MedleyA-PT-10-CTLFireability-2024-10 38063538 m, 104698 m/sec, 212661884 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 332 secs. Pages in use: 162
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 321/358 164/2000 MedleyA-PT-10-CTLFireability-2024-10 38560900 m, 99472 m/sec, 215961506 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 337 secs. Pages in use: 164
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 326/358 166/2000 MedleyA-PT-10-CTLFireability-2024-10 39050395 m, 97899 m/sec, 219493972 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 342 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 331/358 168/2000 MedleyA-PT-10-CTLFireability-2024-10 39553241 m, 100569 m/sec, 223022680 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 347 secs. Pages in use: 168
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 336/358 170/2000 MedleyA-PT-10-CTLFireability-2024-10 40048834 m, 99118 m/sec, 226504118 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 352 secs. Pages in use: 170
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 341/358 172/2000 MedleyA-PT-10-CTLFireability-2024-10 40567172 m, 103667 m/sec, 229758389 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 357 secs. Pages in use: 172
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 346/358 174/2000 MedleyA-PT-10-CTLFireability-2024-10 41098183 m, 106202 m/sec, 232922738 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 362 secs. Pages in use: 174
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 351/358 177/2000 MedleyA-PT-10-CTLFireability-2024-10 41640059 m, 108375 m/sec, 236026824 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 367 secs. Pages in use: 177
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 356/358 179/2000 MedleyA-PT-10-CTLFireability-2024-10 42170942 m, 106176 m/sec, 239480640 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 372 secs. Pages in use: 179
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 47 (type EXCL) for MedleyA-PT-10-CTLFireability-2024-10 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 377 secs. Pages in use: 181
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 44 (type EXCL) for 43 MedleyA-PT-10-CTLFireability-2024-09
[[35mlola[0m][I] time limit : 358 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 47 (type EXCL) for 46 MedleyA-PT-10-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 3223 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 44 (type EXCL) for MedleyA-PT-10-CTLFireability-2024-09
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 29
[[35mlola[0m][I] fired transitions : 86
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 5/358 4/5 MedleyA-PT-10-CTLFireability-2024-10 916780 m, -8250832 m/sec, 3599577 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 382 secs. Pages in use: 185
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 47 (type EXCL) for MedleyA-PT-10-CTLFireability-2024-10 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 387 secs. Pages in use: 186
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 41 (type EXCL) for 40 MedleyA-PT-10-CTLFireability-2024-08
[[35mlola[0m][I] time limit : 401 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 5/401 4/2000 MedleyA-PT-10-CTLFireability-2024-08 912170 m, 182434 m/sec, 3404204 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 392 secs. Pages in use: 186
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 10/401 8/2000 MedleyA-PT-10-CTLFireability-2024-08 1679390 m, 153444 m/sec, 7153373 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 397 secs. Pages in use: 189
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 15/401 11/2000 MedleyA-PT-10-CTLFireability-2024-08 2403950 m, 144912 m/sec, 10624251 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 402 secs. Pages in use: 192
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 20/401 14/2000 MedleyA-PT-10-CTLFireability-2024-08 3233036 m, 165817 m/sec, 14063788 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 407 secs. Pages in use: 195
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 25/401 17/2000 MedleyA-PT-10-CTLFireability-2024-08 3972372 m, 147867 m/sec, 17619700 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 412 secs. Pages in use: 198
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 30/401 21/2000 MedleyA-PT-10-CTLFireability-2024-08 4687022 m, 142930 m/sec, 20892954 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 417 secs. Pages in use: 202
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 35/401 24/2000 MedleyA-PT-10-CTLFireability-2024-08 5499792 m, 162554 m/sec, 24424428 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 422 secs. Pages in use: 205
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 40/401 27/2000 MedleyA-PT-10-CTLFireability-2024-08 6261653 m, 152372 m/sec, 27916185 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 427 secs. Pages in use: 208
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 45/401 30/2000 MedleyA-PT-10-CTLFireability-2024-08 7014569 m, 150583 m/sec, 31392407 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 432 secs. Pages in use: 211
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 50/401 33/2000 MedleyA-PT-10-CTLFireability-2024-08 7646679 m, 126422 m/sec, 34917032 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 437 secs. Pages in use: 214
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 55/401 36/2000 MedleyA-PT-10-CTLFireability-2024-08 8283688 m, 127401 m/sec, 38335853 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 442 secs. Pages in use: 217
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 60/401 38/2000 MedleyA-PT-10-CTLFireability-2024-08 8896464 m, 122555 m/sec, 41813393 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 447 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 65/401 41/2000 MedleyA-PT-10-CTLFireability-2024-08 9508086 m, 122324 m/sec, 44982760 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 452 secs. Pages in use: 222
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 70/401 44/2000 MedleyA-PT-10-CTLFireability-2024-08 10150633 m, 128509 m/sec, 48444045 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 457 secs. Pages in use: 225
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 75/401 46/2000 MedleyA-PT-10-CTLFireability-2024-08 10696849 m, 109243 m/sec, 51725429 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 462 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 80/401 48/2000 MedleyA-PT-10-CTLFireability-2024-08 11254793 m, 111588 m/sec, 54996402 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 467 secs. Pages in use: 229
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 85/401 51/2000 MedleyA-PT-10-CTLFireability-2024-08 11863693 m, 121780 m/sec, 58483721 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 472 secs. Pages in use: 232
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 90/401 54/2000 MedleyA-PT-10-CTLFireability-2024-08 12494651 m, 126191 m/sec, 61938620 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 477 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 95/401 56/2000 MedleyA-PT-10-CTLFireability-2024-08 13015564 m, 104182 m/sec, 65427421 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 482 secs. Pages in use: 237
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 100/401 58/2000 MedleyA-PT-10-CTLFireability-2024-08 13502064 m, 97300 m/sec, 68956011 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 487 secs. Pages in use: 239
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 105/401 60/2000 MedleyA-PT-10-CTLFireability-2024-08 13986197 m, 96826 m/sec, 72387789 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 492 secs. Pages in use: 241
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 110/401 62/2000 MedleyA-PT-10-CTLFireability-2024-08 14508581 m, 104476 m/sec, 75938421 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 497 secs. Pages in use: 243
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 115/401 65/2000 MedleyA-PT-10-CTLFireability-2024-08 15107544 m, 119792 m/sec, 79379521 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 502 secs. Pages in use: 246
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 120/401 67/2000 MedleyA-PT-10-CTLFireability-2024-08 15636677 m, 105826 m/sec, 82836706 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 507 secs. Pages in use: 248
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 125/401 69/2000 MedleyA-PT-10-CTLFireability-2024-08 16148875 m, 102439 m/sec, 86337606 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 512 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 130/401 71/2000 MedleyA-PT-10-CTLFireability-2024-08 16721302 m, 114485 m/sec, 89791502 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 517 secs. Pages in use: 252
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 135/401 73/2000 MedleyA-PT-10-CTLFireability-2024-08 17199745 m, 95688 m/sec, 93237089 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 522 secs. Pages in use: 254
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 140/401 76/2000 MedleyA-PT-10-CTLFireability-2024-08 17697166 m, 99484 m/sec, 96653242 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 527 secs. Pages in use: 257
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 145/401 77/2000 MedleyA-PT-10-CTLFireability-2024-08 18161466 m, 92860 m/sec, 100053690 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 532 secs. Pages in use: 258
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 150/401 80/2000 MedleyA-PT-10-CTLFireability-2024-08 18760852 m, 119877 m/sec, 103468698 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 537 secs. Pages in use: 261
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 155/401 82/2000 MedleyA-PT-10-CTLFireability-2024-08 19290365 m, 105902 m/sec, 106858526 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 542 secs. Pages in use: 263
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 160/401 85/2000 MedleyA-PT-10-CTLFireability-2024-08 19859318 m, 113790 m/sec, 110188537 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 547 secs. Pages in use: 266
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 165/401 87/2000 MedleyA-PT-10-CTLFireability-2024-08 20408804 m, 109897 m/sec, 113673405 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 552 secs. Pages in use: 268
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 170/401 89/2000 MedleyA-PT-10-CTLFireability-2024-08 20891085 m, 96456 m/sec, 117152249 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 557 secs. Pages in use: 270
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 175/401 91/2000 MedleyA-PT-10-CTLFireability-2024-08 21428864 m, 107555 m/sec, 120425439 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 562 secs. Pages in use: 272
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 180/401 93/2000 MedleyA-PT-10-CTLFireability-2024-08 21947171 m, 103661 m/sec, 123806038 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 567 secs. Pages in use: 274
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 185/401 96/2000 MedleyA-PT-10-CTLFireability-2024-08 22462644 m, 103094 m/sec, 127149481 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 572 secs. Pages in use: 277
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 190/401 98/2000 MedleyA-PT-10-CTLFireability-2024-08 22960351 m, 99541 m/sec, 130529034 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 577 secs. Pages in use: 279
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 195/401 100/2000 MedleyA-PT-10-CTLFireability-2024-08 23421045 m, 92138 m/sec, 133878136 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 582 secs. Pages in use: 281
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 200/401 102/2000 MedleyA-PT-10-CTLFireability-2024-08 23926984 m, 101187 m/sec, 137374543 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 587 secs. Pages in use: 283
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 205/401 104/2000 MedleyA-PT-10-CTLFireability-2024-08 24420761 m, 98755 m/sec, 140847151 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 592 secs. Pages in use: 285
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 210/401 106/2000 MedleyA-PT-10-CTLFireability-2024-08 24949821 m, 105812 m/sec, 144268510 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 597 secs. Pages in use: 287
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 215/401 108/2000 MedleyA-PT-10-CTLFireability-2024-08 25447651 m, 99566 m/sec, 147615440 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 602 secs. Pages in use: 289
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 220/401 111/2000 MedleyA-PT-10-CTLFireability-2024-08 25990709 m, 108611 m/sec, 150949316 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 607 secs. Pages in use: 292
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 225/401 113/2000 MedleyA-PT-10-CTLFireability-2024-08 26586868 m, 119231 m/sec, 154219989 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 612 secs. Pages in use: 294
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 230/401 116/2000 MedleyA-PT-10-CTLFireability-2024-08 27185245 m, 119675 m/sec, 157453367 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 617 secs. Pages in use: 297
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 235/401 118/2000 MedleyA-PT-10-CTLFireability-2024-08 27736017 m, 110154 m/sec, 160723186 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 622 secs. Pages in use: 299
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 240/401 120/2000 MedleyA-PT-10-CTLFireability-2024-08 28336211 m, 120038 m/sec, 164107392 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 627 secs. Pages in use: 301
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 245/401 123/2000 MedleyA-PT-10-CTLFireability-2024-08 28864228 m, 105603 m/sec, 167320666 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 632 secs. Pages in use: 304
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 250/401 125/2000 MedleyA-PT-10-CTLFireability-2024-08 29440418 m, 115238 m/sec, 170659979 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 637 secs. Pages in use: 306
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 255/401 127/2000 MedleyA-PT-10-CTLFireability-2024-08 29990236 m, 109963 m/sec, 174043412 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 642 secs. Pages in use: 308
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 260/401 130/2000 MedleyA-PT-10-CTLFireability-2024-08 30612117 m, 124376 m/sec, 177335103 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 647 secs. Pages in use: 311
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 265/401 133/2000 MedleyA-PT-10-CTLFireability-2024-08 31274273 m, 132431 m/sec, 180657200 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 652 secs. Pages in use: 314
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 270/401 135/2000 MedleyA-PT-10-CTLFireability-2024-08 31820832 m, 109311 m/sec, 184119165 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 657 secs. Pages in use: 316
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 275/401 138/2000 MedleyA-PT-10-CTLFireability-2024-08 32438056 m, 123444 m/sec, 187419302 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 662 secs. Pages in use: 319
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 280/401 140/2000 MedleyA-PT-10-CTLFireability-2024-08 33069845 m, 126357 m/sec, 190630235 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 667 secs. Pages in use: 321
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 285/401 143/2000 MedleyA-PT-10-CTLFireability-2024-08 33647538 m, 115538 m/sec, 193921955 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 672 secs. Pages in use: 324
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 290/401 145/2000 MedleyA-PT-10-CTLFireability-2024-08 34238428 m, 118178 m/sec, 197139593 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 677 secs. Pages in use: 326
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 295/401 148/2000 MedleyA-PT-10-CTLFireability-2024-08 34821104 m, 116535 m/sec, 200395048 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 682 secs. Pages in use: 329
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 300/401 150/2000 MedleyA-PT-10-CTLFireability-2024-08 35366183 m, 109015 m/sec, 203736755 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 687 secs. Pages in use: 331
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 305/401 153/2000 MedleyA-PT-10-CTLFireability-2024-08 36000463 m, 126856 m/sec, 207020313 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 692 secs. Pages in use: 334
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 310/401 155/2000 MedleyA-PT-10-CTLFireability-2024-08 36595972 m, 119101 m/sec, 210313397 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 697 secs. Pages in use: 336
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 315/401 158/2000 MedleyA-PT-10-CTLFireability-2024-08 37161504 m, 113106 m/sec, 213599051 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 702 secs. Pages in use: 339
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 320/401 160/2000 MedleyA-PT-10-CTLFireability-2024-08 37729441 m, 113587 m/sec, 216711349 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 707 secs. Pages in use: 341
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 325/401 162/2000 MedleyA-PT-10-CTLFireability-2024-08 38212867 m, 96685 m/sec, 220028760 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 712 secs. Pages in use: 343
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 330/401 164/2000 MedleyA-PT-10-CTLFireability-2024-08 38690013 m, 95429 m/sec, 223180031 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 717 secs. Pages in use: 345
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 335/401 166/2000 MedleyA-PT-10-CTLFireability-2024-08 39187966 m, 99590 m/sec, 226526202 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 722 secs. Pages in use: 347
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 340/401 169/2000 MedleyA-PT-10-CTLFireability-2024-08 39734812 m, 109369 m/sec, 229721850 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 727 secs. Pages in use: 350
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 345/401 171/2000 MedleyA-PT-10-CTLFireability-2024-08 40210863 m, 95210 m/sec, 232995161 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 732 secs. Pages in use: 352
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 350/401 173/2000 MedleyA-PT-10-CTLFireability-2024-08 40638733 m, 85574 m/sec, 236036452 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 737 secs. Pages in use: 354
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 355/401 175/2000 MedleyA-PT-10-CTLFireability-2024-08 41150606 m, 102374 m/sec, 239262700 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 742 secs. Pages in use: 356
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 360/401 177/2000 MedleyA-PT-10-CTLFireability-2024-08 41670224 m, 103923 m/sec, 242411433 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 747 secs. Pages in use: 358
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 365/401 179/2000 MedleyA-PT-10-CTLFireability-2024-08 42166621 m, 99279 m/sec, 245629302 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 752 secs. Pages in use: 360
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 370/401 181/2000 MedleyA-PT-10-CTLFireability-2024-08 42721534 m, 110982 m/sec, 248860661 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 757 secs. Pages in use: 362
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 375/401 184/2000 MedleyA-PT-10-CTLFireability-2024-08 43273636 m, 110420 m/sec, 252066579 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 762 secs. Pages in use: 365
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 380/401 186/2000 MedleyA-PT-10-CTLFireability-2024-08 43873720 m, 120016 m/sec, 255211645 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 767 secs. Pages in use: 367
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 385/401 189/2000 MedleyA-PT-10-CTLFireability-2024-08 44426308 m, 110517 m/sec, 258362148 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 772 secs. Pages in use: 370
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 390/401 191/2000 MedleyA-PT-10-CTLFireability-2024-08 44984721 m, 111682 m/sec, 261499886 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 777 secs. Pages in use: 372
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 395/401 193/2000 MedleyA-PT-10-CTLFireability-2024-08 45483696 m, 99795 m/sec, 264762261 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 782 secs. Pages in use: 374
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 400/401 195/2000 MedleyA-PT-10-CTLFireability-2024-08 45995569 m, 102374 m/sec, 267911984 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 787 secs. Pages in use: 376
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 41 (type EXCL) for MedleyA-PT-10-CTLFireability-2024-08 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 792 secs. Pages in use: 378
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 16 (type EXCL) for 15 MedleyA-PT-10-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 401 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 41 (type EXCL) for 40 MedleyA-PT-10-CTLFireability-2024-08
[[35mlola[0m][I] time limit : 2808 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 16 (type EXCL) for MedleyA-PT-10-CTLFireability-2024-05
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 33
[[35mlola[0m][I] fired transitions : 32
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 5/401 4/5 MedleyA-PT-10-CTLFireability-2024-08 926973 m, -9013719 m/sec, 3474720 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 797 secs. Pages in use: 382
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 41 (type EXCL) for MedleyA-PT-10-CTLFireability-2024-08 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-00: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-06: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMedleyA-PT-10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMedleyA-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MedleyA-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 802 secs. Pages in use: 383
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 10 (type EXCL) for 9 MedleyA-PT-10-CTLFireability-2024-03
[[35mlola[0m][I] time limit : 466 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 10 (type EXCL) for MedleyA-PT-10-CTLFireability-2024-03
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 28
[[35mlola[0m][I] fired transitions : 27
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 7 (type EXCL) for 6 MedleyA-PT-10-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 559 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 7 (type EXCL) for MedleyA-PT-10-CTLFireability-2024-02
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 19506
[[35mlola[0m][I] fired transitions : 92641
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 62 (type EXCL) for 61 MedleyA-PT-10-CTLFireability-2024-15
[[35mlola[0m][I] time limit : 699 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 62 (type EXCL) for MedleyA-PT-10-CTLFireability-2024-15
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 27093
[[35mlola[0m][I] fired transitions : 117197
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 53 (type EXCL) for 52 MedleyA-PT-10-CTLFireability-2024-12
[[35mlola[0m][I] time limit : 932 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 53 (type EXCL) for MedleyA-PT-10-CTLFireability-2024-12
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 13
[[35mlola[0m][I] fired transitions : 51
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 4 (type EXCL) for 3 MedleyA-PT-10-CTLFireability-2024-01
[[35mlola[0m][I] time limit : 1399 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 4 (type EXCL) for MedleyA-PT-10-CTLFireability-2024-01
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 21
[[35mlola[0m][I] fired transitions : 21
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 38 (type EXCL) for 37 MedleyA-PT-10-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 2798 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 38 (type EXCL) for MedleyA-PT-10-CTLFireability-2024-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 53404
[[35mlola[0m][I] fired transitions : 230354
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] Portfolio finished: no open tasks 16
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="MedleyA-PT-10"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is MedleyA-PT-10, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r577-smll-171734920400074"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/MedleyA-PT-10.tgz
mv MedleyA-PT-10 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;