fond
Model Checking Contest 2024
14th edition, Geneva, Switzerland, June 25, 2024
Execution of r553-tall-171734901100198
Last Updated
July 7, 2024

About the Execution of LTSMin+red for FireWire-PT-04

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
347.023 22675.00 49168.00 109.20 FFFFTTTTTFFTFFFF normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r553-tall-171734901100198.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool ltsminxred
Input is FireWire-PT-04, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r553-tall-171734901100198
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 524K
-rw-r--r-- 1 mcc users 6.2K Jun 2 17:16 CTLCardinality.txt
-rw-r--r-- 1 mcc users 71K Jun 2 17:16 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.1K Jun 2 17:16 CTLFireability.txt
-rw-r--r-- 1 mcc users 48K Jun 2 17:16 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.2K Jun 2 17:12 LTLCardinality.txt
-rw-r--r-- 1 mcc users 23K Jun 2 17:12 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Jun 2 17:12 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Jun 2 17:12 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 Jun 2 16:33 NewModel
-rw-r--r-- 1 mcc users 13K Jun 2 17:16 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 137K Jun 2 17:16 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 6.9K Jun 2 17:16 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 58K Jun 2 17:16 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Jun 2 17:12 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Jun 2 17:12 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Jun 2 16:33 equiv_col
-rw-r--r-- 1 mcc users 3 Jun 2 16:33 instance
-rw-r--r-- 1 mcc users 6 Jun 2 16:33 iscolored
-rw-r--r-- 1 mcc users 89K Jun 2 16:33 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME FireWire-PT-04-ReachabilityCardinality-2024-00
FORMULA_NAME FireWire-PT-04-ReachabilityCardinality-2024-01
FORMULA_NAME FireWire-PT-04-ReachabilityCardinality-2024-02
FORMULA_NAME FireWire-PT-04-ReachabilityCardinality-2024-03
FORMULA_NAME FireWire-PT-04-ReachabilityCardinality-2024-04
FORMULA_NAME FireWire-PT-04-ReachabilityCardinality-2024-05
FORMULA_NAME FireWire-PT-04-ReachabilityCardinality-2024-06
FORMULA_NAME FireWire-PT-04-ReachabilityCardinality-2024-07
FORMULA_NAME FireWire-PT-04-ReachabilityCardinality-2024-08
FORMULA_NAME FireWire-PT-04-ReachabilityCardinality-2024-09
FORMULA_NAME FireWire-PT-04-ReachabilityCardinality-2024-10
FORMULA_NAME FireWire-PT-04-ReachabilityCardinality-2024-11
FORMULA_NAME FireWire-PT-04-ReachabilityCardinality-2024-12
FORMULA_NAME FireWire-PT-04-ReachabilityCardinality-2024-13
FORMULA_NAME FireWire-PT-04-ReachabilityCardinality-2024-14
FORMULA_NAME FireWire-PT-04-ReachabilityCardinality-2024-15

=== Now, execution of the tool begins

BK_START 1717353871142

Invoking MCC driver with
BK_TOOL=ltsminxred
BK_EXAMINATION=ReachabilityCardinality
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=FireWire-PT-04
BK_MEMORY_CONFINEMENT=16384
Applying reductions before tool ltsmin
Invoking reducer
Running Version 202405141337
[2024-06-02 18:44:32] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityCardinality, -timeout, 360, -rebuildPNML]
[2024-06-02 18:44:32] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2024-06-02 18:44:32] [INFO ] Load time of PNML (sax parser for PT used): 72 ms
[2024-06-02 18:44:32] [INFO ] Transformed 113 places.
[2024-06-02 18:44:32] [INFO ] Transformed 364 transitions.
[2024-06-02 18:44:32] [INFO ] Found NUPN structural information;
[2024-06-02 18:44:32] [INFO ] Parsed PT model containing 113 places and 364 transitions and 1349 arcs in 163 ms.
Parsed 16 properties from file /home/mcc/execution/ReachabilityCardinality.xml in 19 ms.
Working with output stream class java.io.PrintStream
Ensure Unique test removed 56 transitions
Reduce redundant transitions removed 56 transitions.
FORMULA FireWire-PT-04-ReachabilityCardinality-2024-00 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA FireWire-PT-04-ReachabilityCardinality-2024-01 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA FireWire-PT-04-ReachabilityCardinality-2024-05 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA FireWire-PT-04-ReachabilityCardinality-2024-06 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA FireWire-PT-04-ReachabilityCardinality-2024-08 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA FireWire-PT-04-ReachabilityCardinality-2024-14 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
RANDOM walk for 40000 steps (2196 resets) in 2437 ms. (16 steps per ms) remains 10/10 properties
BEST_FIRST walk for 40003 steps (709 resets) in 419 ms. (95 steps per ms) remains 10/10 properties
BEST_FIRST walk for 40003 steps (18 resets) in 758 ms. (52 steps per ms) remains 9/10 properties
FORMULA FireWire-PT-04-ReachabilityCardinality-2024-03 FALSE TECHNIQUES TOPOLOGICAL BESTFIRST_WALK
BEST_FIRST walk for 40002 steps (615 resets) in 476 ms. (83 steps per ms) remains 9/9 properties
BEST_FIRST walk for 40003 steps (574 resets) in 587 ms. (68 steps per ms) remains 9/9 properties
BEST_FIRST walk for 40003 steps (1540 resets) in 149 ms. (266 steps per ms) remains 9/9 properties
BEST_FIRST walk for 40002 steps (1752 resets) in 181 ms. (219 steps per ms) remains 9/9 properties
BEST_FIRST walk for 40001 steps (612 resets) in 123 ms. (322 steps per ms) remains 9/9 properties
BEST_FIRST walk for 40002 steps (578 resets) in 140 ms. (283 steps per ms) remains 9/9 properties
BEST_FIRST walk for 40004 steps (523 resets) in 95 ms. (416 steps per ms) remains 9/9 properties
BEST_FIRST walk for 40004 steps (588 resets) in 88 ms. (449 steps per ms) remains 8/9 properties
FORMULA FireWire-PT-04-ReachabilityCardinality-2024-15 FALSE TECHNIQUES TOPOLOGICAL BESTFIRST_WALK
[2024-06-02 18:44:34] [INFO ] Flow matrix only has 276 transitions (discarded 32 similar events)
// Phase 1: matrix 276 rows 113 cols
[2024-06-02 18:44:34] [INFO ] Computed 8 invariants in 12 ms
[2024-06-02 18:44:34] [INFO ] State equation strengthened by 40 read => feed constraints.
Problem FireWire-PT-04-ReachabilityCardinality-2024-09 is UNSAT
FORMULA FireWire-PT-04-ReachabilityCardinality-2024-09 FALSE TECHNIQUES SMT_REFINEMENT
Problem FireWire-PT-04-ReachabilityCardinality-2024-10 is UNSAT
FORMULA FireWire-PT-04-ReachabilityCardinality-2024-10 FALSE TECHNIQUES SMT_REFINEMENT
All remaining problems are real, not stopping.
At refinement iteration 0 (INCLUDED_ONLY) 0/91 variables, 91/91 constraints. Problems are: Problem set: 2 solved, 6 unsolved
At refinement iteration 1 (INCLUDED_ONLY) 0/91 variables, 3/94 constraints. Problems are: Problem set: 2 solved, 6 unsolved
At refinement iteration 2 (INCLUDED_ONLY) 0/91 variables, 0/94 constraints. Problems are: Problem set: 2 solved, 6 unsolved
Problem FireWire-PT-04-ReachabilityCardinality-2024-13 is UNSAT
FORMULA FireWire-PT-04-ReachabilityCardinality-2024-13 FALSE TECHNIQUES SMT_REFINEMENT
At refinement iteration 3 (OVERLAPS) 22/113 variables, 5/99 constraints. Problems are: Problem set: 3 solved, 5 unsolved
At refinement iteration 4 (INCLUDED_ONLY) 0/113 variables, 22/121 constraints. Problems are: Problem set: 3 solved, 5 unsolved
At refinement iteration 5 (INCLUDED_ONLY) 0/113 variables, 0/121 constraints. Problems are: Problem set: 3 solved, 5 unsolved
At refinement iteration 6 (OVERLAPS) 275/388 variables, 113/234 constraints. Problems are: Problem set: 3 solved, 5 unsolved
At refinement iteration 7 (INCLUDED_ONLY) 0/388 variables, 39/273 constraints. Problems are: Problem set: 3 solved, 5 unsolved
At refinement iteration 8 (INCLUDED_ONLY) 0/388 variables, 0/273 constraints. Problems are: Problem set: 3 solved, 5 unsolved
At refinement iteration 9 (OVERLAPS) 1/389 variables, 1/274 constraints. Problems are: Problem set: 3 solved, 5 unsolved
At refinement iteration 10 (INCLUDED_ONLY) 0/389 variables, 0/274 constraints. Problems are: Problem set: 3 solved, 5 unsolved
At refinement iteration 11 (OVERLAPS) 0/389 variables, 0/274 constraints. Problems are: Problem set: 3 solved, 5 unsolved
No progress, stopping.
After SMT solving in domain Real declared 389/389 variables, and 274 constraints, problems are : Problem set: 3 solved, 5 unsolved in 686 ms.
Refiners :[Domain max(s): 113/113 constraints, Positive P Invariants (semi-flows): 8/8 constraints, State Equation: 113/113 constraints, ReadFeed: 40/40 constraints, PredecessorRefiner: 8/8 constraints, Known Traps: 0/0 constraints]
Escalating to Integer solving :Problem set: 3 solved, 5 unsolved
At refinement iteration 0 (INCLUDED_ONLY) 0/69 variables, 69/69 constraints. Problems are: Problem set: 3 solved, 5 unsolved
At refinement iteration 1 (INCLUDED_ONLY) 0/69 variables, 1/70 constraints. Problems are: Problem set: 3 solved, 5 unsolved
At refinement iteration 2 (INCLUDED_ONLY) 0/69 variables, 0/70 constraints. Problems are: Problem set: 3 solved, 5 unsolved
At refinement iteration 3 (OVERLAPS) 44/113 variables, 7/77 constraints. Problems are: Problem set: 3 solved, 5 unsolved
At refinement iteration 4 (INCLUDED_ONLY) 0/113 variables, 44/121 constraints. Problems are: Problem set: 3 solved, 5 unsolved
[2024-06-02 18:44:35] [INFO ] Deduced a trap composed of 37 places in 85 ms of which 11 ms to minimize.
At refinement iteration 5 (INCLUDED_ONLY) 0/113 variables, 1/122 constraints. Problems are: Problem set: 3 solved, 5 unsolved
[2024-06-02 18:44:35] [INFO ] Deduced a trap composed of 15 places in 106 ms of which 1 ms to minimize.
[2024-06-02 18:44:35] [INFO ] Deduced a trap composed of 13 places in 86 ms of which 1 ms to minimize.
At refinement iteration 6 (INCLUDED_ONLY) 0/113 variables, 2/124 constraints. Problems are: Problem set: 3 solved, 5 unsolved
At refinement iteration 7 (INCLUDED_ONLY) 0/113 variables, 0/124 constraints. Problems are: Problem set: 3 solved, 5 unsolved
At refinement iteration 8 (OVERLAPS) 275/388 variables, 113/237 constraints. Problems are: Problem set: 3 solved, 5 unsolved
At refinement iteration 9 (INCLUDED_ONLY) 0/388 variables, 39/276 constraints. Problems are: Problem set: 3 solved, 5 unsolved
At refinement iteration 10 (INCLUDED_ONLY) 0/388 variables, 5/281 constraints. Problems are: Problem set: 3 solved, 5 unsolved
[2024-06-02 18:44:35] [INFO ] Deduced a trap composed of 17 places in 30 ms of which 1 ms to minimize.
[2024-06-02 18:44:35] [INFO ] Deduced a trap composed of 17 places in 35 ms of which 1 ms to minimize.
At refinement iteration 11 (INCLUDED_ONLY) 0/388 variables, 2/283 constraints. Problems are: Problem set: 3 solved, 5 unsolved
At refinement iteration 12 (INCLUDED_ONLY) 0/388 variables, 0/283 constraints. Problems are: Problem set: 3 solved, 5 unsolved
At refinement iteration 13 (OVERLAPS) 1/389 variables, 1/284 constraints. Problems are: Problem set: 3 solved, 5 unsolved
At refinement iteration 14 (INCLUDED_ONLY) 0/389 variables, 0/284 constraints. Problems are: Problem set: 3 solved, 5 unsolved
At refinement iteration 15 (OVERLAPS) 0/389 variables, 0/284 constraints. Problems are: Problem set: 3 solved, 5 unsolved
No progress, stopping.
After SMT solving in domain Int declared 389/389 variables, and 284 constraints, problems are : Problem set: 3 solved, 5 unsolved in 1522 ms.
Refiners :[Domain max(s): 113/113 constraints, Positive P Invariants (semi-flows): 8/8 constraints, State Equation: 113/113 constraints, ReadFeed: 40/40 constraints, PredecessorRefiner: 5/8 constraints, Known Traps: 5/5 constraints]
After SMT, in 2359ms problems are : Problem set: 3 solved, 5 unsolved
Parikh walk visited 0 properties in 13875 ms.
Support contains 69 out of 113 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 113/113 places, 308/308 transitions.
Drop transitions (Empty/Sink Transition effects.) removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 0 with 3 rules applied. Total rules applied 3 place count 113 transition count 305
Discarding 1 places :
Symmetric choice reduction at 1 with 1 rule applications. Total rules 4 place count 112 transition count 303
Iterating global reduction 1 with 1 rules applied. Total rules applied 5 place count 112 transition count 303
Drop transitions (Redundant composition of simpler transitions.) removed 6 transitions
Redundant transition composition rules discarded 6 transitions
Iterating global reduction 1 with 6 rules applied. Total rules applied 11 place count 112 transition count 297
Free-agglomeration rule (complex) applied 1 times.
Iterating global reduction 1 with 1 rules applied. Total rules applied 12 place count 112 transition count 299
Reduce places removed 1 places and 0 transitions.
Drop transitions (Empty/Sink Transition effects.) removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 1 with 3 rules applied. Total rules applied 15 place count 111 transition count 297
Drop transitions (Redundant composition of simpler transitions.) removed 2 transitions
Redundant transition composition rules discarded 2 transitions
Iterating global reduction 2 with 2 rules applied. Total rules applied 17 place count 111 transition count 295
Partial Free-agglomeration rule applied 2 times.
Drop transitions (Partial Free agglomeration) removed 2 transitions
Iterating global reduction 2 with 2 rules applied. Total rules applied 19 place count 111 transition count 295
Applied a total of 19 rules in 69 ms. Remains 111 /113 variables (removed 2) and now considering 295/308 (removed 13) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 79 ms. Remains : 111/113 places, 295/308 transitions.
RANDOM walk for 40000 steps (2265 resets) in 365 ms. (109 steps per ms) remains 5/5 properties
BEST_FIRST walk for 40003 steps (683 resets) in 117 ms. (339 steps per ms) remains 5/5 properties
BEST_FIRST walk for 40004 steps (559 resets) in 111 ms. (357 steps per ms) remains 5/5 properties
BEST_FIRST walk for 40003 steps (595 resets) in 170 ms. (233 steps per ms) remains 5/5 properties
BEST_FIRST walk for 40002 steps (603 resets) in 71 ms. (555 steps per ms) remains 5/5 properties
BEST_FIRST walk for 40004 steps (600 resets) in 70 ms. (563 steps per ms) remains 5/5 properties
Finished probabilistic random walk after 1616372 steps, run visited all 5 properties in 2815 ms. (steps per millisecond=574 )
Probabilistic random walk after 1616372 steps, saw 364050 distinct states, run finished after 2819 ms. (steps per millisecond=573 ) properties seen :5
FORMULA FireWire-PT-04-ReachabilityCardinality-2024-12 FALSE TECHNIQUES TOPOLOGICAL PROBABILISTIC_WALK
FORMULA FireWire-PT-04-ReachabilityCardinality-2024-11 TRUE TECHNIQUES TOPOLOGICAL PROBABILISTIC_WALK
FORMULA FireWire-PT-04-ReachabilityCardinality-2024-07 TRUE TECHNIQUES TOPOLOGICAL PROBABILISTIC_WALK
FORMULA FireWire-PT-04-ReachabilityCardinality-2024-04 TRUE TECHNIQUES TOPOLOGICAL PROBABILISTIC_WALK
FORMULA FireWire-PT-04-ReachabilityCardinality-2024-02 FALSE TECHNIQUES TOPOLOGICAL PROBABILISTIC_WALK
All properties solved without resorting to model-checking.
Total runtime 21491 ms.
ITS solved all properties within timeout

BK_STOP 1717353893817

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202405141337.jar
++ perl -pe 's/.*\.//g'
+ VERSION=202405141337
+ echo 'Running Version 202405141337'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination ReachabilityCardinality -timeout 360 -rebuildPNML

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="FireWire-PT-04"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="ltsminxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool ltsminxred"
echo " Input is FireWire-PT-04, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r553-tall-171734901100198"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/FireWire-PT-04.tgz
mv FireWire-PT-04 execution
cd execution
if [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "UpperBounds" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] || [ "ReachabilityCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME ReachabilityCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;