About the Execution of LoLA for FireWire-PT-19
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
9599.739 | 3600000.00 | 969228.00 | 9642.40 | [undef] | Time out reached |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r551-tall-171734899900315.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is FireWire-PT-19, examination is LTLCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r551-tall-171734899900315
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 668K
-rw-r--r-- 1 mcc users 7.8K Jun 2 17:16 CTLCardinality.txt
-rw-r--r-- 1 mcc users 89K Jun 2 17:16 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.2K Jun 2 17:16 CTLFireability.txt
-rw-r--r-- 1 mcc users 58K Jun 2 17:16 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.3K Jun 2 17:12 LTLCardinality.txt
-rw-r--r-- 1 mcc users 23K Jun 2 17:12 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Jun 2 17:12 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K Jun 2 17:12 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 Jun 2 16:33 NewModel
-rw-r--r-- 1 mcc users 9.5K Jun 2 17:16 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 100K Jun 2 17:16 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.4K Jun 2 17:16 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 73K Jun 2 17:16 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Jun 2 17:12 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Jun 2 17:12 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Jun 2 16:33 equiv_col
-rw-r--r-- 1 mcc users 3 Jun 2 16:33 instance
-rw-r--r-- 1 mcc users 6 Jun 2 16:33 iscolored
-rw-r--r-- 1 mcc users 221K Jun 2 16:33 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME FireWire-PT-19-LTLCardinality-00
FORMULA_NAME FireWire-PT-19-LTLCardinality-01
FORMULA_NAME FireWire-PT-19-LTLCardinality-02
FORMULA_NAME FireWire-PT-19-LTLCardinality-03
FORMULA_NAME FireWire-PT-19-LTLCardinality-04
FORMULA_NAME FireWire-PT-19-LTLCardinality-05
FORMULA_NAME FireWire-PT-19-LTLCardinality-06
FORMULA_NAME FireWire-PT-19-LTLCardinality-07
FORMULA_NAME FireWire-PT-19-LTLCardinality-08
FORMULA_NAME FireWire-PT-19-LTLCardinality-09
FORMULA_NAME FireWire-PT-19-LTLCardinality-10
FORMULA_NAME FireWire-PT-19-LTLCardinality-11
FORMULA_NAME FireWire-PT-19-LTLCardinality-12
FORMULA_NAME FireWire-PT-19-LTLCardinality-13
FORMULA_NAME FireWire-PT-19-LTLCardinality-14
FORMULA_NAME FireWire-PT-19-LTLCardinality-15
=== Now, execution of the tool begins
BK_START 1717427697226
starting LoLA
BK_EXAMINATION: LTLCardinality
BK_TIME_CONFINEMENT: 3600
BK_MEMORY_CONFINEMENT: 16384
BK_BIN_PATH: /home/mcc/BenchKit/bin/
current directory: /home/mcc/execution
BK_TIME_CONFINEMENT_REACHED
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mLTLCardinality.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 44 (type CNST) for 43 FireWire-PT-19-LTLCardinality-13
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] LAUNCH task # 29 (type CNST) for 28 FireWire-PT-19-LTLCardinality-08
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 29 (type CNST) for FireWire-PT-19-LTLCardinality-08
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 44 (type CNST) for FireWire-PT-19-LTLCardinality-13
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 11 (type CNST) for 10 FireWire-PT-19-LTLCardinality-02
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 11 (type CNST) for FireWire-PT-19-LTLCardinality-02
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 8 (type EXCL) for 7 FireWire-PT-19-LTLCardinality-01
[[35mlola[0m][I] time limit : 238 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 8 (type EXCL) for FireWire-PT-19-LTLCardinality-01
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 3 (type EXCL) for 0 FireWire-PT-19-LTLCardinality-00
[[35mlola[0m][I] time limit : 274 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 3 (type EXCL) for FireWire-PT-19-LTLCardinality-00
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 18143
[[35mlola[0m][I] fired transitions : 34779
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 50 (type EXCL) for 49 FireWire-PT-19-LTLCardinality-15
[[35mlola[0m][I] time limit : 324 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 50 (type EXCL) for FireWire-PT-19-LTLCardinality-15
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 4
[[35mlola[0m][I] fired transitions : 3
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 47 (type EXCL) for 46 FireWire-PT-19-LTLCardinality-14
[[35mlola[0m][I] time limit : 357 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 47 (type EXCL) for FireWire-PT-19-LTLCardinality-14
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 24
[[35mlola[0m][I] fired transitions : 32
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 41 (type EXCL) for 40 FireWire-PT-19-LTLCardinality-12
[[35mlola[0m][I] time limit : 397 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 41 (type EXCL) for FireWire-PT-19-LTLCardinality-12
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 96
[[35mlola[0m][I] fired transitions : 96
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 38 (type EXCL) for 37 FireWire-PT-19-LTLCardinality-11
[[35mlola[0m][I] time limit : 446 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 LTL EXCL 4/446 5/2000 FireWire-PT-19-LTLCardinality-11 615307 m, 123061 m/sec, 2149407 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 30 secs. Pages in use: 5
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 LTL EXCL 9/446 9/2000 FireWire-PT-19-LTLCardinality-11 1250654 m, 127069 m/sec, 4460221 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 35 secs. Pages in use: 9
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 LTL EXCL 14/446 14/2000 FireWire-PT-19-LTLCardinality-11 1905095 m, 130888 m/sec, 6869013 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 40 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 38 (type EXCL) for FireWire-PT-19-LTLCardinality-11
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 2426709
[[35mlola[0m][I] fired transitions : 8735733
[[35mlola[0m][I] time used : 18
[[35mlola[0m][I] memory pages used : 18
[[35mlola[0m][I] LAUNCH task # 35 (type EXCL) for 34 FireWire-PT-19-LTLCardinality-10
[[35mlola[0m][I] time limit : 508 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 35 (type EXCL) for FireWire-PT-19-LTLCardinality-10
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 91
[[35mlola[0m][I] fired transitions : 91
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 26 (type EXCL) for 25 FireWire-PT-19-LTLCardinality-07
[[35mlola[0m][I] time limit : 592 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 26 (type EXCL) for FireWire-PT-19-LTLCardinality-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 23 (type EXCL) for 22 FireWire-PT-19-LTLCardinality-06
[[35mlola[0m][I] time limit : 711 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 23 (type EXCL) for FireWire-PT-19-LTLCardinality-06
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 91
[[35mlola[0m][I] fired transitions : 91
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 17 (type EXCL) for 16 FireWire-PT-19-LTLCardinality-04
[[35mlola[0m][I] time limit : 889 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 1/889 1/2000 FireWire-PT-19-LTLCardinality-04 136714 m, 27342 m/sec, 411001 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 45 secs. Pages in use: 18
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 6/889 6/2000 FireWire-PT-19-LTLCardinality-04 782111 m, 129079 m/sec, 2842916 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 50 secs. Pages in use: 18
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 11/889 11/2000 FireWire-PT-19-LTLCardinality-04 1456985 m, 134974 m/sec, 5180977 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 55 secs. Pages in use: 18
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 16/889 15/2000 FireWire-PT-19-LTLCardinality-04 2077839 m, 124170 m/sec, 7586198 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 60 secs. Pages in use: 18
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 21/889 20/2000 FireWire-PT-19-LTLCardinality-04 2725528 m, 129537 m/sec, 9719857 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 65 secs. Pages in use: 20
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 26/889 24/2000 FireWire-PT-19-LTLCardinality-04 3243192 m, 103532 m/sec, 11878635 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 70 secs. Pages in use: 24
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 31/889 27/2000 FireWire-PT-19-LTLCardinality-04 3742924 m, 99946 m/sec, 13881030 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 75 secs. Pages in use: 27
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 36/889 30/2000 FireWire-PT-19-LTLCardinality-04 4152697 m, 81954 m/sec, 15798702 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 80 secs. Pages in use: 30
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 41/889 33/2000 FireWire-PT-19-LTLCardinality-04 4572481 m, 83956 m/sec, 17646763 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 85 secs. Pages in use: 33
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 46/889 36/2000 FireWire-PT-19-LTLCardinality-04 5080022 m, 101508 m/sec, 19473771 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 90 secs. Pages in use: 36
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 51/889 40/2000 FireWire-PT-19-LTLCardinality-04 5593369 m, 102669 m/sec, 21380842 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 95 secs. Pages in use: 40
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 56/889 43/2000 FireWire-PT-19-LTLCardinality-04 6046965 m, 90719 m/sec, 23259396 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 100 secs. Pages in use: 43
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 61/889 46/2000 FireWire-PT-19-LTLCardinality-04 6470234 m, 84653 m/sec, 24979104 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 105 secs. Pages in use: 46
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 66/889 49/2000 FireWire-PT-19-LTLCardinality-04 6819806 m, 69914 m/sec, 26708871 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 110 secs. Pages in use: 49
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 71/889 51/2000 FireWire-PT-19-LTLCardinality-04 7210449 m, 78128 m/sec, 28369725 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 115 secs. Pages in use: 51
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 76/889 54/2000 FireWire-PT-19-LTLCardinality-04 7669906 m, 91891 m/sec, 30009419 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 120 secs. Pages in use: 54
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 81/889 57/2000 FireWire-PT-19-LTLCardinality-04 8066973 m, 79413 m/sec, 31809209 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 125 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 86/889 60/2000 FireWire-PT-19-LTLCardinality-04 8409669 m, 68539 m/sec, 33630134 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 130 secs. Pages in use: 60
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 91/889 62/2000 FireWire-PT-19-LTLCardinality-04 8772146 m, 72495 m/sec, 35416788 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 135 secs. Pages in use: 62
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 96/889 64/2000 FireWire-PT-19-LTLCardinality-04 9100268 m, 65624 m/sec, 37143333 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 140 secs. Pages in use: 64
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 101/889 66/2000 FireWire-PT-19-LTLCardinality-04 9390853 m, 58117 m/sec, 38879612 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 145 secs. Pages in use: 66
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 106/889 69/2000 FireWire-PT-19-LTLCardinality-04 9712919 m, 64413 m/sec, 40594260 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 150 secs. Pages in use: 69
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 111/889 71/2000 FireWire-PT-19-LTLCardinality-04 10077665 m, 72949 m/sec, 42263949 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 155 secs. Pages in use: 71
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 116/889 74/2000 FireWire-PT-19-LTLCardinality-04 10470692 m, 78605 m/sec, 44004150 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 160 secs. Pages in use: 74
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 121/889 76/2000 FireWire-PT-19-LTLCardinality-04 10817131 m, 69287 m/sec, 45805228 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 165 secs. Pages in use: 76
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 126/889 79/2000 FireWire-PT-19-LTLCardinality-04 11175243 m, 71622 m/sec, 47651650 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 170 secs. Pages in use: 79
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 131/889 81/2000 FireWire-PT-19-LTLCardinality-04 11532312 m, 71413 m/sec, 49392256 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 175 secs. Pages in use: 81
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 136/889 83/2000 FireWire-PT-19-LTLCardinality-04 11836024 m, 60742 m/sec, 51127993 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 180 secs. Pages in use: 83
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 141/889 86/2000 FireWire-PT-19-LTLCardinality-04 12135629 m, 59921 m/sec, 52829972 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 185 secs. Pages in use: 86
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 146/889 88/2000 FireWire-PT-19-LTLCardinality-04 12466656 m, 66205 m/sec, 54471619 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 190 secs. Pages in use: 88
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 151/889 90/2000 FireWire-PT-19-LTLCardinality-04 12820599 m, 70788 m/sec, 56102083 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 195 secs. Pages in use: 90
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 156/889 93/2000 FireWire-PT-19-LTLCardinality-04 13219282 m, 79736 m/sec, 57886029 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 200 secs. Pages in use: 93
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 161/889 95/2000 FireWire-PT-19-LTLCardinality-04 13559338 m, 68011 m/sec, 59698695 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 205 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 166/889 98/2000 FireWire-PT-19-LTLCardinality-04 13932871 m, 74706 m/sec, 61534180 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 210 secs. Pages in use: 98
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 171/889 100/2000 FireWire-PT-19-LTLCardinality-04 14264749 m, 66375 m/sec, 63283411 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 215 secs. Pages in use: 100
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 176/889 102/2000 FireWire-PT-19-LTLCardinality-04 14558660 m, 58782 m/sec, 65037088 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 220 secs. Pages in use: 102
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 181/889 105/2000 FireWire-PT-19-LTLCardinality-04 14878566 m, 63981 m/sec, 66741335 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 225 secs. Pages in use: 105
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 186/889 107/2000 FireWire-PT-19-LTLCardinality-04 15240369 m, 72360 m/sec, 68395096 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 230 secs. Pages in use: 107
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 191/889 110/2000 FireWire-PT-19-LTLCardinality-04 15710382 m, 94002 m/sec, 70192960 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 235 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 196/889 114/2000 FireWire-PT-19-LTLCardinality-04 16163462 m, 90616 m/sec, 72117707 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 240 secs. Pages in use: 114
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 201/889 117/2000 FireWire-PT-19-LTLCardinality-04 16620119 m, 91331 m/sec, 73933959 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 245 secs. Pages in use: 117
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 206/889 119/2000 FireWire-PT-19-LTLCardinality-04 17007212 m, 77418 m/sec, 75701308 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 250 secs. Pages in use: 119
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 211/889 122/2000 FireWire-PT-19-LTLCardinality-04 17378630 m, 74283 m/sec, 77436251 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 255 secs. Pages in use: 122
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 216/889 125/2000 FireWire-PT-19-LTLCardinality-04 17832084 m, 90690 m/sec, 79091601 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 260 secs. Pages in use: 125
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 221/889 128/2000 FireWire-PT-19-LTLCardinality-04 18209399 m, 75463 m/sec, 80809486 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 265 secs. Pages in use: 128
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 226/889 130/2000 FireWire-PT-19-LTLCardinality-04 18503766 m, 58873 m/sec, 82600901 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 270 secs. Pages in use: 130
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 231/889 132/2000 FireWire-PT-19-LTLCardinality-04 18791054 m, 57457 m/sec, 84420900 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 275 secs. Pages in use: 132
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 236/889 134/2000 FireWire-PT-19-LTLCardinality-04 19088983 m, 59585 m/sec, 86162511 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 280 secs. Pages in use: 134
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 241/889 136/2000 FireWire-PT-19-LTLCardinality-04 19361562 m, 54515 m/sec, 87859853 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 285 secs. Pages in use: 136
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 246/889 138/2000 FireWire-PT-19-LTLCardinality-04 19614111 m, 50509 m/sec, 89559665 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 290 secs. Pages in use: 138
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 251/889 139/2000 FireWire-PT-19-LTLCardinality-04 19857677 m, 48713 m/sec, 91243234 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 295 secs. Pages in use: 139
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 256/889 141/2000 FireWire-PT-19-LTLCardinality-04 20123464 m, 53157 m/sec, 92863629 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 300 secs. Pages in use: 141
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 261/889 143/2000 FireWire-PT-19-LTLCardinality-04 20421484 m, 59604 m/sec, 94480366 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 305 secs. Pages in use: 143
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 266/889 146/2000 FireWire-PT-19-LTLCardinality-04 20770319 m, 69767 m/sec, 96166925 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 310 secs. Pages in use: 146
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 271/889 148/2000 FireWire-PT-19-LTLCardinality-04 21121686 m, 70273 m/sec, 97955910 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 315 secs. Pages in use: 148
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 276/889 151/2000 FireWire-PT-19-LTLCardinality-04 21470687 m, 69800 m/sec, 99783302 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 320 secs. Pages in use: 151
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 281/889 153/2000 FireWire-PT-19-LTLCardinality-04 21816099 m, 69082 m/sec, 101465849 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 325 secs. Pages in use: 153
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 286/889 155/2000 FireWire-PT-19-LTLCardinality-04 22127311 m, 62242 m/sec, 103165122 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 330 secs. Pages in use: 155
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 291/889 157/2000 FireWire-PT-19-LTLCardinality-04 22408159 m, 56169 m/sec, 104841376 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 335 secs. Pages in use: 157
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 296/889 159/2000 FireWire-PT-19-LTLCardinality-04 22729368 m, 64241 m/sec, 106469470 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 340 secs. Pages in use: 159
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 301/889 162/2000 FireWire-PT-19-LTLCardinality-04 23087797 m, 71685 m/sec, 108073157 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 345 secs. Pages in use: 162
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 306/889 165/2000 FireWire-PT-19-LTLCardinality-04 23474100 m, 77260 m/sec, 109796711 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 350 secs. Pages in use: 165
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 311/889 167/2000 FireWire-PT-19-LTLCardinality-04 23801650 m, 65510 m/sec, 111578989 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 355 secs. Pages in use: 167
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 316/889 169/2000 FireWire-PT-19-LTLCardinality-04 24165146 m, 72699 m/sec, 113369103 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 360 secs. Pages in use: 169
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 321/889 172/2000 FireWire-PT-19-LTLCardinality-04 24497551 m, 66481 m/sec, 115046612 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 365 secs. Pages in use: 172
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 326/889 174/2000 FireWire-PT-19-LTLCardinality-04 24793361 m, 59162 m/sec, 116736382 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 370 secs. Pages in use: 174
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 331/889 176/2000 FireWire-PT-19-LTLCardinality-04 25090201 m, 59368 m/sec, 118404662 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 375 secs. Pages in use: 176
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 336/889 178/2000 FireWire-PT-19-LTLCardinality-04 25418643 m, 65688 m/sec, 120017082 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 380 secs. Pages in use: 178
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 341/889 180/2000 FireWire-PT-19-LTLCardinality-04 25764063 m, 69084 m/sec, 121616304 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 385 secs. Pages in use: 180
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 346/889 183/2000 FireWire-PT-19-LTLCardinality-04 26074976 m, 62182 m/sec, 123312226 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 390 secs. Pages in use: 183
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 351/889 185/2000 FireWire-PT-19-LTLCardinality-04 26345399 m, 54084 m/sec, 125029783 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 395 secs. Pages in use: 185
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 356/889 187/2000 FireWire-PT-19-LTLCardinality-04 26635314 m, 57983 m/sec, 126823350 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 400 secs. Pages in use: 187
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 361/889 189/2000 FireWire-PT-19-LTLCardinality-04 26923979 m, 57733 m/sec, 128484846 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 405 secs. Pages in use: 189
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 366/889 190/2000 FireWire-PT-19-LTLCardinality-04 27188240 m, 52852 m/sec, 130153780 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 410 secs. Pages in use: 190
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 371/889 192/2000 FireWire-PT-19-LTLCardinality-04 27425529 m, 47457 m/sec, 131824989 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 415 secs. Pages in use: 192
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 376/889 194/2000 FireWire-PT-19-LTLCardinality-04 27682829 m, 51460 m/sec, 133478188 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 420 secs. Pages in use: 194
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 381/889 196/2000 FireWire-PT-19-LTLCardinality-04 27946481 m, 52730 m/sec, 135067494 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 425 secs. Pages in use: 196
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 386/889 198/2000 FireWire-PT-19-LTLCardinality-04 28240628 m, 58829 m/sec, 136655855 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 430 secs. Pages in use: 198
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 391/889 201/2000 FireWire-PT-19-LTLCardinality-04 28675168 m, 86908 m/sec, 138432389 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 435 secs. Pages in use: 201
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 396/889 204/2000 FireWire-PT-19-LTLCardinality-04 29158121 m, 96590 m/sec, 140249351 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 440 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 401/889 208/2000 FireWire-PT-19-LTLCardinality-04 29656017 m, 99579 m/sec, 141708647 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 445 secs. Pages in use: 208
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 406/889 211/2000 FireWire-PT-19-LTLCardinality-04 30147524 m, 98301 m/sec, 143492977 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 450 secs. Pages in use: 211
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 411/889 215/2000 FireWire-PT-19-LTLCardinality-04 30641189 m, 98733 m/sec, 145247683 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 455 secs. Pages in use: 215
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 416/889 217/2000 FireWire-PT-19-LTLCardinality-04 31050071 m, 81776 m/sec, 147120364 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 460 secs. Pages in use: 217
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 421/889 220/2000 FireWire-PT-19-LTLCardinality-04 31429458 m, 75877 m/sec, 148944254 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 465 secs. Pages in use: 220
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 426/889 223/2000 FireWire-PT-19-LTLCardinality-04 31841495 m, 82407 m/sec, 150742302 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 470 secs. Pages in use: 223
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 431/889 226/2000 FireWire-PT-19-LTLCardinality-04 32215083 m, 74717 m/sec, 152605233 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 475 secs. Pages in use: 226
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 436/889 228/2000 FireWire-PT-19-LTLCardinality-04 32622253 m, 81434 m/sec, 154340576 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 480 secs. Pages in use: 228
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 441/889 231/2000 FireWire-PT-19-LTLCardinality-04 33002524 m, 76054 m/sec, 156202989 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 485 secs. Pages in use: 231
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 446/889 234/2000 FireWire-PT-19-LTLCardinality-04 33395334 m, 78562 m/sec, 157951521 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 490 secs. Pages in use: 234
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 451/889 237/2000 FireWire-PT-19-LTLCardinality-04 33859627 m, 92858 m/sec, 159740423 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 495 secs. Pages in use: 237
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 456/889 240/2000 FireWire-PT-19-LTLCardinality-04 34346733 m, 97421 m/sec, 161417137 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 500 secs. Pages in use: 240
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 461/889 243/2000 FireWire-PT-19-LTLCardinality-04 34679248 m, 66503 m/sec, 163318334 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 505 secs. Pages in use: 243
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 466/889 245/2000 FireWire-PT-19-LTLCardinality-04 34986134 m, 61377 m/sec, 165166759 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 510 secs. Pages in use: 245
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 471/889 247/2000 FireWire-PT-19-LTLCardinality-04 35327265 m, 68226 m/sec, 166874240 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 515 secs. Pages in use: 247
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 476/889 250/2000 FireWire-PT-19-LTLCardinality-04 35703788 m, 75304 m/sec, 168701444 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 520 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 481/889 253/2000 FireWire-PT-19-LTLCardinality-04 36086099 m, 76462 m/sec, 170437289 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 525 secs. Pages in use: 253
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 486/889 255/2000 FireWire-PT-19-LTLCardinality-04 36475409 m, 77862 m/sec, 172200716 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 530 secs. Pages in use: 255
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 491/889 258/2000 FireWire-PT-19-LTLCardinality-04 36832956 m, 71509 m/sec, 173988923 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 535 secs. Pages in use: 258
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 496/889 260/2000 FireWire-PT-19-LTLCardinality-04 37212261 m, 75861 m/sec, 175681276 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 540 secs. Pages in use: 260
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 501/889 263/2000 FireWire-PT-19-LTLCardinality-04 37522774 m, 62102 m/sec, 177528071 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 545 secs. Pages in use: 263
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 506/889 265/2000 FireWire-PT-19-LTLCardinality-04 37832647 m, 61974 m/sec, 179304503 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 550 secs. Pages in use: 265
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 511/889 267/2000 FireWire-PT-19-LTLCardinality-04 38200728 m, 73616 m/sec, 181036271 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 555 secs. Pages in use: 267
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 516/889 270/2000 FireWire-PT-19-LTLCardinality-04 38575350 m, 74924 m/sec, 182913571 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 560 secs. Pages in use: 270
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 521/889 273/2000 FireWire-PT-19-LTLCardinality-04 38971743 m, 79278 m/sec, 184600692 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 565 secs. Pages in use: 273
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 526/889 275/2000 FireWire-PT-19-LTLCardinality-04 39354390 m, 76529 m/sec, 186440471 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 570 secs. Pages in use: 275
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 531/889 278/2000 FireWire-PT-19-LTLCardinality-04 39727298 m, 74581 m/sec, 188198922 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 575 secs. Pages in use: 278
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 536/889 281/2000 FireWire-PT-19-LTLCardinality-04 40120203 m, 78581 m/sec, 189839029 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 580 secs. Pages in use: 281
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 541/889 283/2000 FireWire-PT-19-LTLCardinality-04 40473485 m, 70656 m/sec, 191613894 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 585 secs. Pages in use: 283
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 546/889 286/2000 FireWire-PT-19-LTLCardinality-04 40848579 m, 75018 m/sec, 193227903 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 590 secs. Pages in use: 286
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 551/889 288/2000 FireWire-PT-19-LTLCardinality-04 41217100 m, 73704 m/sec, 194666547 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 595 secs. Pages in use: 288
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 556/889 291/2000 FireWire-PT-19-LTLCardinality-04 41609529 m, 78485 m/sec, 196459871 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 600 secs. Pages in use: 291
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 561/889 294/2000 FireWire-PT-19-LTLCardinality-04 41982405 m, 74575 m/sec, 198306370 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 605 secs. Pages in use: 294
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 566/889 296/2000 FireWire-PT-19-LTLCardinality-04 42367872 m, 77093 m/sec, 200061044 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 610 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 571/889 299/2000 FireWire-PT-19-LTLCardinality-04 42684836 m, 63392 m/sec, 201952597 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 615 secs. Pages in use: 299
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 576/889 301/2000 FireWire-PT-19-LTLCardinality-04 43007084 m, 64449 m/sec, 203756262 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 620 secs. Pages in use: 301
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 581/889 303/2000 FireWire-PT-19-LTLCardinality-04 43344220 m, 67427 m/sec, 205556031 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 625 secs. Pages in use: 303
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 586/889 305/2000 FireWire-PT-19-LTLCardinality-04 43658488 m, 62853 m/sec, 207426613 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 630 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 591/889 308/2000 FireWire-PT-19-LTLCardinality-04 43979563 m, 64215 m/sec, 209190338 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 635 secs. Pages in use: 308
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 596/889 310/2000 FireWire-PT-19-LTLCardinality-04 44307195 m, 65526 m/sec, 210980498 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 640 secs. Pages in use: 310
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 601/889 312/2000 FireWire-PT-19-LTLCardinality-04 44610822 m, 60725 m/sec, 212823680 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 645 secs. Pages in use: 312
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 606/889 314/2000 FireWire-PT-19-LTLCardinality-04 44933663 m, 64568 m/sec, 214533042 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 650 secs. Pages in use: 314
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 611/889 317/2000 FireWire-PT-19-LTLCardinality-04 45301309 m, 73529 m/sec, 216310937 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 655 secs. Pages in use: 317
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 616/889 319/2000 FireWire-PT-19-LTLCardinality-04 45665087 m, 72755 m/sec, 218088730 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 660 secs. Pages in use: 319
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 621/889 322/2000 FireWire-PT-19-LTLCardinality-04 46019008 m, 70784 m/sec, 219793969 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 665 secs. Pages in use: 322
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 626/889 324/2000 FireWire-PT-19-LTLCardinality-04 46289845 m, 54167 m/sec, 221655279 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 670 secs. Pages in use: 324
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 631/889 326/2000 FireWire-PT-19-LTLCardinality-04 46549173 m, 51865 m/sec, 223478578 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 675 secs. Pages in use: 326
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 636/889 327/2000 FireWire-PT-19-LTLCardinality-04 46824206 m, 55006 m/sec, 225138427 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 680 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 641/889 330/2000 FireWire-PT-19-LTLCardinality-04 47142560 m, 63670 m/sec, 226979013 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 685 secs. Pages in use: 330
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 646/889 332/2000 FireWire-PT-19-LTLCardinality-04 47444133 m, 60314 m/sec, 228766425 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 690 secs. Pages in use: 332
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 651/889 334/2000 FireWire-PT-19-LTLCardinality-04 47760838 m, 63341 m/sec, 230405656 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 695 secs. Pages in use: 334
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 656/889 336/2000 FireWire-PT-19-LTLCardinality-04 48076564 m, 63145 m/sec, 232220679 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 700 secs. Pages in use: 336
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 661/889 338/2000 FireWire-PT-19-LTLCardinality-04 48373213 m, 59329 m/sec, 234005212 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 705 secs. Pages in use: 338
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 666/889 340/2000 FireWire-PT-19-LTLCardinality-04 48687621 m, 62881 m/sec, 235644983 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 710 secs. Pages in use: 340
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 671/889 342/2000 FireWire-PT-19-LTLCardinality-04 48960193 m, 54514 m/sec, 237489349 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 715 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 676/889 344/2000 FireWire-PT-19-LTLCardinality-04 49218315 m, 51624 m/sec, 239300134 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 720 secs. Pages in use: 344
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 681/889 346/2000 FireWire-PT-19-LTLCardinality-04 49487564 m, 53849 m/sec, 241001720 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 725 secs. Pages in use: 346
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 686/889 348/2000 FireWire-PT-19-LTLCardinality-04 49799424 m, 62372 m/sec, 242779438 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 730 secs. Pages in use: 348
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 691/889 350/2000 FireWire-PT-19-LTLCardinality-04 50116102 m, 63335 m/sec, 244654267 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 735 secs. Pages in use: 350
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 696/889 353/2000 FireWire-PT-19-LTLCardinality-04 50437141 m, 64207 m/sec, 246400237 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 740 secs. Pages in use: 353
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 701/889 355/2000 FireWire-PT-19-LTLCardinality-04 50763567 m, 65285 m/sec, 248184238 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 745 secs. Pages in use: 355
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 706/889 357/2000 FireWire-PT-19-LTLCardinality-04 51065550 m, 60396 m/sec, 250016611 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 750 secs. Pages in use: 357
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 711/889 359/2000 FireWire-PT-19-LTLCardinality-04 51385474 m, 63984 m/sec, 251711274 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 755 secs. Pages in use: 359
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 716/889 363/2000 FireWire-PT-19-LTLCardinality-04 51849894 m, 92884 m/sec, 253529218 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 760 secs. Pages in use: 363
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 721/889 366/2000 FireWire-PT-19-LTLCardinality-04 52320237 m, 94068 m/sec, 255138243 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 765 secs. Pages in use: 366
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 726/889 369/2000 FireWire-PT-19-LTLCardinality-04 52726210 m, 81194 m/sec, 256561267 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 770 secs. Pages in use: 369
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 731/889 371/2000 FireWire-PT-19-LTLCardinality-04 53096315 m, 74021 m/sec, 258011385 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 775 secs. Pages in use: 371
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 736/889 374/2000 FireWire-PT-19-LTLCardinality-04 53461995 m, 73136 m/sec, 259483529 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 780 secs. Pages in use: 374
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 741/889 376/2000 FireWire-PT-19-LTLCardinality-04 53827140 m, 73029 m/sec, 260905658 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 785 secs. Pages in use: 376
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 746/889 380/2000 FireWire-PT-19-LTLCardinality-04 54269951 m, 88562 m/sec, 262337680 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 790 secs. Pages in use: 380
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 751/889 382/2000 FireWire-PT-19-LTLCardinality-04 54625725 m, 71154 m/sec, 263721745 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 795 secs. Pages in use: 382
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 756/889 384/2000 FireWire-PT-19-LTLCardinality-04 54921224 m, 59099 m/sec, 265206192 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 800 secs. Pages in use: 384
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 761/889 387/2000 FireWire-PT-19-LTLCardinality-04 55279711 m, 71697 m/sec, 266622241 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 805 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 766/889 389/2000 FireWire-PT-19-LTLCardinality-04 55638790 m, 71815 m/sec, 268020478 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 810 secs. Pages in use: 389
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 771/889 392/2000 FireWire-PT-19-LTLCardinality-04 55988161 m, 69874 m/sec, 269457719 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 815 secs. Pages in use: 392
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 776/889 394/2000 FireWire-PT-19-LTLCardinality-04 56270659 m, 56499 m/sec, 270873564 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 820 secs. Pages in use: 394
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 781/889 396/2000 FireWire-PT-19-LTLCardinality-04 56684814 m, 82831 m/sec, 272429070 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 825 secs. Pages in use: 396
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 786/889 400/2000 FireWire-PT-19-LTLCardinality-04 57128414 m, 88720 m/sec, 274031172 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 830 secs. Pages in use: 400
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 791/889 403/2000 FireWire-PT-19-LTLCardinality-04 57571334 m, 88584 m/sec, 275634613 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 835 secs. Pages in use: 403
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 796/889 406/2000 FireWire-PT-19-LTLCardinality-04 57995648 m, 84862 m/sec, 277252007 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 840 secs. Pages in use: 406
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 801/889 408/2000 FireWire-PT-19-LTLCardinality-04 58313114 m, 63493 m/sec, 278795022 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 845 secs. Pages in use: 408
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 806/889 410/2000 FireWire-PT-19-LTLCardinality-04 58690595 m, 75496 m/sec, 280379302 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 850 secs. Pages in use: 410
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 811/889 413/2000 FireWire-PT-19-LTLCardinality-04 59021491 m, 66179 m/sec, 281951508 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 855 secs. Pages in use: 413
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 816/889 415/2000 FireWire-PT-19-LTLCardinality-04 59366720 m, 69045 m/sec, 283501926 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 860 secs. Pages in use: 415
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 821/889 418/2000 FireWire-PT-19-LTLCardinality-04 59734834 m, 73622 m/sec, 285156599 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 865 secs. Pages in use: 418
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 826/889 420/2000 FireWire-PT-19-LTLCardinality-04 60042288 m, 61490 m/sec, 286729510 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 870 secs. Pages in use: 420
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 831/889 422/2000 FireWire-PT-19-LTLCardinality-04 60295184 m, 50579 m/sec, 288252745 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 875 secs. Pages in use: 422
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 836/889 424/2000 FireWire-PT-19-LTLCardinality-04 60654668 m, 71896 m/sec, 289820801 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 880 secs. Pages in use: 424
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 841/889 427/2000 FireWire-PT-19-LTLCardinality-04 60987925 m, 66651 m/sec, 291394180 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 885 secs. Pages in use: 427
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 846/889 429/2000 FireWire-PT-19-LTLCardinality-04 61328911 m, 68197 m/sec, 292935414 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 890 secs. Pages in use: 429
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 851/889 431/2000 FireWire-PT-19-LTLCardinality-04 61694364 m, 73090 m/sec, 294577968 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 895 secs. Pages in use: 431
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 856/889 434/2000 FireWire-PT-19-LTLCardinality-04 62001121 m, 61351 m/sec, 296150829 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 900 secs. Pages in use: 434
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 861/889 435/2000 FireWire-PT-19-LTLCardinality-04 62254822 m, 50740 m/sec, 297671677 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 905 secs. Pages in use: 435
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 866/889 438/2000 FireWire-PT-19-LTLCardinality-04 62703313 m, 89698 m/sec, 299265411 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 910 secs. Pages in use: 438
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 871/889 441/2000 FireWire-PT-19-LTLCardinality-04 63131239 m, 85585 m/sec, 300802227 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 915 secs. Pages in use: 441
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 876/889 445/2000 FireWire-PT-19-LTLCardinality-04 63592193 m, 92190 m/sec, 302425590 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 920 secs. Pages in use: 445
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 881/889 447/2000 FireWire-PT-19-LTLCardinality-04 63972011 m, 75963 m/sec, 304016926 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 925 secs. Pages in use: 447
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 886/889 450/2000 FireWire-PT-19-LTLCardinality-04 64297231 m, 65044 m/sec, 305530502 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 930 secs. Pages in use: 450
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 17 (type EXCL) for FireWire-PT-19-LTLCardinality-04 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 935 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 14 (type EXCL) for 13 FireWire-PT-19-LTLCardinality-03
[[35mlola[0m][I] time limit : 888 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 17 (type EXCL) for 16 FireWire-PT-19-LTLCardinality-04
[[35mlola[0m][I] time limit : 2665 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 14 (type EXCL) for FireWire-PT-19-LTLCardinality-03
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 91
[[35mlola[0m][I] fired transitions : 91
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 5/888 5/5 FireWire-PT-19-LTLCardinality-04 648260 m, -12729794 m/sec, 2292643 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 940 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 17 (type EXCL) for FireWire-PT-19-LTLCardinality-04 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 945 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 32 (type EXCL) for 31 FireWire-PT-19-LTLCardinality-09
[[35mlola[0m][I] time limit : 1327 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 32 (type EXCL) for FireWire-PT-19-LTLCardinality-09
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 20 (type EXCL) for 19 FireWire-PT-19-LTLCardinality-05
[[35mlola[0m][I] time limit : 2655 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 20 (type EXCL) for FireWire-PT-19-LTLCardinality-05
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 950 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 955 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 960 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 965 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 970 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 975 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 980 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 985 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 990 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 995 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1000 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1005 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1010 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1015 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1020 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1025 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1030 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1035 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1040 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1045 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1050 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1055 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1060 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1065 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1070 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1075 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1080 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1085 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1090 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1095 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1100 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1105 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1110 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1115 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1120 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1125 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1130 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1135 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1140 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1145 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1150 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1155 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1160 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1165 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1170 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1175 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1180 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1185 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1190 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1195 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1200 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1205 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1210 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1215 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1220 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1225 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1230 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1235 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1240 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1245 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1250 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1255 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1260 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1265 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1270 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1275 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1280 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1285 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1290 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1295 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1300 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1305 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1310 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1315 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1320 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1325 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1330 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1335 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1340 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1345 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1350 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1355 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1360 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1365 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1370 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1375 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1380 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1385 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1390 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1395 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1400 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1405 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1410 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1415 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1420 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1425 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1430 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1435 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1440 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1445 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1450 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1455 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1460 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1465 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1470 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1475 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1480 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1485 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1490 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1495 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1500 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1505 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1510 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1515 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1520 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1525 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1530 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1535 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1540 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1545 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1550 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1555 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1560 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1565 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1570 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1575 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1580 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1585 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1590 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1595 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1600 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1605 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1610 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1615 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1620 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1625 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1630 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1635 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1640 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1645 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1650 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1655 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1660 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1665 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1670 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1675 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1680 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1685 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1690 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1695 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1700 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1705 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1710 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1715 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1720 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1725 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1730 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1735 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1740 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1745 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1750 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1755 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1760 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1765 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1770 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1775 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1780 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1785 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1790 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1795 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1800 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1805 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1810 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1815 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1820 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1826 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1831 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1836 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1841 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1846 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1851 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1856 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1861 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1866 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1871 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1876 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1881 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1886 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1891 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1896 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1901 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1906 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1911 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1916 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1921 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1926 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1931 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1936 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1941 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1946 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1951 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1956 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1961 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1966 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1971 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1976 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1981 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1986 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1991 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1996 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2001 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2006 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2011 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2016 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2021 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2026 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2031 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2036 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2041 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2046 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2051 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2056 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2061 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2066 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-09: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-19-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-19-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-19-LTLCardinality-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2071 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
========== file over 1MB has been truncated ======
retrieve it from the run archives if needed
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="FireWire-PT-19"
export BK_EXAMINATION="LTLCardinality"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is FireWire-PT-19, examination is LTLCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r551-tall-171734899900315"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/FireWire-PT-19.tgz
mv FireWire-PT-19 execution
cd execution
if [ "LTLCardinality" = "ReachabilityDeadlock" ] || [ "LTLCardinality" = "UpperBounds" ] || [ "LTLCardinality" = "QuasiLiveness" ] || [ "LTLCardinality" = "StableMarking" ] || [ "LTLCardinality" = "Liveness" ] || [ "LTLCardinality" = "OneSafe" ] || [ "LTLCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLCardinality" = "ReachabilityDeadlock" ] || [ "LTLCardinality" = "QuasiLiveness" ] || [ "LTLCardinality" = "StableMarking" ] || [ "LTLCardinality" = "Liveness" ] || [ "LTLCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;