Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r551-tall-171734899800290.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is FireWire-PT-16, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r551-tall-171734899800290
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 556K
-rw-r--r-- 1 mcc users 8.1K Jun 2 17:16 CTLCardinality.txt
-rw-r--r-- 1 mcc users 94K Jun 2 17:16 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.6K Jun 2 17:16 CTLFireability.txt
-rw-r--r-- 1 mcc users 37K Jun 2 17:16 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.3K Jun 2 17:12 LTLCardinality.txt
-rw-r--r-- 1 mcc users 23K Jun 2 17:12 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Jun 2 17:12 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Jun 2 17:12 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 Jun 2 16:33 NewModel
-rw-r--r-- 1 mcc users 9.3K Jun 2 17:16 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 99K Jun 2 17:16 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 12K Jun 2 17:16 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 113K Jun 2 17:16 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Jun 2 17:12 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Jun 2 17:12 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Jun 2 16:33 equiv_col
-rw-r--r-- 1 mcc users 3 Jun 2 16:33 instance
-rw-r--r-- 1 mcc users 6 Jun 2 16:33 iscolored
-rw-r--r-- 1 mcc users 84K Jun 2 16:33 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME FireWire-PT-16-CTLFireability-2024-00
FORMULA_NAME FireWire-PT-16-CTLFireability-2024-01
FORMULA_NAME FireWire-PT-16-CTLFireability-2024-02
FORMULA_NAME FireWire-PT-16-CTLFireability-2024-03
FORMULA_NAME FireWire-PT-16-CTLFireability-2024-04
FORMULA_NAME FireWire-PT-16-CTLFireability-2024-05
FORMULA_NAME FireWire-PT-16-CTLFireability-2024-06
FORMULA_NAME FireWire-PT-16-CTLFireability-2024-07
FORMULA_NAME FireWire-PT-16-CTLFireability-2024-08
FORMULA_NAME FireWire-PT-16-CTLFireability-2024-09
FORMULA_NAME FireWire-PT-16-CTLFireability-2024-10
FORMULA_NAME FireWire-PT-16-CTLFireability-2024-11
FORMULA_NAME FireWire-PT-16-CTLFireability-2024-12
FORMULA_NAME FireWire-PT-16-CTLFireability-2024-13
FORMULA_NAME FireWire-PT-16-CTLFireability-2024-14
FORMULA_NAME FireWire-PT-16-CTLFireability-2024-15

=== Now, execution of the tool begins

BK_START 1717422817255

starting LoLA
BK_EXAMINATION: CTLFireability
BK_TIME_CONFINEMENT: 3600
BK_MEMORY_CONFINEMENT: 16384
BK_BIN_PATH: /home/mcc/BenchKit/bin/
current directory: /home/mcc/execution
FORMULA FireWire-PT-16-CTLFireability-2024-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-16-CTLFireability-2024-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-16-CTLFireability-2024-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-16-CTLFireability-2024-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-16-CTLFireability-2024-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-16-CTLFireability-2024-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-16-CTLFireability-2024-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-16-CTLFireability-2024-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-16-CTLFireability-2024-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-16-CTLFireability-2024-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-16-CTLFireability-2024-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-16-CTLFireability-2024-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-16-CTLFireability-2024-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-16-CTLFireability-2024-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-16-CTLFireability-2024-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-16-CTLFireability-2024-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[lola] FINAL RESULTS
[lola]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola] FireWire-PT-16-CTLFireability-2024-00: CTL false CTL model checker
[lola] FireWire-PT-16-CTLFireability-2024-01: DISJ false DISJ
[lola] FireWire-PT-16-CTLFireability-2024-02: CTL true CTL model checker
[lola] FireWire-PT-16-CTLFireability-2024-03: CTL false CTL model checker
[lola] FireWire-PT-16-CTLFireability-2024-04: CTL false CTL model checker
[lola] FireWire-PT-16-CTLFireability-2024-05: INITIAL false preprocessing
[lola] FireWire-PT-16-CTLFireability-2024-06: CTL false CTL model checker
[lola] FireWire-PT-16-CTLFireability-2024-07: CTL true CTL model checker
[lola] FireWire-PT-16-CTLFireability-2024-08: CTL true CTL model checker
[lola] FireWire-PT-16-CTLFireability-2024-09: CONJ true CONJ
[lola] FireWire-PT-16-CTLFireability-2024-10: CTL false CTL model checker
[lola] FireWire-PT-16-CTLFireability-2024-11: CTL false CTL model checker
[lola] FireWire-PT-16-CTLFireability-2024-12: CTL true CTL model checker
[lola] FireWire-PT-16-CTLFireability-2024-13: CTL false CTL model checker
[lola] FireWire-PT-16-CTLFireability-2024-14: CTL true CTL model checker
[lola] FireWire-PT-16-CTLFireability-2024-15: EF true state space
[lola]
[lola] Time elapsed: 97 secs. Pages in use: 22

BK_STOP 1717422915046

--------------------
content from stderr:

[lola][I] LoLA will run for 3600 seconds at most (--timelimit)
[lola][W] unknown unit in memory specification: using default
[lola][I] MEM LIMIT 5
[lola][I] NET
[lola][I] reading net from model.pnml
[lola][I] input: PNML file (--pnmlnet)
[lola][I] reading pnml
[lola][I] PNML file contains place/transition net
[lola][I] closed net file model.pnml
[lola][I] finished parsing
[lola][I] Reading formula.
[lola][I] Using XML format (--xmlformula)
[lola][I] reading XML formula
[lola][I] reading formula from CTLFireability.xml
[lola][I] Rule S: 0 transitions removed,0 places removed
[lola][I] LAUNCH task # 20 (type CNST) for 19 FireWire-PT-16-CTLFireability-2024-05
[lola][I] time limit : 0 sec
[lola][I] memory limit: 0 pages
[lola][I] FINISHED task # 20 (type CNST) for FireWire-PT-16-CTLFireability-2024-05
[lola][I] result : false
[lola][I] LAUNCH task # 14 (type EXCL) for 13 FireWire-PT-16-CTLFireability-2024-03
[lola][I] time limit : 171 sec
[lola][I] memory limit: 2000 pages
[lola][I] LAUNCH task # 59 (type FNDP) for 31 FireWire-PT-16-CTLFireability-2024-09
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 60 (type EQUN) for 31 FireWire-PT-16-CTLFireability-2024-09
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 56 (type FNDP) for 53 FireWire-PT-16-CTLFireability-2024-15
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 60 (type EQUN) for FireWire-PT-16-CTLFireability-2024-09
[lola][I] result : unknown
[lola][I] LAUNCH task # 57 (type EQUN) for 53 FireWire-PT-16-CTLFireability-2024-15
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 57 (type EQUN) for FireWire-PT-16-CTLFireability-2024-15
[lola][I] result : unknown
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] FireWire-PT-16-CTLFireability-2024-05: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] FireWire-PT-16-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-01: DISJ 0 2 0 0 2 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-09: CONJ 0 2 1 0 3 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-15: EF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 14 CTL EXCL 5/211 5/2000 FireWire-PT-16-CTLFireability-2024-03 960166 m, 192033 m/sec, 3753321 t fired, .
[lola][.] 56 EF FNDP 5/3599 0/5 FireWire-PT-16-CTLFireability-2024-15 161677 attempts, .
[lola][.] 59 EF FNDP 5/3599 0/5 FireWire-PT-16-CTLFireability-2024-09 160482 attempts, .
[lola][.]
[lola][.] Time elapsed: 6 secs. Pages in use: 5
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] FireWire-PT-16-CTLFireability-2024-05: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] FireWire-PT-16-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-01: DISJ 0 2 0 0 2 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-09: CONJ 0 2 1 0 3 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-15: EF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 14 CTL EXCL 10/211 9/2000 FireWire-PT-16-CTLFireability-2024-03 1805411 m, 169049 m/sec, 7629695 t fired, .
[lola][.] 56 EF FNDP 10/3599 0/5 FireWire-PT-16-CTLFireability-2024-15 334237 attempts, .
[lola][.] 59 EF FNDP 10/3599 0/5 FireWire-PT-16-CTLFireability-2024-09 332733 attempts, .
[lola][.]
[lola][.] Time elapsed: 11 secs. Pages in use: 9
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] FireWire-PT-16-CTLFireability-2024-05: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] FireWire-PT-16-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-01: DISJ 0 2 0 0 2 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-09: CONJ 0 2 1 0 3 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-15: EF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 14 CTL EXCL 15/211 13/2000 FireWire-PT-16-CTLFireability-2024-03 2662992 m, 171516 m/sec, 11438050 t fired, .
[lola][.] 56 EF FNDP 15/3599 0/5 FireWire-PT-16-CTLFireability-2024-15 506476 attempts, .
[lola][.] 59 EF FNDP 15/3599 0/5 FireWire-PT-16-CTLFireability-2024-09 504302 attempts, .
[lola][.]
[lola][.] Time elapsed: 16 secs. Pages in use: 13
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] FireWire-PT-16-CTLFireability-2024-05: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] FireWire-PT-16-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-01: DISJ 0 2 0 0 2 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-09: CONJ 0 2 1 0 3 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-15: EF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 14 CTL EXCL 20/211 17/2000 FireWire-PT-16-CTLFireability-2024-03 3441936 m, 155788 m/sec, 15178200 t fired, .
[lola][.] 56 EF FNDP 20/3599 0/5 FireWire-PT-16-CTLFireability-2024-15 679258 attempts, .
[lola][.] 59 EF FNDP 20/3599 0/5 FireWire-PT-16-CTLFireability-2024-09 676513 attempts, .
[lola][.]
[lola][.] Time elapsed: 21 secs. Pages in use: 17
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] FireWire-PT-16-CTLFireability-2024-05: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] FireWire-PT-16-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-01: DISJ 0 2 0 0 2 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-09: CONJ 0 2 1 0 3 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-15: EF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 14 CTL EXCL 25/211 20/2000 FireWire-PT-16-CTLFireability-2024-03 4147510 m, 141114 m/sec, 18873998 t fired, .
[lola][.] 56 EF FNDP 25/3599 0/5 FireWire-PT-16-CTLFireability-2024-15 852590 attempts, .
[lola][.] 59 EF FNDP 25/3599 0/5 FireWire-PT-16-CTLFireability-2024-09 848638 attempts, .
[lola][.]
[lola][.] Time elapsed: 26 secs. Pages in use: 20
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I] FINISHED task # 14 (type EXCL) for FireWire-PT-16-CTLFireability-2024-03
[lola][I] result : false
[lola][I] markings : 4618610
[lola][I] fired transitions : 21159944
[lola][I] time used : 28
[lola][I] memory pages used : 22
[lola][I] LAUNCH task # 51 (type EXCL) for 50 FireWire-PT-16-CTLFireability-2024-14
[lola][I] time limit : 223 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 51 (type EXCL) for FireWire-PT-16-CTLFireability-2024-14
[lola][I] result : true
[lola][I] markings : 360
[lola][I] fired transitions : 407
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 48 (type EXCL) for 47 FireWire-PT-16-CTLFireability-2024-13
[lola][I] time limit : 238 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 48 (type EXCL) for FireWire-PT-16-CTLFireability-2024-13
[lola][I] result : false
[lola][I] markings : 27
[lola][I] fired transitions : 67
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 45 (type EXCL) for 44 FireWire-PT-16-CTLFireability-2024-12
[lola][I] time limit : 255 sec
[lola][I] memory limit: 2000 pages
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] FireWire-PT-16-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] FireWire-PT-16-CTLFireability-2024-05: INITIAL false preprocessing
[lola][.] FireWire-PT-16-CTLFireability-2024-13: CTL false CTL model checker
[lola][.] FireWire-PT-16-CTLFireability-2024-14: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] FireWire-PT-16-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-01: DISJ 0 2 0 0 2 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-09: CONJ 0 2 1 0 3 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-15: EF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 45 CTL EXCL 2/255 3/2000 FireWire-PT-16-CTLFireability-2024-12 529915 m, 105983 m/sec, 1532569 t fired, .
[lola][.] 56 EF FNDP 30/3599 0/5 FireWire-PT-16-CTLFireability-2024-15 1025657 attempts, .
[lola][.] 59 EF FNDP 30/3599 0/5 FireWire-PT-16-CTLFireability-2024-09 1020432 attempts, .
[lola][.]
[lola][.] Time elapsed: 31 secs. Pages in use: 22
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] FireWire-PT-16-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] FireWire-PT-16-CTLFireability-2024-05: INITIAL false preprocessing
[lola][.] FireWire-PT-16-CTLFireability-2024-13: CTL false CTL model checker
[lola][.] FireWire-PT-16-CTLFireability-2024-14: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] FireWire-PT-16-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-01: DISJ 0 2 0 0 2 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-09: CONJ 0 2 1 0 3 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-15: EF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 45 CTL EXCL 7/255 8/2000 FireWire-PT-16-CTLFireability-2024-12 1661335 m, 226284 m/sec, 5418650 t fired, .
[lola][.] 56 EF FNDP 35/3599 0/5 FireWire-PT-16-CTLFireability-2024-15 1198441 attempts, .
[lola][.] 59 EF FNDP 35/3599 0/5 FireWire-PT-16-CTLFireability-2024-09 1192558 attempts, .
[lola][.]
[lola][.] Time elapsed: 36 secs. Pages in use: 22
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] FireWire-PT-16-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] FireWire-PT-16-CTLFireability-2024-05: INITIAL false preprocessing
[lola][.] FireWire-PT-16-CTLFireability-2024-13: CTL false CTL model checker
[lola][.] FireWire-PT-16-CTLFireability-2024-14: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] FireWire-PT-16-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-01: DISJ 0 2 0 0 2 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-09: CONJ 0 2 1 0 3 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-15: EF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 45 CTL EXCL 12/255 13/2000 FireWire-PT-16-CTLFireability-2024-12 2647192 m, 197171 m/sec, 9162501 t fired, .
[lola][.] 56 EF FNDP 40/3599 0/5 FireWire-PT-16-CTLFireability-2024-15 1371152 attempts, .
[lola][.] 59 EF FNDP 40/3599 0/5 FireWire-PT-16-CTLFireability-2024-09 1364811 attempts, .
[lola][.]
[lola][.] Time elapsed: 41 secs. Pages in use: 22
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] FireWire-PT-16-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] FireWire-PT-16-CTLFireability-2024-05: INITIAL false preprocessing
[lola][.] FireWire-PT-16-CTLFireability-2024-13: CTL false CTL model checker
[lola][.] FireWire-PT-16-CTLFireability-2024-14: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] FireWire-PT-16-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-01: DISJ 0 2 0 0 2 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-09: CONJ 0 2 1 0 3 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-15: EF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 45 CTL EXCL 17/255 17/2000 FireWire-PT-16-CTLFireability-2024-12 3490885 m, 168738 m/sec, 12909049 t fired, .
[lola][.] 56 EF FNDP 45/3599 0/5 FireWire-PT-16-CTLFireability-2024-15 1544248 attempts, .
[lola][.] 59 EF FNDP 45/3599 0/5 FireWire-PT-16-CTLFireability-2024-09 1537552 attempts, .
[lola][.]
[lola][.] Time elapsed: 46 secs. Pages in use: 22
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I] FINISHED task # 45 (type EXCL) for FireWire-PT-16-CTLFireability-2024-12
[lola][I] result : true
[lola][I] markings : 4108103
[lola][I] fired transitions : 15460137
[lola][I] time used : 20
[lola][I] memory pages used : 20
[lola][I] LAUNCH task # 42 (type EXCL) for 41 FireWire-PT-16-CTLFireability-2024-11
[lola][I] time limit : 273 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 42 (type EXCL) for FireWire-PT-16-CTLFireability-2024-11
[lola][I] result : false
[lola][I] markings : 1100
[lola][I] fired transitions : 2845
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 39 (type EXCL) for 38 FireWire-PT-16-CTLFireability-2024-10
[lola][I] time limit : 295 sec
[lola][I] memory limit: 2000 pages
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] FireWire-PT-16-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] FireWire-PT-16-CTLFireability-2024-05: INITIAL false preprocessing
[lola][.] FireWire-PT-16-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] FireWire-PT-16-CTLFireability-2024-12: CTL true CTL model checker
[lola][.] FireWire-PT-16-CTLFireability-2024-13: CTL false CTL model checker
[lola][.] FireWire-PT-16-CTLFireability-2024-14: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] FireWire-PT-16-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-01: DISJ 0 2 0 0 2 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-09: CONJ 0 2 1 0 3 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-15: EF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 39 CTL EXCL 2/295 2/2000 FireWire-PT-16-CTLFireability-2024-10 360672 m, 72134 m/sec, 1430235 t fired, .
[lola][.] 56 EF FNDP 50/3599 0/5 FireWire-PT-16-CTLFireability-2024-15 1717192 attempts, .
[lola][.] 59 EF FNDP 50/3599 0/5 FireWire-PT-16-CTLFireability-2024-09 1709582 attempts, .
[lola][.]
[lola][.] Time elapsed: 51 secs. Pages in use: 22
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] FireWire-PT-16-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] FireWire-PT-16-CTLFireability-2024-05: INITIAL false preprocessing
[lola][.] FireWire-PT-16-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] FireWire-PT-16-CTLFireability-2024-12: CTL true CTL model checker
[lola][.] FireWire-PT-16-CTLFireability-2024-13: CTL false CTL model checker
[lola][.] FireWire-PT-16-CTLFireability-2024-14: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] FireWire-PT-16-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-01: DISJ 0 2 0 0 2 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-09: CONJ 0 2 1 0 3 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-15: EF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 39 CTL EXCL 7/295 7/2000 FireWire-PT-16-CTLFireability-2024-10 1314499 m, 190765 m/sec, 5641211 t fired, .
[lola][.] 56 EF FNDP 55/3599 0/5 FireWire-PT-16-CTLFireability-2024-15 1889721 attempts, .
[lola][.] 59 EF FNDP 55/3599 0/5 FireWire-PT-16-CTLFireability-2024-09 1882001 attempts, .
[lola][.]
[lola][.] Time elapsed: 56 secs. Pages in use: 22
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I] FINISHED task # 39 (type EXCL) for FireWire-PT-16-CTLFireability-2024-10
[lola][I] result : false
[lola][I] markings : 1797438
[lola][I] fired transitions : 7617876
[lola][I] time used : 9
[lola][I] memory pages used : 9
[lola][I] LAUNCH task # 36 (type EXCL) for 31 FireWire-PT-16-CTLFireability-2024-09
[lola][I] time limit : 322 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 36 (type EXCL) for FireWire-PT-16-CTLFireability-2024-09
[lola][I] result : true
[lola][I] markings : 7
[lola][I] fired transitions : 8
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 29 (type EXCL) for 28 FireWire-PT-16-CTLFireability-2024-08
[lola][I] time limit : 354 sec
[lola][I] memory limit: 2000 pages
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] FireWire-PT-16-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] FireWire-PT-16-CTLFireability-2024-05: INITIAL false preprocessing
[lola][.] FireWire-PT-16-CTLFireability-2024-10: CTL false CTL model checker
[lola][.] FireWire-PT-16-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] FireWire-PT-16-CTLFireability-2024-12: CTL true CTL model checker
[lola][.] FireWire-PT-16-CTLFireability-2024-13: CTL false CTL model checker
[lola][.] FireWire-PT-16-CTLFireability-2024-14: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] FireWire-PT-16-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-01: DISJ 0 2 0 0 2 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-09: CONJ 0 1 1 0 4 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-15: EF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 29 CTL EXCL 3/354 3/2000 FireWire-PT-16-CTLFireability-2024-08 561619 m, 112323 m/sec, 2197456 t fired, .
[lola][.] 56 EF FNDP 60/3599 0/5 FireWire-PT-16-CTLFireability-2024-15 2062852 attempts, .
[lola][.] 59 EF FNDP 60/3599 0/5 FireWire-PT-16-CTLFireability-2024-09 2054443 attempts, .
[lola][.]
[lola][.] Time elapsed: 61 secs. Pages in use: 22
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] FireWire-PT-16-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] FireWire-PT-16-CTLFireability-2024-05: INITIAL false preprocessing
[lola][.] FireWire-PT-16-CTLFireability-2024-10: CTL false CTL model checker
[lola][.] FireWire-PT-16-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] FireWire-PT-16-CTLFireability-2024-12: CTL true CTL model checker
[lola][.] FireWire-PT-16-CTLFireability-2024-13: CTL false CTL model checker
[lola][.] FireWire-PT-16-CTLFireability-2024-14: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] FireWire-PT-16-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-01: DISJ 0 2 0 0 2 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-09: CONJ 0 1 1 0 4 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-15: EF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 29 CTL EXCL 8/354 7/2000 FireWire-PT-16-CTLFireability-2024-08 1443265 m, 176329 m/sec, 6199812 t fired, .
[lola][.] 56 EF FNDP 65/3599 0/5 FireWire-PT-16-CTLFireability-2024-15 2236077 attempts, .
[lola][.] 59 EF FNDP 65/3599 0/5 FireWire-PT-16-CTLFireability-2024-09 2226299 attempts, .
[lola][.]
[lola][.] Time elapsed: 66 secs. Pages in use: 22
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I] FINISHED task # 29 (type EXCL) for FireWire-PT-16-CTLFireability-2024-08
[lola][I] result : true
[lola][I] markings : 2036663
[lola][I] fired transitions : 8819442
[lola][I] time used : 11
[lola][I] memory pages used : 10
[lola][I] LAUNCH task # 26 (type EXCL) for 25 FireWire-PT-16-CTLFireability-2024-07
[lola][I] time limit : 392 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 26 (type EXCL) for FireWire-PT-16-CTLFireability-2024-07
[lola][I] result : true
[lola][I] markings : 219
[lola][I] fired transitions : 278
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 23 (type EXCL) for 22 FireWire-PT-16-CTLFireability-2024-06
[lola][I] time limit : 441 sec
[lola][I] memory limit: 2000 pages
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] FireWire-PT-16-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] FireWire-PT-16-CTLFireability-2024-05: INITIAL false preprocessing
[lola][.] FireWire-PT-16-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] FireWire-PT-16-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] FireWire-PT-16-CTLFireability-2024-10: CTL false CTL model checker
[lola][.] FireWire-PT-16-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] FireWire-PT-16-CTLFireability-2024-12: CTL true CTL model checker
[lola][.] FireWire-PT-16-CTLFireability-2024-13: CTL false CTL model checker
[lola][.] FireWire-PT-16-CTLFireability-2024-14: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] FireWire-PT-16-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-01: DISJ 0 2 0 0 2 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-09: CONJ 0 1 1 0 4 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-15: EF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 23 CTL EXCL 2/441 2/2000 FireWire-PT-16-CTLFireability-2024-06 353327 m, 70665 m/sec, 1294099 t fired, .
[lola][.] 56 EF FNDP 70/3599 0/5 FireWire-PT-16-CTLFireability-2024-15 2408985 attempts, .
[lola][.] 59 EF FNDP 70/3599 0/5 FireWire-PT-16-CTLFireability-2024-09 2398447 attempts, .
[lola][.]
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[lola][.] FireWire-PT-16-CTLFireability-2024-07: CTL true CTL model checker
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[lola][.] FireWire-PT-16-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-09: CONJ 0 1 1 0 4 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-15: EF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 23 CTL EXCL 7/441 6/2000 FireWire-PT-16-CTLFireability-2024-06 1251449 m, 179624 m/sec, 4956262 t fired, .
[lola][.] 56 EF FNDP 75/3599 0/5 FireWire-PT-16-CTLFireability-2024-15 2581814 attempts, .
[lola][.] 59 EF FNDP 75/3599 0/5 FireWire-PT-16-CTLFireability-2024-09 2570538 attempts, .
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[lola][.] FireWire-PT-16-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-09: CONJ 0 1 1 0 4 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-15: EF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 23 CTL EXCL 12/441 10/2000 FireWire-PT-16-CTLFireability-2024-06 2117076 m, 173125 m/sec, 8611184 t fired, .
[lola][.] 56 EF FNDP 80/3599 0/5 FireWire-PT-16-CTLFireability-2024-15 2754796 attempts, .
[lola][.] 59 EF FNDP 80/3599 0/5 FireWire-PT-16-CTLFireability-2024-09 2742903 attempts, .
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[lola][.] FireWire-PT-16-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-09: CONJ 0 1 1 0 4 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-15: EF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 23 CTL EXCL 17/441 14/2000 FireWire-PT-16-CTLFireability-2024-06 2918671 m, 160319 m/sec, 12203704 t fired, .
[lola][.] 56 EF FNDP 85/3599 0/5 FireWire-PT-16-CTLFireability-2024-15 2927734 attempts, .
[lola][.] 59 EF FNDP 85/3599 0/5 FireWire-PT-16-CTLFireability-2024-09 2914878 attempts, .
[lola][.]
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[lola][.] FireWire-PT-16-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-09: CONJ 0 1 1 0 4 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-15: EF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 23 CTL EXCL 22/441 18/2000 FireWire-PT-16-CTLFireability-2024-06 3652185 m, 146702 m/sec, 15762094 t fired, .
[lola][.] 56 EF FNDP 90/3599 0/5 FireWire-PT-16-CTLFireability-2024-15 3100188 attempts, .
[lola][.] 59 EF FNDP 90/3599 0/5 FireWire-PT-16-CTLFireability-2024-09 3086579 attempts, .
[lola][.]
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[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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[lola][.] FireWire-PT-16-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-09: CONJ 0 1 1 0 4 0 0 0
[lola][.] FireWire-PT-16-CTLFireability-2024-15: EF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 23 CTL EXCL 27/441 21/2000 FireWire-PT-16-CTLFireability-2024-06 4367367 m, 143036 m/sec, 19296970 t fired, .
[lola][.] 56 EF FNDP 95/3599 0/5 FireWire-PT-16-CTLFireability-2024-15 3273397 attempts, .
[lola][.] 59 EF FNDP 95/3599 0/5 FireWire-PT-16-CTLFireability-2024-09 3258770 attempts, .
[lola][.]
[lola][.] Time elapsed: 96 secs. Pages in use: 22
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[lola][I] FINISHED task # 23 (type EXCL) for FireWire-PT-16-CTLFireability-2024-06
[lola][I] result : false
[lola][I] markings : 4618610
[lola][I] fired transitions : 20434556
[lola][I] time used : 28
[lola][I] memory pages used : 22
[lola][I] LAUNCH task # 17 (type EXCL) for 16 FireWire-PT-16-CTLFireability-2024-04
[lola][I] time limit : 500 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 17 (type EXCL) for FireWire-PT-16-CTLFireability-2024-04
[lola][I] result : false
[lola][I] markings : 43539
[lola][I] fired transitions : 165043
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 11 (type EXCL) for 10 FireWire-PT-16-CTLFireability-2024-02
[lola][I] time limit : 583 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 11 (type EXCL) for FireWire-PT-16-CTLFireability-2024-02
[lola][I] result : true
[lola][I] markings : 220
[lola][I] fired transitions : 498
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 8 (type EXCL) for 3 FireWire-PT-16-CTLFireability-2024-01
[lola][I] time limit : 700 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 8 (type EXCL) for FireWire-PT-16-CTLFireability-2024-01
[lola][I] result : false
[lola][I] markings : 959
[lola][I] fired transitions : 1427
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 6 (type EXCL) for 3 FireWire-PT-16-CTLFireability-2024-01
[lola][I] time limit : 875 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 6 (type EXCL) for FireWire-PT-16-CTLFireability-2024-01
[lola][I] result : false
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 1 (type EXCL) for 0 FireWire-PT-16-CTLFireability-2024-00
[lola][I] time limit : 1167 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 1 (type EXCL) for FireWire-PT-16-CTLFireability-2024-00
[lola][I] result : false
[lola][I] markings : 475
[lola][I] fired transitions : 1031
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 61 (type EXCL) for 31 FireWire-PT-16-CTLFireability-2024-09
[lola][I] time limit : 1751 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 61 (type EXCL) for FireWire-PT-16-CTLFireability-2024-09
[lola][I] result : true
[lola][I] markings : 4182
[lola][I] fired transitions : 7324
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][W] CANCELED task # 59 (type FNDP) for FireWire-PT-16-CTLFireability-2024-09 (obsolete)
[lola][I] LAUNCH task # 58 (type EXCL) for 53 FireWire-PT-16-CTLFireability-2024-15
[lola][I] time limit : 3503 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 59 (type FNDP) for FireWire-PT-16-CTLFireability-2024-09
[lola][I] result : unknown
[lola][I] tried executions : 3321668
[lola][I] time used : 96
[lola][I] memory pages used : 0
[lola][I] FINISHED task # 58 (type EXCL) for FireWire-PT-16-CTLFireability-2024-15
[lola][I] result : true
[lola][I] markings : 2502
[lola][I] fired transitions : 4454
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][W] CANCELED task # 56 (type FNDP) for FireWire-PT-16-CTLFireability-2024-15 (obsolete)
[lola][I] Portfolio finished: no open formulas

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="FireWire-PT-16"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is FireWire-PT-16, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r551-tall-171734899800290"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/FireWire-PT-16.tgz
mv FireWire-PT-16 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;