Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r551-tall-171734899800282.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is FireWire-PT-15, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r551-tall-171734899800282
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 492K
-rw-r--r-- 1 mcc users 7.6K Jun 2 17:16 CTLCardinality.txt
-rw-r--r-- 1 mcc users 87K Jun 2 17:16 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.0K Jun 2 17:16 CTLFireability.txt
-rw-r--r-- 1 mcc users 46K Jun 2 17:16 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.5K Jun 2 17:12 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Jun 2 17:12 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Jun 2 17:12 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Jun 2 17:12 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 Jun 2 16:33 NewModel
-rw-r--r-- 1 mcc users 9.1K Jun 2 17:16 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 95K Jun 2 17:16 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 6.9K Jun 2 17:16 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 56K Jun 2 17:16 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Jun 2 17:12 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Jun 2 17:12 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Jun 2 16:33 equiv_col
-rw-r--r-- 1 mcc users 3 Jun 2 16:33 instance
-rw-r--r-- 1 mcc users 6 Jun 2 16:33 iscolored
-rw-r--r-- 1 mcc users 90K Jun 2 16:33 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME FireWire-PT-15-CTLFireability-2024-00
FORMULA_NAME FireWire-PT-15-CTLFireability-2024-01
FORMULA_NAME FireWire-PT-15-CTLFireability-2024-02
FORMULA_NAME FireWire-PT-15-CTLFireability-2024-03
FORMULA_NAME FireWire-PT-15-CTLFireability-2024-04
FORMULA_NAME FireWire-PT-15-CTLFireability-2024-05
FORMULA_NAME FireWire-PT-15-CTLFireability-2024-06
FORMULA_NAME FireWire-PT-15-CTLFireability-2024-07
FORMULA_NAME FireWire-PT-15-CTLFireability-2024-08
FORMULA_NAME FireWire-PT-15-CTLFireability-2024-09
FORMULA_NAME FireWire-PT-15-CTLFireability-2024-10
FORMULA_NAME FireWire-PT-15-CTLFireability-2024-11
FORMULA_NAME FireWire-PT-15-CTLFireability-2024-12
FORMULA_NAME FireWire-PT-15-CTLFireability-2024-13
FORMULA_NAME FireWire-PT-15-CTLFireability-2024-14
FORMULA_NAME FireWire-PT-15-CTLFireability-2024-15

=== Now, execution of the tool begins

BK_START 1717422422115

starting LoLA
BK_EXAMINATION: CTLFireability
BK_TIME_CONFINEMENT: 3600
BK_MEMORY_CONFINEMENT: 16384
BK_BIN_PATH: /home/mcc/BenchKit/bin/
current directory: /home/mcc/execution
FORMULA FireWire-PT-15-CTLFireability-2024-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-15-CTLFireability-2024-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-15-CTLFireability-2024-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-15-CTLFireability-2024-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-15-CTLFireability-2024-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-15-CTLFireability-2024-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-15-CTLFireability-2024-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-15-CTLFireability-2024-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-15-CTLFireability-2024-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-15-CTLFireability-2024-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-15-CTLFireability-2024-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-15-CTLFireability-2024-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-15-CTLFireability-2024-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-15-CTLFireability-2024-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-15-CTLFireability-2024-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-15-CTLFireability-2024-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[lola] FINAL RESULTS
[lola]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola] FireWire-PT-15-CTLFireability-2024-00: DISJ false DISJ
[lola] FireWire-PT-15-CTLFireability-2024-01: DISJ true DISJ
[lola] FireWire-PT-15-CTLFireability-2024-02: CTL true CTL model checker
[lola] FireWire-PT-15-CTLFireability-2024-03: EFEG true state space /EFEG
[lola] FireWire-PT-15-CTLFireability-2024-04: CTL false CTL model checker
[lola] FireWire-PT-15-CTLFireability-2024-05: CTL true CTL model checker
[lola] FireWire-PT-15-CTLFireability-2024-06: CTL true CTL model checker
[lola] FireWire-PT-15-CTLFireability-2024-07: CTL false CTL model checker
[lola] FireWire-PT-15-CTLFireability-2024-08: CTL false CTL model checker
[lola] FireWire-PT-15-CTLFireability-2024-09: CTL false CTL model checker
[lola] FireWire-PT-15-CTLFireability-2024-10: CTL true CTL model checker
[lola] FireWire-PT-15-CTLFireability-2024-11: CTL true CTL model checker
[lola] FireWire-PT-15-CTLFireability-2024-12: CTL true CTL model checker
[lola] FireWire-PT-15-CTLFireability-2024-13: CTL true CTL model checker
[lola] FireWire-PT-15-CTLFireability-2024-14: CTL false CTL model checker
[lola] FireWire-PT-15-CTLFireability-2024-15: CTL false CTL model checker
[lola]
[lola] Time elapsed: 121 secs. Pages in use: 10

BK_STOP 1717422543296

--------------------
content from stderr:

[lola][I] LoLA will run for 3600 seconds at most (--timelimit)
[lola][W] unknown unit in memory specification: using default
[lola][I] MEM LIMIT 5
[lola][I] NET
[lola][I] reading net from model.pnml
[lola][I] input: PNML file (--pnmlnet)
[lola][I] reading pnml
[lola][I] PNML file contains place/transition net
[lola][I] closed net file model.pnml
[lola][I] finished parsing
[lola][I] Reading formula.
[lola][I] Using XML format (--xmlformula)
[lola][I] reading XML formula
[lola][I] reading formula from CTLFireability.xml
[lola][I] Rule S: 0 transitions removed,0 places removed
[lola][I] LAUNCH task # 10 (type EXCL) for 7 FireWire-PT-15-CTLFireability-2024-01
[lola][I] time limit : 138 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 10 (type EXCL) for FireWire-PT-15-CTLFireability-2024-01
[lola][I] result : false
[lola][I] markings : 2
[lola][I] fired transitions : 3
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 74 (type EXCL) for 7 FireWire-PT-15-CTLFireability-2024-01
[lola][I] time limit : 144 sec
[lola][I] memory limit: 2000 pages
[lola][I] LAUNCH task # 72 (type FNDP) for 7 FireWire-PT-15-CTLFireability-2024-01
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 73 (type EQUN) for 7 FireWire-PT-15-CTLFireability-2024-01
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 74 (type EXCL) for FireWire-PT-15-CTLFireability-2024-01
[lola][I] result : true
[lola][I] markings : 516
[lola][I] fired transitions : 577
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][W] CANCELED task # 72 (type FNDP) for FireWire-PT-15-CTLFireability-2024-01 (obsolete)
[lola][W] CANCELED task # 73 (type EQUN) for FireWire-PT-15-CTLFireability-2024-01 (obsolete)
[lola][I] LAUNCH task # 20 (type EXCL) for 7 FireWire-PT-15-CTLFireability-2024-01
[lola][I] time limit : 189 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 73 (type EQUN) for FireWire-PT-15-CTLFireability-2024-01
[lola][I] result : unknown
[lola][I] FINISHED task # 20 (type EXCL) for FireWire-PT-15-CTLFireability-2024-01
[lola][I] result : false
[lola][I] markings : 1
[lola][I] fired transitions : 1
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 58 (type EXCL) for 57 FireWire-PT-15-CTLFireability-2024-11
[lola][I] time limit : 211 sec
[lola][I] memory limit: 2000 pages
[lola][I] LAUNCH task # 80 (type EQUN) for 33 FireWire-PT-15-CTLFireability-2024-03
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 82 (type EQUN) for 33 FireWire-PT-15-CTLFireability-2024-03
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 85 (type EQUN) for 0 FireWire-PT-15-CTLFireability-2024-00
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 85 (type EQUN) for FireWire-PT-15-CTLFireability-2024-00
[lola][I] result : true
[lola][I] FINISHED task # 82 (type EQUN) for FireWire-PT-15-CTLFireability-2024-03
[lola][I] result : unknown
[lola][I] FINISHED task # 80 (type EQUN) for FireWire-PT-15-CTLFireability-2024-03
[lola][I] result : unknown
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] FireWire-PT-15-CTLFireability-2024-00: DISJ 0 2 0 0 3 0 0 0
[lola][.] FireWire-PT-15-CTLFireability-2024-01: DISJ 0 1 0 0 10 0 0 4
[lola][.] FireWire-PT-15-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-15-CTLFireability-2024-03: EFEG 0 1 0 0 3 0 0 0
[lola][.] FireWire-PT-15-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-15-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-15-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-15-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-15-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-15-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-15-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-15-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[lola][.] FireWire-PT-15-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-15-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-15-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-15-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 58 CTL EXCL 5/211 5/2000 FireWire-PT-15-CTLFireability-2024-11 1146753 m, 229350 m/sec, 3465872 t fired, .
[lola][.]
[lola][.] Time elapsed: 5 secs. Pages in use: 5
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I] FINISHED task # 58 (type EXCL) for FireWire-PT-15-CTLFireability-2024-11
[lola][I] result : true
[lola][I] markings : 1811581
[lola][I] fired transitions : 5800675
[lola][I] time used : 8
[lola][I] memory pages used : 8
[lola][I] LAUNCH task # 70 (type EXCL) for 69 FireWire-PT-15-CTLFireability-2024-15
[lola][I] time limit : 224 sec
[lola][I] memory limit: 2000 pages
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] FireWire-PT-15-CTLFireability-2024-11: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] FireWire-PT-15-CTLFireability-2024-00: DISJ 0 2 0 0 3 0 0 0
[lola][.] FireWire-PT-15-CTLFireability-2024-01: DISJ 0 1 0 0 10 0 0 4
[lola][.] FireWire-PT-15-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-15-CTLFireability-2024-03: EFEG 0 1 0 0 3 0 0 0
[lola][.] FireWire-PT-15-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-15-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-15-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-15-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-15-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-15-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-15-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-15-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-15-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-15-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-15-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 70 CTL EXCL 2/224 2/2000 FireWire-PT-15-CTLFireability-2024-15 425883 m, 85176 m/sec, 1614588 t fired, .
[lola][.]
[lola][.] Time elapsed: 10 secs. Pages in use: 8
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] FireWire-PT-15-CTLFireability-2024-11: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] FireWire-PT-15-CTLFireability-2024-00: DISJ 0 2 0 0 3 0 0 0
[lola][.] FireWire-PT-15-CTLFireability-2024-01: DISJ 0 1 0 0 10 0 0 4
[lola][.] FireWire-PT-15-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-15-CTLFireability-2024-03: EFEG 0 1 0 0 3 0 0 0
[lola][.] FireWire-PT-15-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-15-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-15-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-15-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-15-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-15-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-15-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-15-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-15-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-15-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-15-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 70 CTL EXCL 7/224 6/2000 FireWire-PT-15-CTLFireability-2024-15 1406319 m, 196087 m/sec, 5776643 t fired, .
[lola][.]
[lola][.] Time elapsed: 15 secs. Pages in use: 8
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I] FINISHED task # 70 (type EXCL) for FireWire-PT-15-CTLFireability-2024-15
[lola][I] result : false
[lola][I] markings : 1908083
[lola][I] fired transitions : 8159732
[lola][I] time used : 10
[lola][I] memory pages used : 8
[lola][I] LAUNCH task # 67 (type EXCL) for 66 FireWire-PT-15-CTLFireability-2024-14
[lola][I] time limit : 238 sec
[lola][I] memory limit: 2000 pages
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] FireWire-PT-15-CTLFireability-2024-11: CTL true CTL model checker
[lola][.] FireWire-PT-15-CTLFireability-2024-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] FireWire-PT-15-CTLFireability-2024-00: DISJ 0 2 0 0 3 0 0 0
[lola][.] FireWire-PT-15-CTLFireability-2024-01: DISJ 0 1 0 0 10 0 0 4
[lola][.] FireWire-PT-15-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-15-CTLFireability-2024-03: EFEG 0 1 0 0 3 0 0 0
[lola][.] FireWire-PT-15-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-15-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-15-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-15-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-15-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-15-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-15-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-15-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-15-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-15-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 67 CTL EXCL 2/238 2/2000 FireWire-PT-15-CTLFireability-2024-14 269479 m, 53895 m/sec, 1436471 t fired, .
[lola][.]
[lola][.] Time elapsed: 20 secs. Pages in use: 8
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] FireWire-PT-15-CTLFireability-2024-11: CTL true CTL model checker
[lola][.] FireWire-PT-15-CTLFireability-2024-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] FireWire-PT-15-CTLFireability-2024-00: DISJ 0 2 0 0 3 0 0 0
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[lola][.] FireWire-PT-15-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-15-CTLFireability-2024-03: EFEG 0 1 0 0 3 0 0 0
[lola][.] FireWire-PT-15-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
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[lola][.] 67 CTL EXCL 7/238 4/2000 FireWire-PT-15-CTLFireability-2024-14 837870 m, 113678 m/sec, 4816312 t fired, .
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[lola][.] FireWire-PT-15-CTLFireability-2024-03: EFEG 0 1 0 0 3 0 0 0
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[lola][.] 67 CTL EXCL 12/238 6/2000 FireWire-PT-15-CTLFireability-2024-14 1319622 m, 96350 m/sec, 8219772 t fired, .
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[lola][.] 67 CTL EXCL 17/238 8/2000 FireWire-PT-15-CTLFireability-2024-14 1840780 m, 104231 m/sec, 11581341 t fired, .
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[lola][.] 67 CTL EXCL 22/238 10/2000 FireWire-PT-15-CTLFireability-2024-14 2348320 m, 101508 m/sec, 14992166 t fired, .
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[lola][.] 61 CTL EXCL 5/254 5/2000 FireWire-PT-15-CTLFireability-2024-12 1083762 m, 216752 m/sec, 3930007 t fired, .
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[lola][.] 61 CTL EXCL 10/254 9/2000 FireWire-PT-15-CTLFireability-2024-12 1944670 m, 172181 m/sec, 7974826 t fired, .
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[lola][.] 52 CTL EXCL 3/272 1/2000 FireWire-PT-15-CTLFireability-2024-09 193162 m, 38632 m/sec, 2099382 t fired, .
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[lola][.] 52 CTL EXCL 8/272 3/2000 FireWire-PT-15-CTLFireability-2024-09 498591 m, 61085 m/sec, 5974867 t fired, .
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[lola][.] 52 CTL EXCL 13/272 4/2000 FireWire-PT-15-CTLFireability-2024-09 785955 m, 57472 m/sec, 9706580 t fired, .
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[lola][.] 52 CTL EXCL 18/272 5/2000 FireWire-PT-15-CTLFireability-2024-09 1070091 m, 56827 m/sec, 13415887 t fired, .
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[lola][.] 52 CTL EXCL 23/272 6/2000 FireWire-PT-15-CTLFireability-2024-09 1282569 m, 42495 m/sec, 17343854 t fired, .
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[lola][.] FireWire-PT-15-CTLFireability-2024-03: EFEG 0 1 0 0 3 0 0 0
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[lola][.] 52 CTL EXCL 28/272 7/2000 FireWire-PT-15-CTLFireability-2024-09 1547486 m, 52983 m/sec, 21064559 t fired, .
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[lola][.] FireWire-PT-15-CTLFireability-2024-03: EFEG 0 1 0 0 3 0 0 0
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[lola][.] 52 CTL EXCL 33/272 8/2000 FireWire-PT-15-CTLFireability-2024-09 1792366 m, 48976 m/sec, 24886644 t fired, .
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[lola][.] FireWire-PT-15-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-15-CTLFireability-2024-03: EFEG 0 1 0 0 3 0 0 0
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[lola][.] 52 CTL EXCL 38/272 9/2000 FireWire-PT-15-CTLFireability-2024-09 2035241 m, 48575 m/sec, 28785908 t fired, .
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[lola][.] FireWire-PT-15-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
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[lola][.] 52 CTL EXCL 43/272 10/2000 FireWire-PT-15-CTLFireability-2024-09 2299468 m, 52845 m/sec, 32497821 t fired, .
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[lola][I] fired transitions : 33538096
[lola][I] time used : 44
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[lola][.] FireWire-PT-15-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
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[lola][.] 49 CTL EXCL 4/292 3/2000 FireWire-PT-15-CTLFireability-2024-08 482678 m, 96535 m/sec, 2738888 t fired, .
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[lola][.] 49 CTL EXCL 9/292 5/2000 FireWire-PT-15-CTLFireability-2024-08 1061727 m, 115809 m/sec, 6159965 t fired, .
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[lola][.] 49 CTL EXCL 14/292 7/2000 FireWire-PT-15-CTLFireability-2024-08 1569733 m, 101601 m/sec, 9675404 t fired, .
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[lola][.] 49 CTL EXCL 19/292 9/2000 FireWire-PT-15-CTLFireability-2024-08 2088324 m, 103718 m/sec, 13212786 t fired, .
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[lola][I] fired transitions : 14993271
[lola][I] time used : 22
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[lola][I] markings : 43
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[lola][I] fired transitions : 1572216
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[lola][I] fired transitions : 560
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[lola][I] result : true
[lola][I] markings : 168
[lola][I] fired transitions : 291
[lola][I] time used : 0
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[lola][I] FINISHED task # 43 (type EXCL) for FireWire-PT-15-CTLFireability-2024-06
[lola][I] result : true
[lola][I] markings : 3075
[lola][I] fired transitions : 6989
[lola][I] time used : 0
[lola][I] memory pages used : 1
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[lola][I] result : false
[lola][I] markings : 3627
[lola][I] fired transitions : 15912
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 3 (type EXCL) for 0 FireWire-PT-15-CTLFireability-2024-00
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[lola][.] FireWire-PT-15-CTLFireability-2024-01: DISJ true DISJ
[lola][.] FireWire-PT-15-CTLFireability-2024-02: CTL true CTL model checker
[lola][.] FireWire-PT-15-CTLFireability-2024-03: EFEG true state space /EFEG
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[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 3 CTL EXCL 0/1160 1/2000 FireWire-PT-15-CTLFireability-2024-00 101519 m, 20303 m/sec, 431813 t fired, .
[lola][.]
[lola][.] Time elapsed: 120 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I] FINISHED task # 3 (type EXCL) for FireWire-PT-15-CTLFireability-2024-00
[lola][I] result : false
[lola][I] markings : 257837
[lola][I] fired transitions : 1257387
[lola][I] time used : 1
[lola][I] memory pages used : 2
[lola][I] LAUNCH task # 64 (type EXCL) for 63 FireWire-PT-15-CTLFireability-2024-13
[lola][I] time limit : 1739 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 64 (type EXCL) for FireWire-PT-15-CTLFireability-2024-13
[lola][I] result : true
[lola][I] markings : 86
[lola][I] fired transitions : 102
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 37 (type EXCL) for 36 FireWire-PT-15-CTLFireability-2024-04
[lola][I] time limit : 3479 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 37 (type EXCL) for FireWire-PT-15-CTLFireability-2024-04
[lola][I] result : false
[lola][I] markings : 412
[lola][I] fired transitions : 761
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] Portfolio finished: no open formulas

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="FireWire-PT-15"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is FireWire-PT-15, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r551-tall-171734899800282"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/FireWire-PT-15.tgz
mv FireWire-PT-15 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;