About the Execution of LoLA for FireWire-PT-14
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16208.128 | 2390554.00 | 2453883.00 | 7464.50 | ?????????????F?? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r551-tall-171734899800274.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is FireWire-PT-14, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r551-tall-171734899800274
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 596K
-rw-r--r-- 1 mcc users 5.8K Jun 2 17:16 CTLCardinality.txt
-rw-r--r-- 1 mcc users 61K Jun 2 17:16 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.8K Jun 2 17:16 CTLFireability.txt
-rw-r--r-- 1 mcc users 58K Jun 2 17:16 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.5K Jun 2 17:12 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Jun 2 17:12 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Jun 2 17:12 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Jun 2 17:12 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 Jun 2 16:33 NewModel
-rw-r--r-- 1 mcc users 11K Jun 2 17:16 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 110K Jun 2 17:16 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.4K Jun 2 17:16 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 84K Jun 2 17:16 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Jun 2 17:12 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Jun 2 17:12 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Jun 2 16:33 equiv_col
-rw-r--r-- 1 mcc users 3 Jun 2 16:33 instance
-rw-r--r-- 1 mcc users 6 Jun 2 16:33 iscolored
-rw-r--r-- 1 mcc users 153K Jun 2 16:33 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME FireWire-PT-14-CTLFireability-2024-00
FORMULA_NAME FireWire-PT-14-CTLFireability-2024-01
FORMULA_NAME FireWire-PT-14-CTLFireability-2024-02
FORMULA_NAME FireWire-PT-14-CTLFireability-2024-03
FORMULA_NAME FireWire-PT-14-CTLFireability-2024-04
FORMULA_NAME FireWire-PT-14-CTLFireability-2024-05
FORMULA_NAME FireWire-PT-14-CTLFireability-2024-06
FORMULA_NAME FireWire-PT-14-CTLFireability-2024-07
FORMULA_NAME FireWire-PT-14-CTLFireability-2024-08
FORMULA_NAME FireWire-PT-14-CTLFireability-2024-09
FORMULA_NAME FireWire-PT-14-CTLFireability-2024-10
FORMULA_NAME FireWire-PT-14-CTLFireability-2024-11
FORMULA_NAME FireWire-PT-14-CTLFireability-2024-12
FORMULA_NAME FireWire-PT-14-CTLFireability-2024-13
FORMULA_NAME FireWire-PT-14-CTLFireability-2024-14
FORMULA_NAME FireWire-PT-14-CTLFireability-2024-15
=== Now, execution of the tool begins
BK_START 1717421343212
starting LoLA
BK_EXAMINATION: CTLFireability
BK_TIME_CONFINEMENT: 3600
BK_MEMORY_CONFINEMENT: 16384
BK_BIN_PATH: /home/mcc/BenchKit/bin/
current directory: /home/mcc/execution
FORMULA FireWire-PT-14-CTLFireability-2024-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1717423733766
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 52 (type EXCL) for 51 FireWire-PT-14-CTLFireability-2024-13
[[35mlola[0m][I] time limit : 156 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 52 (type EXCL) for FireWire-PT-14-CTLFireability-2024-13
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 615
[[35mlola[0m][I] fired transitions : 1152
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 28 (type EXCL) for 27 FireWire-PT-14-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 171 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 65 (type EQUN) for 39 FireWire-PT-14-CTLFireability-2024-09
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 63 (type FNDP) for 12 FireWire-PT-14-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 66 (type EQUN) for 12 FireWire-PT-14-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 15 (type CNST) for 12 FireWire-PT-14-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 15 (type CNST) for FireWire-PT-14-CTLFireability-2024-04
[[35mlola[0m][I] result : false
[[35mlola[0m][I] FINISHED task # 65 (type EQUN) for FireWire-PT-14-CTLFireability-2024-09
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] LAUNCH task # 70 (type EQUN) for 30 FireWire-PT-14-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 66 (type EQUN) for FireWire-PT-14-CTLFireability-2024-04
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] FINISHED task # 70 (type EQUN) for FireWire-PT-14-CTLFireability-2024-06
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 63 (type FNDP) for FireWire-PT-14-CTLFireability-2024-04
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 4733
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-14-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-14-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-14-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-14-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-14-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-14-CTLFireability-2024-04: DISJ 0 1 0 0 5 0 0 2
[[35mlola[0m][.] FireWire-PT-14-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-14-CTLFireability-2024-06: EXEF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] FireWire-PT-14-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-14-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-14-CTLFireability-2024-09: AXAG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] FireWire-PT-14-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-14-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-14-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-14-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-14-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 4/239 5/2000 FireWire-PT-14-CTLFireability-2024-05 964756 m, 192951 m/sec, 3167703 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 6 secs. Pages in use: 5
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 28 (type EXCL) for FireWire-PT-14-CTLFireability-2024-05
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1194796
[[35mlola[0m][I] fired transitions : 3880727
[[35mlola[0m][I] time used : 5
[[35mlola[0m][I] memory pages used : 6
[[35mlola[0m][I] LAUNCH task # 68 (type EXCL) for 30 FireWire-PT-14-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 256 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 68 (type EXCL) for FireWire-PT-14-CTLFireability-2024-06
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1254
[[35mlola[0m][I] fired transitions : 2663
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 62 (type EXCL) for 39 FireWire-PT-14-CTLFireability-2024-09
[[35mlola[0m][I] time limit : 276 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-14-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-14-CTLFireability-2024-06: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-14-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-14-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-14-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-14-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-14-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-14-CTLFireability-2024-04: DISJ 0 1 0 0 5 0 0 2
[[35mlola[0m][.] FireWire-PT-14-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-14-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-14-CTLFireability-2024-09: AXAG 0 0 1 0 2 0 0 0
[[35mlola[0m][.] FireWire-PT-14-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-14-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-14-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-14-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-14-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 EXEF EXCL 4/276 1/2000 FireWire-PT-14-CTLFireability-2024-09 264381 m, 52876 m/sec, 713580 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 11 secs. Pages in use: 6
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-14-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-14-CTLFireability-2024-06: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-14-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-14-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-14-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-14-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-14-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-14-CTLFireability-2024-04: DISJ 0 1 0 0 5 0 0 2
[[35mlola[0m][.] FireWire-PT-14-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-14-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-14-CTLFireability-2024-09: AXAG 0 0 1 0 2 0 0 0
[[35mlola[0m][.] FireWire-PT-14-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-14-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-14-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-14-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-14-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 EXEF EXCL 9/276 3/2000 FireWire-PT-14-CTLFireability-2024-09 600395 m, 67202 m/sec, 1623863 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 16 secs. Pages in use: 6
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-14-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-14-CTLFireability-2024-06: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-14-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-14-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-14-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-14-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-14-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-14-CTLFireability-2024-04: DISJ 0 1 0 0 5 0 0 2
[[35mlola[0m][.] FireWire-PT-14-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-14-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-14-CTLFireability-2024-09: AXAG 0 0 1 0 2 0 0 0
[[35mlola[0m][.] FireWire-PT-14-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-14-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-14-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-14-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-14-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 EXEF EXCL 14/276 4/2000 FireWire-PT-14-CTLFireability-2024-09 929372 m, 65795 m/sec, 2590044 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 21 secs. Pages in use: 6
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-14-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-14-CTLFireability-2024-06: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-14-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-14-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-14-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-14-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-14-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-14-CTLFireability-2024-04: DISJ 0 1 0 0 5 0 0 2
[[35mlola[0m][.] FireWire-PT-14-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-14-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-14-CTLFireability-2024-09: AXAG 0 0 1 0 2 0 0 0
[[35mlola[0m][.] FireWire-PT-14-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-14-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-14-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-14-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-14-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 EXEF EXCL 19/276 5/2000 FireWire-PT-14-CTLFireability-2024-09 1257196 m, 65564 m/sec, 3490749 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 26 secs. Pages in use: 6
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
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[[35mlola[0m][.] 62 EXEF EXCL 69/276 16/2000 FireWire-PT-14-CTLFireability-2024-09 4313574 m, 58079 m/sec, 12176636 t fired, .
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[[35mlola[0m][.] 37 CTL EXCL 232/330 165/2000 FireWire-PT-14-CTLFireability-2024-08 38542525 m, 158094 m/sec, 136403270 t fired, .
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[[35mlola[0m][I] FINISHED task # 34 (type EXCL) for FireWire-PT-14-CTLFireability-2024-07
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[[35mlola[0m][.] 19 CTL EXCL 227/647 166/2000 FireWire-PT-14-CTLFireability-2024-04 38826395 m, 163834 m/sec, 138554590 t fired, .
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[[35mlola[0m][.] 19 CTL EXCL 232/647 170/2000 FireWire-PT-14-CTLFireability-2024-04 39666976 m, 168116 m/sec, 141593596 t fired, .
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[[35mlola[0m][I] FINISHED task # 46 (type EXCL) for FireWire-PT-14-CTLFireability-2024-11
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[[35mlola[0m][.] 43 CTL EXCL 4/1708 4/2000 FireWire-PT-14-CTLFireability-2024-10 779594 m, 155918 m/sec, 4139978 t fired, .
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[[35mlola[0m][.] 43 CTL EXCL 9/1708 7/2000 FireWire-PT-14-CTLFireability-2024-10 1568790 m, 157839 m/sec, 8425987 t fired, .
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[[35mlola[0m][.] 43 CTL EXCL 14/1708 11/2000 FireWire-PT-14-CTLFireability-2024-10 2296097 m, 145461 m/sec, 12785600 t fired, .
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[[35mlola[0m][.] 43 CTL EXCL 19/1708 13/2000 FireWire-PT-14-CTLFireability-2024-10 2990613 m, 138903 m/sec, 16344740 t fired, .
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[[35mlola[0m][.] 43 CTL EXCL 24/1708 16/2000 FireWire-PT-14-CTLFireability-2024-10 3687055 m, 139288 m/sec, 20321207 t fired, .
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[[35mlola[0m][.] 43 CTL EXCL 29/1708 19/2000 FireWire-PT-14-CTLFireability-2024-10 4294173 m, 121423 m/sec, 23857809 t fired, .
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[[35mlola[0m][.] 43 CTL EXCL 34/1708 22/2000 FireWire-PT-14-CTLFireability-2024-10 4970980 m, 135361 m/sec, 27541893 t fired, .
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[[35mlola[0m][.] 43 CTL EXCL 39/1708 24/2000 FireWire-PT-14-CTLFireability-2024-10 5559619 m, 117727 m/sec, 31428728 t fired, .
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[[35mlola[0m][.] 43 CTL EXCL 44/1708 27/2000 FireWire-PT-14-CTLFireability-2024-10 6302209 m, 148518 m/sec, 35238076 t fired, .
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[[35mlola[0m][.] 43 CTL EXCL 49/1708 31/2000 FireWire-PT-14-CTLFireability-2024-10 7063655 m, 152289 m/sec, 39288775 t fired, .
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[[35mlola[0m][.] 43 CTL EXCL 54/1708 34/2000 FireWire-PT-14-CTLFireability-2024-10 7821056 m, 151480 m/sec, 43119742 t fired, .
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[[35mlola[0m][.] 43 CTL EXCL 59/1708 37/2000 FireWire-PT-14-CTLFireability-2024-10 8524552 m, 140699 m/sec, 47113974 t fired, .
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[[35mlola[0m][.] 43 CTL EXCL 79/1708 49/2000 FireWire-PT-14-CTLFireability-2024-10 11311918 m, 140151 m/sec, 62766551 t fired, .
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[[35mlola[0m][.] 43 CTL EXCL 84/1708 52/2000 FireWire-PT-14-CTLFireability-2024-10 12021946 m, 142005 m/sec, 66428792 t fired, .
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========== file over 1MB has been truncated ======
retrieve it from the run archives if needed
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="FireWire-PT-14"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is FireWire-PT-14, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r551-tall-171734899800274"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/FireWire-PT-14.tgz
mv FireWire-PT-14 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;