About the Execution of LoLA for FireWire-PT-10
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 1246.056 | 96687.00 | 99428.00 | 332.70 | FTFFFTTTTTFTFFTF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r551-tall-171734899700242.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is FireWire-PT-10, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r551-tall-171734899700242
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 620K
-rw-r--r-- 1 mcc users 7.2K Jun 2 17:16 CTLCardinality.txt
-rw-r--r-- 1 mcc users 80K Jun 2 17:16 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.3K Jun 2 17:16 CTLFireability.txt
-rw-r--r-- 1 mcc users 49K Jun 2 17:16 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.5K Jun 2 17:12 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Jun 2 17:12 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Jun 2 17:12 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Jun 2 17:12 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 Jun 2 16:33 NewModel
-rw-r--r-- 1 mcc users 15K Jun 2 17:16 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 178K Jun 2 17:16 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.7K Jun 2 17:16 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 78K Jun 2 17:16 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Jun 2 17:12 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Jun 2 17:12 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Jun 2 16:33 equiv_col
-rw-r--r-- 1 mcc users 3 Jun 2 16:33 instance
-rw-r--r-- 1 mcc users 6 Jun 2 16:33 iscolored
-rw-r--r-- 1 mcc users 101K Jun 2 16:33 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME FireWire-PT-10-CTLFireability-2024-00
FORMULA_NAME FireWire-PT-10-CTLFireability-2024-01
FORMULA_NAME FireWire-PT-10-CTLFireability-2024-02
FORMULA_NAME FireWire-PT-10-CTLFireability-2024-03
FORMULA_NAME FireWire-PT-10-CTLFireability-2024-04
FORMULA_NAME FireWire-PT-10-CTLFireability-2024-05
FORMULA_NAME FireWire-PT-10-CTLFireability-2024-06
FORMULA_NAME FireWire-PT-10-CTLFireability-2024-07
FORMULA_NAME FireWire-PT-10-CTLFireability-2024-08
FORMULA_NAME FireWire-PT-10-CTLFireability-2024-09
FORMULA_NAME FireWire-PT-10-CTLFireability-2024-10
FORMULA_NAME FireWire-PT-10-CTLFireability-2024-11
FORMULA_NAME FireWire-PT-10-CTLFireability-2024-12
FORMULA_NAME FireWire-PT-10-CTLFireability-2024-13
FORMULA_NAME FireWire-PT-10-CTLFireability-2024-14
FORMULA_NAME FireWire-PT-10-CTLFireability-2024-15
=== Now, execution of the tool begins
BK_START 1717416421259
starting LoLA
BK_EXAMINATION: CTLFireability
BK_TIME_CONFINEMENT: 3600
BK_MEMORY_CONFINEMENT: 16384
BK_BIN_PATH: /home/mcc/BenchKit/bin/
current directory: /home/mcc/execution
FORMULA FireWire-PT-10-CTLFireability-2024-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-10-CTLFireability-2024-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-10-CTLFireability-2024-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-10-CTLFireability-2024-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-10-CTLFireability-2024-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-10-CTLFireability-2024-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-10-CTLFireability-2024-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-10-CTLFireability-2024-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-10-CTLFireability-2024-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-10-CTLFireability-2024-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-10-CTLFireability-2024-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-10-CTLFireability-2024-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-10-CTLFireability-2024-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-10-CTLFireability-2024-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-10-CTLFireability-2024-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-10-CTLFireability-2024-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[[35mlola[0m] [1mFINAL RESULTS[0m
[[35mlola[0m] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m] [1m[31mFireWire-PT-10-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m] [1m[32mFireWire-PT-10-CTLFireability-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m] [1m[31mFireWire-PT-10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mFireWire-PT-10-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mFireWire-PT-10-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mFireWire-PT-10-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mFireWire-PT-10-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mFireWire-PT-10-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m] [1m[32mFireWire-PT-10-CTLFireability-2024-08: CONJ true CONJ[0m
[[35mlola[0m] [1m[32mFireWire-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mFireWire-PT-10-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mFireWire-PT-10-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mFireWire-PT-10-CTLFireability-2024-12: DISJ false DISJ[0m
[[35mlola[0m] [1m[31mFireWire-PT-10-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mFireWire-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mFireWire-PT-10-CTLFireability-2024-15: AXAF false state equation[0m
[[35mlola[0m]
[[35mlola[0m] Time elapsed: 96 secs. Pages in use: 54
BK_STOP 1717416517946
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 4 (type CNST) for 3 FireWire-PT-10-CTLFireability-2024-01
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 4 (type CNST) for FireWire-PT-10-CTLFireability-2024-01
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 19 (type EXCL) for 18 FireWire-PT-10-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 171 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 1 (type CNST) for 0 FireWire-PT-10-CTLFireability-2024-00
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 1 (type CNST) for FireWire-PT-10-CTLFireability-2024-00
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 59 (type EQUN) for 24 FireWire-PT-10-CTLFireability-2024-08
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 62 (type FNDP) for 21 FireWire-PT-10-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 63 (type EQUN) for 21 FireWire-PT-10-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 59 (type EQUN) for FireWire-PT-10-CTLFireability-2024-08
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] LAUNCH task # 67 (type EQUN) for 53 FireWire-PT-10-CTLFireability-2024-15
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 67 (type EQUN) for FireWire-PT-10-CTLFireability-2024-15
[[35mlola[0m][I] result : false
[[35mlola[0m][I] FINISHED task # 63 (type EQUN) for FireWire-PT-10-CTLFireability-2024-07
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] FINISHED task # 62 (type FNDP) for FireWire-PT-10-CTLFireability-2024-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 3510
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] FINISHED task # 19 (type EXCL) for FireWire-PT-10-CTLFireability-2024-06
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 458674
[[35mlola[0m][I] fired transitions : 2832547
[[35mlola[0m][I] time used : 3
[[35mlola[0m][I] memory pages used : 2
[[35mlola[0m][I] LAUNCH task # 51 (type EXCL) for 50 FireWire-PT-10-CTLFireability-2024-14
[[35mlola[0m][I] time limit : 276 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 51 (type EXCL) for FireWire-PT-10-CTLFireability-2024-14
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 81535
[[35mlola[0m][I] fired transitions : 525406
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 48 (type EXCL) for 47 FireWire-PT-10-CTLFireability-2024-13
[[35mlola[0m][I] time limit : 299 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 48 (type EXCL) for FireWire-PT-10-CTLFireability-2024-13
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 182571
[[35mlola[0m][I] fired transitions : 672053
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 45 (type EXCL) for 40 FireWire-PT-10-CTLFireability-2024-12
[[35mlola[0m][I] time limit : 326 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 45 (type EXCL) for FireWire-PT-10-CTLFireability-2024-12
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 83
[[35mlola[0m][I] fired transitions : 213
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 43 (type EXCL) for 40 FireWire-PT-10-CTLFireability-2024-12
[[35mlola[0m][I] time limit : 359 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 43 (type EXCL) for FireWire-PT-10-CTLFireability-2024-12
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 38 (type EXCL) for 37 FireWire-PT-10-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 399 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 38 (type EXCL) for FireWire-PT-10-CTLFireability-2024-11
[[35mlola[0m][I] result : true
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 35 (type EXCL) for 34 FireWire-PT-10-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 449 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 35 (type EXCL) for FireWire-PT-10-CTLFireability-2024-10
[[35mlola[0m][I] result : false
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 32 (type EXCL) for 31 FireWire-PT-10-CTLFireability-2024-09
[[35mlola[0m][I] time limit : 513 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 32 (type EXCL) for FireWire-PT-10-CTLFireability-2024-09
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 346
[[35mlola[0m][I] fired transitions : 1589
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 29 (type EXCL) for 24 FireWire-PT-10-CTLFireability-2024-08
[[35mlola[0m][I] time limit : 599 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 29 (type EXCL) for FireWire-PT-10-CTLFireability-2024-08
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] fired transitions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 16 (type EXCL) for 15 FireWire-PT-10-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 719 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 16 (type EXCL) for FireWire-PT-10-CTLFireability-2024-05
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 61
[[35mlola[0m][I] fired transitions : 99
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 13 (type EXCL) for 12 FireWire-PT-10-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 899 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 13 (type EXCL) for FireWire-PT-10-CTLFireability-2024-04
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 9238
[[35mlola[0m][I] fired transitions : 25802
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 10 (type EXCL) for 9 FireWire-PT-10-CTLFireability-2024-03
[[35mlola[0m][I] time limit : 1198 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-10-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-10-CTLFireability-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-10-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-10-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-10-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-10-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-10-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-10-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-10-CTLFireability-2024-12: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-10-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-10-CTLFireability-2024-15: AXAF false state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-10-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-10-CTLFireability-2024-08: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 1/1198 1/2000 FireWire-PT-10-CTLFireability-2024-03 142857 m, 28571 m/sec, 1063657 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-10-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-10-CTLFireability-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-10-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-10-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-10-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-10-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-10-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-10-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-10-CTLFireability-2024-12: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-10-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-10-CTLFireability-2024-15: AXAF false state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-10-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
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[[35mlola[0m][.] 10 CTL EXCL 6/1198 4/2000 FireWire-PT-10-CTLFireability-2024-03 847575 m, 140943 m/sec, 6729202 t fired, .
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[[35mlola[0m][I] result : false
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 7 (type EXCL) for 6 FireWire-PT-10-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 3504 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 7 (type EXCL) for FireWire-PT-10-CTLFireability-2024-02
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 24359
[[35mlola[0m][I] fired transitions : 90290
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] Portfolio finished: no open formulas
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="FireWire-PT-10"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is FireWire-PT-10, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r551-tall-171734899700242"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/FireWire-PT-10.tgz
mv FireWire-PT-10 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;