About the Execution of LoLA for FireWire-PT-09
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 1530.439 | 117808.00 | 121059.00 | 430.30 | TFTTTFTFTFTTTTFF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r551-tall-171734899700234.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is FireWire-PT-09, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r551-tall-171734899700234
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 588K
-rw-r--r-- 1 mcc users 7.4K Jun 2 17:16 CTLCardinality.txt
-rw-r--r-- 1 mcc users 85K Jun 2 17:16 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.7K Jun 2 17:16 CTLFireability.txt
-rw-r--r-- 1 mcc users 56K Jun 2 17:16 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.3K Jun 2 17:12 LTLCardinality.txt
-rw-r--r-- 1 mcc users 23K Jun 2 17:12 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Jun 2 17:12 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Jun 2 17:12 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 Jun 2 16:33 NewModel
-rw-r--r-- 1 mcc users 12K Jun 2 17:16 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 126K Jun 2 17:16 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Jun 2 17:16 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 99K Jun 2 17:16 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Jun 2 17:12 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Jun 2 17:12 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Jun 2 16:33 equiv_col
-rw-r--r-- 1 mcc users 3 Jun 2 16:33 instance
-rw-r--r-- 1 mcc users 6 Jun 2 16:33 iscolored
-rw-r--r-- 1 mcc users 100K Jun 2 16:33 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME FireWire-PT-09-CTLFireability-2024-00
FORMULA_NAME FireWire-PT-09-CTLFireability-2024-01
FORMULA_NAME FireWire-PT-09-CTLFireability-2024-02
FORMULA_NAME FireWire-PT-09-CTLFireability-2024-03
FORMULA_NAME FireWire-PT-09-CTLFireability-2024-04
FORMULA_NAME FireWire-PT-09-CTLFireability-2024-05
FORMULA_NAME FireWire-PT-09-CTLFireability-2024-06
FORMULA_NAME FireWire-PT-09-CTLFireability-2024-07
FORMULA_NAME FireWire-PT-09-CTLFireability-2024-08
FORMULA_NAME FireWire-PT-09-CTLFireability-2024-09
FORMULA_NAME FireWire-PT-09-CTLFireability-2024-10
FORMULA_NAME FireWire-PT-09-CTLFireability-2024-11
FORMULA_NAME FireWire-PT-09-CTLFireability-2024-12
FORMULA_NAME FireWire-PT-09-CTLFireability-2024-13
FORMULA_NAME FireWire-PT-09-CTLFireability-2024-14
FORMULA_NAME FireWire-PT-09-CTLFireability-2024-15
=== Now, execution of the tool begins
BK_START 1717416199206
starting LoLA
BK_EXAMINATION: CTLFireability
BK_TIME_CONFINEMENT: 3600
BK_MEMORY_CONFINEMENT: 16384
BK_BIN_PATH: /home/mcc/BenchKit/bin/
current directory: /home/mcc/execution
FORMULA FireWire-PT-09-CTLFireability-2024-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-09-CTLFireability-2024-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-09-CTLFireability-2024-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-09-CTLFireability-2024-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-09-CTLFireability-2024-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-09-CTLFireability-2024-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-09-CTLFireability-2024-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-09-CTLFireability-2024-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-09-CTLFireability-2024-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-09-CTLFireability-2024-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-09-CTLFireability-2024-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-09-CTLFireability-2024-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-09-CTLFireability-2024-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-09-CTLFireability-2024-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-09-CTLFireability-2024-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-09-CTLFireability-2024-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[[35mlola[0m] [1mFINAL RESULTS[0m
[[35mlola[0m] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m] [1m[32mFireWire-PT-09-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mFireWire-PT-09-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mFireWire-PT-09-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mFireWire-PT-09-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mFireWire-PT-09-CTLFireability-2024-04: DISJ true state space /EXEF[0m
[[35mlola[0m] [1m[31mFireWire-PT-09-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mFireWire-PT-09-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mFireWire-PT-09-CTLFireability-2024-07: AG false findpath[0m
[[35mlola[0m] [1m[32mFireWire-PT-09-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mFireWire-PT-09-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mFireWire-PT-09-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mFireWire-PT-09-CTLFireability-2024-11: DISJ true CTL model checker[0m
[[35mlola[0m] [1m[32mFireWire-PT-09-CTLFireability-2024-12: EF true findpath[0m
[[35mlola[0m] [1m[32mFireWire-PT-09-CTLFireability-2024-13: EF true findpath[0m
[[35mlola[0m] [1m[31mFireWire-PT-09-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mFireWire-PT-09-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m]
[[35mlola[0m] Time elapsed: 117 secs. Pages in use: 30
BK_STOP 1717416317014
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 7 (type EXCL) for 6 FireWire-PT-09-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 163 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 60 (type FNDP) for 48 FireWire-PT-09-CTLFireability-2024-12
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 61 (type EQUN) for 48 FireWire-PT-09-CTLFireability-2024-12
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 60 (type FNDP) for FireWire-PT-09-CTLFireability-2024-12
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 82
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 61 (type EQUN) for FireWire-PT-09-CTLFireability-2024-12 (obsolete)
[[35mlola[0m][I] FINISHED task # 7 (type EXCL) for FireWire-PT-09-CTLFireability-2024-02
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 7590
[[35mlola[0m][I] fired transitions : 22195
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 21 (type EXCL) for 12 FireWire-PT-09-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 189 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 21 (type EXCL) for FireWire-PT-09-CTLFireability-2024-04
[[35mlola[0m][I] result : false
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 19 (type EXCL) for 12 FireWire-PT-09-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 200 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 19 (type EXCL) for FireWire-PT-09-CTLFireability-2024-04
[[35mlola[0m][I] result : false
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 1 (type EXCL) for 0 FireWire-PT-09-CTLFireability-2024-00
[[35mlola[0m][I] time limit : 211 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 64 (type FNDP) for 29 FireWire-PT-09-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 65 (type EQUN) for 29 FireWire-PT-09-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 61 (type EQUN) for FireWire-PT-09-CTLFireability-2024-12
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] FINISHED task # 64 (type FNDP) for FireWire-PT-09-CTLFireability-2024-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 14
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 65 (type EQUN) for FireWire-PT-09-CTLFireability-2024-07 (obsolete)
[[35mlola[0m][I] FINISHED task # 65 (type EQUN) for FireWire-PT-09-CTLFireability-2024-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 67 (type FNDP) for 51 FireWire-PT-09-CTLFireability-2024-13
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 68 (type EQUN) for 51 FireWire-PT-09-CTLFireability-2024-13
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 72 (type EQUN) for 12 FireWire-PT-09-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 68 (type EQUN) for FireWire-PT-09-CTLFireability-2024-13
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] FINISHED task # 72 (type EQUN) for FireWire-PT-09-CTLFireability-2024-04
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] FINISHED task # 67 (type FNDP) for FireWire-PT-09-CTLFireability-2024-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 10494
[[35mlola[0m][I] time used : 2
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-09-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-09-CTLFireability-2024-07: AG false findpath[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-09-CTLFireability-2024-12: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-09-CTLFireability-2024-13: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-09-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-09-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-09-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-09-CTLFireability-2024-04: DISJ 0 1 0 0 6 0 0 0
[[35mlola[0m][.] FireWire-PT-09-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-09-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-09-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-09-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-09-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-09-CTLFireability-2024-11: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FireWire-PT-09-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-09-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 5/276 4/2000 FireWire-PT-09-CTLFireability-2024-00 849546 m, 169909 m/sec, 5087252 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-09-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-09-CTLFireability-2024-07: AG false findpath[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-09-CTLFireability-2024-12: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-09-CTLFireability-2024-13: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-09-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-09-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-09-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-09-CTLFireability-2024-04: DISJ 0 1 0 0 6 0 0 0
[[35mlola[0m][.] FireWire-PT-09-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-09-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-09-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-09-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-09-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-09-CTLFireability-2024-11: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FireWire-PT-09-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-09-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 10/276 8/2000 FireWire-PT-09-CTLFireability-2024-00 1866433 m, 203377 m/sec, 9927338 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs. Pages in use: 8
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 1 (type EXCL) for FireWire-PT-09-CTLFireability-2024-00
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 2138377
[[35mlola[0m][I] fired transitions : 11337919
[[35mlola[0m][I] time used : 12
[[35mlola[0m][I] memory pages used : 10
[[35mlola[0m][I] LAUNCH task # 70 (type EXCL) for 12 FireWire-PT-09-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 299 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-09-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-09-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-09-CTLFireability-2024-07: AG false findpath[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-09-CTLFireability-2024-12: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-09-CTLFireability-2024-13: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-09-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-09-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-09-CTLFireability-2024-04: DISJ 0 0 1 0 6 0 0 0
[[35mlola[0m][.] FireWire-PT-09-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-09-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-09-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-09-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-09-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-09-CTLFireability-2024-11: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FireWire-PT-09-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-09-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 70 EXEF EXCL 3/299 2/2000 FireWire-PT-09-CTLFireability-2024-04 338726 m, 67745 m/sec, 1134982 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 15 secs. Pages in use: 10
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[[35mlola[0m][I] FINISHED task # 70 (type EXCL) for FireWire-PT-09-CTLFireability-2024-04
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 501880
[[35mlola[0m][I] fired transitions : 1684505
[[35mlola[0m][I] time used : 5
[[35mlola[0m][I] memory pages used : 2
[[35mlola[0m][I] LAUNCH task # 58 (type EXCL) for 57 FireWire-PT-09-CTLFireability-2024-15
[[35mlola[0m][I] time limit : 325 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 58 (type EXCL) for FireWire-PT-09-CTLFireability-2024-15
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 181289
[[35mlola[0m][I] fired transitions : 828481
[[35mlola[0m][I] time used : 1
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[[35mlola[0m][I] LAUNCH task # 55 (type EXCL) for 54 FireWire-PT-09-CTLFireability-2024-14
[[35mlola[0m][I] time limit : 358 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 55 (type EXCL) for FireWire-PT-09-CTLFireability-2024-14
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 2539
[[35mlola[0m][I] fired transitions : 16108
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 44 (type EXCL) for 41 FireWire-PT-09-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 398 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
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[[35mlola[0m][.]
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[[35mlola[0m][.] 44 CTL EXCL 2/398 3/2000 FireWire-PT-09-CTLFireability-2024-11 571295 m, 114259 m/sec, 2815479 t fired, .
[[35mlola[0m][.]
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[[35mlola[0m][.] FireWire-PT-09-CTLFireability-2024-11: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 7/398 8/2000 FireWire-PT-09-CTLFireability-2024-11 1712787 m, 228298 m/sec, 7958497 t fired, .
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[[35mlola[0m][.] [1m[31mFireWire-PT-09-CTLFireability-2024-14: CTL false CTL model checker[0m
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[[35mlola[0m][.]
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[[35mlola[0m][.] FireWire-PT-09-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-09-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] FireWire-PT-09-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-09-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-09-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-09-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-09-CTLFireability-2024-11: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 12/398 12/2000 FireWire-PT-09-CTLFireability-2024-11 2774192 m, 212281 m/sec, 12910109 t fired, .
[[35mlola[0m][.]
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[[35mlola[0m][.] FireWire-PT-09-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 17/398 17/2000 FireWire-PT-09-CTLFireability-2024-11 3841238 m, 213409 m/sec, 17763385 t fired, .
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[[35mlola[0m][.] [1m[31mFireWire-PT-09-CTLFireability-2024-14: CTL false CTL model checker[0m
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[[35mlola[0m][.] FireWire-PT-09-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.]
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[[35mlola[0m][.] 44 CTL EXCL 22/398 21/2000 FireWire-PT-09-CTLFireability-2024-11 4899277 m, 211607 m/sec, 22044911 t fired, .
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[[35mlola[0m][.] 44 CTL EXCL 27/398 25/2000 FireWire-PT-09-CTLFireability-2024-11 5884598 m, 197064 m/sec, 26471445 t fired, .
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[[35mlola[0m][.]
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[[35mlola[0m][.] 44 CTL EXCL 32/398 30/2000 FireWire-PT-09-CTLFireability-2024-11 6900673 m, 203215 m/sec, 31055698 t fired, .
[[35mlola[0m][.]
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[[35mlola[0m][I] FINISHED task # 44 (type EXCL) for FireWire-PT-09-CTLFireability-2024-11
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 6927249
[[35mlola[0m][I] fired transitions : 31174906
[[35mlola[0m][I] time used : 32
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[[35mlola[0m][I] LAUNCH task # 39 (type EXCL) for 38 FireWire-PT-09-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 443 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 39 (type EXCL) for FireWire-PT-09-CTLFireability-2024-10
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 131
[[35mlola[0m][I] fired transitions : 432
[[35mlola[0m][I] time used : 0
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[[35mlola[0m][I] LAUNCH task # 33 (type EXCL) for 32 FireWire-PT-09-CTLFireability-2024-08
[[35mlola[0m][I] time limit : 507 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 33 (type EXCL) for FireWire-PT-09-CTLFireability-2024-08
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 170045
[[35mlola[0m][I] fired transitions : 784209
[[35mlola[0m][I] time used : 1
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[[35mlola[0m][I] LAUNCH task # 4 (type EXCL) for 3 FireWire-PT-09-CTLFireability-2024-01
[[35mlola[0m][I] time limit : 591 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 4 (type EXCL) for FireWire-PT-09-CTLFireability-2024-01
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 18513
[[35mlola[0m][I] fired transitions : 126603
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 46 (type EXCL) for 41 FireWire-PT-09-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 709 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-09-CTLFireability-2024-00: CTL true CTL model checker[0m
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[[35mlola[0m][.] 46 CTL EXCL 4/709 5/2000 FireWire-PT-09-CTLFireability-2024-11 996407 m, 199281 m/sec, 4566824 t fired, .
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[[35mlola[0m][I] FINISHED task # 46 (type EXCL) for FireWire-PT-09-CTLFireability-2024-11
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1759270
[[35mlola[0m][I] fired transitions : 8167780
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[[35mlola[0m][I] LAUNCH task # 24 (type EXCL) for 23 FireWire-PT-09-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 885 sec
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[[35mlola[0m][I] FINISHED task # 24 (type EXCL) for FireWire-PT-09-CTLFireability-2024-05
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 3837
[[35mlola[0m][I] fired transitions : 12752
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[[35mlola[0m][I] LAUNCH task # 27 (type EXCL) for 26 FireWire-PT-09-CTLFireability-2024-06
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[[35mlola[0m][.] 27 CTL EXCL 1/1180 2/2000 FireWire-PT-09-CTLFireability-2024-06 349353 m, 69870 m/sec, 1941224 t fired, .
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[[35mlola[0m][.] 27 CTL EXCL 6/1180 6/2000 FireWire-PT-09-CTLFireability-2024-06 1397702 m, 209669 m/sec, 7730131 t fired, .
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[[35mlola[0m][.] 27 CTL EXCL 11/1180 11/2000 FireWire-PT-09-CTLFireability-2024-06 2394082 m, 199276 m/sec, 13218958 t fired, .
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[[35mlola[0m][.] 27 CTL EXCL 16/1180 15/2000 FireWire-PT-09-CTLFireability-2024-06 3387928 m, 198769 m/sec, 18531143 t fired, .
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[[35mlola[0m][.] 27 CTL EXCL 21/1180 19/2000 FireWire-PT-09-CTLFireability-2024-06 4391299 m, 200674 m/sec, 23466973 t fired, .
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[[35mlola[0m][.] 27 CTL EXCL 26/1180 23/2000 FireWire-PT-09-CTLFireability-2024-06 5286070 m, 178954 m/sec, 28586206 t fired, .
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[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 5780976
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[[35mlola[0m][I] LAUNCH task # 36 (type EXCL) for 35 FireWire-PT-09-CTLFireability-2024-09
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[[35mlola[0m][.] 36 CTL EXCL 2/1756 3/2000 FireWire-PT-09-CTLFireability-2024-09 508971 m, 101794 m/sec, 2994150 t fired, .
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[[35mlola[0m][.] 36 CTL EXCL 7/1756 7/2000 FireWire-PT-09-CTLFireability-2024-09 1508317 m, 199869 m/sec, 8500917 t fired, .
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[[35mlola[0m][.] 36 CTL EXCL 12/1756 11/2000 FireWire-PT-09-CTLFireability-2024-09 2488949 m, 196126 m/sec, 13797388 t fired, .
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[[35mlola[0m][.] 36 CTL EXCL 17/1756 15/2000 FireWire-PT-09-CTLFireability-2024-09 3440353 m, 190280 m/sec, 18964490 t fired, .
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[[35mlola[0m][.] 36 CTL EXCL 22/1756 19/2000 FireWire-PT-09-CTLFireability-2024-09 4451995 m, 202328 m/sec, 23899785 t fired, .
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[[35mlola[0m][.] 36 CTL EXCL 27/1756 23/2000 FireWire-PT-09-CTLFireability-2024-09 5334962 m, 176593 m/sec, 29004966 t fired, .
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[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 5780976
[[35mlola[0m][I] fired transitions : 31452067
[[35mlola[0m][I] time used : 29
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[[35mlola[0m][I] LAUNCH task # 10 (type EXCL) for 9 FireWire-PT-09-CTLFireability-2024-03
[[35mlola[0m][I] time limit : 3483 sec
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[[35mlola[0m][I] FINISHED task # 10 (type EXCL) for FireWire-PT-09-CTLFireability-2024-03
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 192
[[35mlola[0m][I] fired transitions : 853
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] Portfolio finished: no open formulas
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="FireWire-PT-09"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is FireWire-PT-09, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r551-tall-171734899700234"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/FireWire-PT-09.tgz
mv FireWire-PT-09 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;