Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r551-tall-171734899700233.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
....................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is FireWire-PT-09, examination is CTLCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r551-tall-171734899700233
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 588K
-rw-r--r-- 1 mcc users 7.4K Jun 2 17:16 CTLCardinality.txt
-rw-r--r-- 1 mcc users 85K Jun 2 17:16 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.7K Jun 2 17:16 CTLFireability.txt
-rw-r--r-- 1 mcc users 56K Jun 2 17:16 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.3K Jun 2 17:12 LTLCardinality.txt
-rw-r--r-- 1 mcc users 23K Jun 2 17:12 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Jun 2 17:12 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Jun 2 17:12 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 Jun 2 16:33 NewModel
-rw-r--r-- 1 mcc users 12K Jun 2 17:16 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 126K Jun 2 17:16 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Jun 2 17:16 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 99K Jun 2 17:16 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Jun 2 17:12 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Jun 2 17:12 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Jun 2 16:33 equiv_col
-rw-r--r-- 1 mcc users 3 Jun 2 16:33 instance
-rw-r--r-- 1 mcc users 6 Jun 2 16:33 iscolored
-rw-r--r-- 1 mcc users 100K Jun 2 16:33 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME FireWire-PT-09-CTLCardinality-2024-00
FORMULA_NAME FireWire-PT-09-CTLCardinality-2024-01
FORMULA_NAME FireWire-PT-09-CTLCardinality-2024-02
FORMULA_NAME FireWire-PT-09-CTLCardinality-2024-03
FORMULA_NAME FireWire-PT-09-CTLCardinality-2024-04
FORMULA_NAME FireWire-PT-09-CTLCardinality-2024-05
FORMULA_NAME FireWire-PT-09-CTLCardinality-2024-06
FORMULA_NAME FireWire-PT-09-CTLCardinality-2024-07
FORMULA_NAME FireWire-PT-09-CTLCardinality-2024-08
FORMULA_NAME FireWire-PT-09-CTLCardinality-2024-09
FORMULA_NAME FireWire-PT-09-CTLCardinality-2024-10
FORMULA_NAME FireWire-PT-09-CTLCardinality-2024-11
FORMULA_NAME FireWire-PT-09-CTLCardinality-2024-12
FORMULA_NAME FireWire-PT-09-CTLCardinality-2024-13
FORMULA_NAME FireWire-PT-09-CTLCardinality-2024-14
FORMULA_NAME FireWire-PT-09-CTLCardinality-2024-15

=== Now, execution of the tool begins

BK_START 1717416145348

starting LoLA
BK_EXAMINATION: CTLCardinality
BK_TIME_CONFINEMENT: 3600
BK_MEMORY_CONFINEMENT: 16384
BK_BIN_PATH: /home/mcc/BenchKit/bin/
current directory: /home/mcc/execution
FORMULA FireWire-PT-09-CTLCardinality-2024-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-09-CTLCardinality-2024-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-09-CTLCardinality-2024-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-09-CTLCardinality-2024-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-09-CTLCardinality-2024-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-09-CTLCardinality-2024-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-09-CTLCardinality-2024-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-09-CTLCardinality-2024-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-09-CTLCardinality-2024-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-09-CTLCardinality-2024-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-09-CTLCardinality-2024-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-09-CTLCardinality-2024-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-09-CTLCardinality-2024-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-09-CTLCardinality-2024-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-09-CTLCardinality-2024-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-09-CTLCardinality-2024-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[lola] FINAL RESULTS
[lola]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola] FireWire-PT-09-CTLCardinality-2024-00: INITIAL false preprocessing
[lola] FireWire-PT-09-CTLCardinality-2024-01: CTL false CTL model checker
[lola] FireWire-PT-09-CTLCardinality-2024-02: CTL true CTL model checker
[lola] FireWire-PT-09-CTLCardinality-2024-03: CTL true CTL model checker
[lola] FireWire-PT-09-CTLCardinality-2024-04: CTL false CTL model checker
[lola] FireWire-PT-09-CTLCardinality-2024-05: AG false findpath
[lola] FireWire-PT-09-CTLCardinality-2024-06: CTL true CTL model checker
[lola] FireWire-PT-09-CTLCardinality-2024-07: CTL true CTL model checker
[lola] FireWire-PT-09-CTLCardinality-2024-08: EFEG true state space /EFEG
[lola] FireWire-PT-09-CTLCardinality-2024-09: CTL false CTL model checker
[lola] FireWire-PT-09-CTLCardinality-2024-10: INITIAL true preprocessing
[lola] FireWire-PT-09-CTLCardinality-2024-11: CTL true CTL model checker
[lola] FireWire-PT-09-CTLCardinality-2024-12: AGEFAG false tscc_search
[lola] FireWire-PT-09-CTLCardinality-2024-13: INITIAL false preprocessing
[lola] FireWire-PT-09-CTLCardinality-2024-14: CTL false CTL model checker
[lola] FireWire-PT-09-CTLCardinality-2024-15: INITIAL false preprocessing
[lola]
[lola] Time elapsed: 61 secs. Pages in use: 8

BK_STOP 1717416206611

--------------------
content from stderr:

[lola][I] LoLA will run for 3600 seconds at most (--timelimit)
[lola][W] unknown unit in memory specification: using default
[lola][I] MEM LIMIT 5
[lola][I] NET
[lola][I] reading net from model.pnml
[lola][I] input: PNML file (--pnmlnet)
[lola][I] reading pnml
[lola][I] PNML file contains place/transition net
[lola][I] closed net file model.pnml
[lola][I] finished parsing
[lola][I] Reading formula.
[lola][I] Using XML format (--xmlformula)
[lola][I] reading XML formula
[lola][I] reading formula from CTLCardinality.xml
[lola][I] Rule S: 0 transitions removed,0 places removed
[lola][I] LAUNCH task # 1 (type CNST) for 0 FireWire-PT-09-CTLCardinality-2024-00
[lola][I] time limit : 0 sec
[lola][I] memory limit: 0 pages
[lola][I] FINISHED task # 1 (type CNST) for FireWire-PT-09-CTLCardinality-2024-00
[lola][I] result : false
[lola][I] LAUNCH task # 40 (type CNST) for 39 FireWire-PT-09-CTLCardinality-2024-13
[lola][I] time limit : 0 sec
[lola][I] memory limit: 0 pages
[lola][I] FINISHED task # 40 (type CNST) for FireWire-PT-09-CTLCardinality-2024-13
[lola][I] result : false
[lola][I] LAUNCH task # 31 (type CNST) for 30 FireWire-PT-09-CTLCardinality-2024-10
[lola][I] time limit : 0 sec
[lola][I] memory limit: 0 pages
[lola][I] LAUNCH task # 46 (type CNST) for 45 FireWire-PT-09-CTLCardinality-2024-15
[lola][I] time limit : 0 sec
[lola][I] memory limit: 0 pages
[lola][I] FINISHED task # 31 (type CNST) for FireWire-PT-09-CTLCardinality-2024-10
[lola][I] result : true
[lola][I] FINISHED task # 46 (type CNST) for FireWire-PT-09-CTLCardinality-2024-15
[lola][I] result : false
[lola][I] LAUNCH task # 48 (type EXCL) for 24 FireWire-PT-09-CTLCardinality-2024-08
[lola][I] time limit : 298 sec
[lola][I] memory limit: 2000 pages
[lola][I] LAUNCH task # 51 (type EQUN) for 24 FireWire-PT-09-CTLCardinality-2024-08
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 53 (type EQUN) for 24 FireWire-PT-09-CTLCardinality-2024-08
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 51 (type EQUN) for FireWire-PT-09-CTLCardinality-2024-08
[lola][I] result : unknown
[lola][I] LAUNCH task # 55 (type FNDP) for 15 FireWire-PT-09-CTLCardinality-2024-05
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 56 (type EQUN) for 15 FireWire-PT-09-CTLCardinality-2024-05
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 53 (type EQUN) for FireWire-PT-09-CTLCardinality-2024-08
[lola][I] result : unknown
[lola][I] LAUNCH task # 62 (type EQUN) for 36 FireWire-PT-09-CTLCardinality-2024-12
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 62 (type EQUN) for FireWire-PT-09-CTLCardinality-2024-12
[lola][I] result : unknown
[lola][I] LAUNCH task # 64 (type EQUN) for 36 FireWire-PT-09-CTLCardinality-2024-12
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 56 (type EQUN) for FireWire-PT-09-CTLCardinality-2024-05
[lola][I] result : unknown
[lola][I] FINISHED task # 64 (type EQUN) for FireWire-PT-09-CTLCardinality-2024-12
[lola][I] result : unknown
[lola][I] FINISHED task # 55 (type FNDP) for FireWire-PT-09-CTLCardinality-2024-05
[lola][I] result : true
[lola][I] tried executions : 886
[lola][I] time used : 0
[lola][I] memory pages used : 0
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] FireWire-PT-09-CTLCardinality-2024-00: INITIAL false preprocessing
[lola][.] FireWire-PT-09-CTLCardinality-2024-05: AG false findpath
[lola][.] FireWire-PT-09-CTLCardinality-2024-10: INITIAL true preprocessing
[lola][.] FireWire-PT-09-CTLCardinality-2024-13: INITIAL false preprocessing
[lola][.] FireWire-PT-09-CTLCardinality-2024-15: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] FireWire-PT-09-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-09-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-09-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-09-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-09-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-09-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-09-CTLCardinality-2024-08: EFEG 0 0 1 0 3 0 0 0
[lola][.] FireWire-PT-09-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-09-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-09-CTLCardinality-2024-12: AGEFAG 0 1 0 0 3 0 0 0
[lola][.] FireWire-PT-09-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 EFEG EXCL 4/325 2/2000 FireWire-PT-09-CTLCardinality-2024-08 431500 m, 86300 m/sec, 1452063 t fired, .
[lola][.]
[lola][.] Time elapsed: 27 secs. Pages in use: 2
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I] FINISHED task # 48 (type EXCL) for FireWire-PT-09-CTLCardinality-2024-08
[lola][I] result : true
[lola][I] markings : 501842
[lola][I] fired transitions : 1684460
[lola][I] time used : 5
[lola][I] memory pages used : 2
[lola][I] LAUNCH task # 28 (type EXCL) for 27 FireWire-PT-09-CTLCardinality-2024-09
[lola][I] time limit : 357 sec
[lola][I] memory limit: 2000 pages
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] FireWire-PT-09-CTLCardinality-2024-00: INITIAL false preprocessing
[lola][.] FireWire-PT-09-CTLCardinality-2024-05: AG false findpath
[lola][.] FireWire-PT-09-CTLCardinality-2024-08: EFEG true state space /EFEG
[lola][.] FireWire-PT-09-CTLCardinality-2024-10: INITIAL true preprocessing
[lola][.] FireWire-PT-09-CTLCardinality-2024-13: INITIAL false preprocessing
[lola][.] FireWire-PT-09-CTLCardinality-2024-15: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] FireWire-PT-09-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-09-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-09-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-09-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-09-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-09-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-09-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[lola][.] FireWire-PT-09-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-09-CTLCardinality-2024-12: AGEFAG 0 1 0 0 3 0 0 0
[lola][.] FireWire-PT-09-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 28 CTL EXCL 4/357 3/2000 FireWire-PT-09-CTLCardinality-2024-09 589505 m, 117901 m/sec, 4685540 t fired, .
[lola][.]
[lola][.] Time elapsed: 32 secs. Pages in use: 3
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I] FINISHED task # 28 (type EXCL) for FireWire-PT-09-CTLCardinality-2024-09
[lola][I] result : false
[lola][I] markings : 693706
[lola][I] fired transitions : 5564714
[lola][I] time used : 5
[lola][I] memory pages used : 3
[lola][I] LAUNCH task # 22 (type EXCL) for 21 FireWire-PT-09-CTLCardinality-2024-07
[lola][I] time limit : 396 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 22 (type EXCL) for FireWire-PT-09-CTLCardinality-2024-07
[lola][I] result : true
[lola][I] markings : 5933
[lola][I] fired transitions : 19154
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 19 (type EXCL) for 18 FireWire-PT-09-CTLCardinality-2024-06
[lola][I] time limit : 445 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 19 (type EXCL) for FireWire-PT-09-CTLCardinality-2024-06
[lola][I] result : true
[lola][I] markings : 173
[lola][I] fired transitions : 498
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 7 (type EXCL) for 6 FireWire-PT-09-CTLCardinality-2024-02
[lola][I] time limit : 509 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 7 (type EXCL) for FireWire-PT-09-CTLCardinality-2024-02
[lola][I] result : true
[lola][I] markings : 15438
[lola][I] fired transitions : 72170
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 4 (type EXCL) for 3 FireWire-PT-09-CTLCardinality-2024-01
[lola][I] time limit : 594 sec
[lola][I] memory limit: 2000 pages
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] FireWire-PT-09-CTLCardinality-2024-00: INITIAL false preprocessing
[lola][.] FireWire-PT-09-CTLCardinality-2024-02: CTL true CTL model checker
[lola][.] FireWire-PT-09-CTLCardinality-2024-05: AG false findpath
[lola][.] FireWire-PT-09-CTLCardinality-2024-06: CTL true CTL model checker
[lola][.] FireWire-PT-09-CTLCardinality-2024-07: CTL true CTL model checker
[lola][.] FireWire-PT-09-CTLCardinality-2024-08: EFEG true state space /EFEG
[lola][.] FireWire-PT-09-CTLCardinality-2024-09: CTL false CTL model checker
[lola][.] FireWire-PT-09-CTLCardinality-2024-10: INITIAL true preprocessing
[lola][.] FireWire-PT-09-CTLCardinality-2024-13: INITIAL false preprocessing
[lola][.] FireWire-PT-09-CTLCardinality-2024-15: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] FireWire-PT-09-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[lola][.] FireWire-PT-09-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-09-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-09-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-09-CTLCardinality-2024-12: AGEFAG 0 1 0 0 3 0 0 0
[lola][.] FireWire-PT-09-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 4 CTL EXCL 4/594 5/2000 FireWire-PT-09-CTLCardinality-2024-01 1018897 m, 203779 m/sec, 4422280 t fired, .
[lola][.]
[lola][.] Time elapsed: 37 secs. Pages in use: 5
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I] FINISHED task # 4 (type EXCL) for FireWire-PT-09-CTLCardinality-2024-01
[lola][I] result : false
[lola][I] markings : 1553763
[lola][I] fired transitions : 6736965
[lola][I] time used : 7
[lola][I] memory pages used : 7
[lola][I] LAUNCH task # 59 (type EXCL) for 36 FireWire-PT-09-CTLCardinality-2024-12
[lola][I] time limit : 712 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 59 (type EXCL) for FireWire-PT-09-CTLCardinality-2024-12
[lola][I] result : true
[lola][I] markings : 172
[lola][I] fired transitions : 324
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 13 (type EXCL) for 12 FireWire-PT-09-CTLCardinality-2024-04
[lola][I] time limit : 890 sec
[lola][I] memory limit: 2000 pages
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] FireWire-PT-09-CTLCardinality-2024-00: INITIAL false preprocessing
[lola][.] FireWire-PT-09-CTLCardinality-2024-01: CTL false CTL model checker
[lola][.] FireWire-PT-09-CTLCardinality-2024-02: CTL true CTL model checker
[lola][.] FireWire-PT-09-CTLCardinality-2024-05: AG false findpath
[lola][.] FireWire-PT-09-CTLCardinality-2024-06: CTL true CTL model checker
[lola][.] FireWire-PT-09-CTLCardinality-2024-07: CTL true CTL model checker
[lola][.] FireWire-PT-09-CTLCardinality-2024-08: EFEG true state space /EFEG
[lola][.] FireWire-PT-09-CTLCardinality-2024-09: CTL false CTL model checker
[lola][.] FireWire-PT-09-CTLCardinality-2024-10: INITIAL true preprocessing
[lola][.] FireWire-PT-09-CTLCardinality-2024-12: AGEFAG false tscc_search
[lola][.] FireWire-PT-09-CTLCardinality-2024-13: INITIAL false preprocessing
[lola][.] FireWire-PT-09-CTLCardinality-2024-15: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] FireWire-PT-09-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-09-CTLCardinality-2024-04: CTL 0 0 1 0 1 0 0 0
[lola][.] FireWire-PT-09-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-09-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 13 CTL EXCL 2/890 3/2000 FireWire-PT-09-CTLCardinality-2024-04 540983 m, 108196 m/sec, 3241588 t fired, .
[lola][.]
[lola][.] Time elapsed: 42 secs. Pages in use: 7
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] FireWire-PT-09-CTLCardinality-2024-00: INITIAL false preprocessing
[lola][.] FireWire-PT-09-CTLCardinality-2024-01: CTL false CTL model checker
[lola][.] FireWire-PT-09-CTLCardinality-2024-02: CTL true CTL model checker
[lola][.] FireWire-PT-09-CTLCardinality-2024-05: AG false findpath
[lola][.] FireWire-PT-09-CTLCardinality-2024-06: CTL true CTL model checker
[lola][.] FireWire-PT-09-CTLCardinality-2024-07: CTL true CTL model checker
[lola][.] FireWire-PT-09-CTLCardinality-2024-08: EFEG true state space /EFEG
[lola][.] FireWire-PT-09-CTLCardinality-2024-09: CTL false CTL model checker
[lola][.] FireWire-PT-09-CTLCardinality-2024-10: INITIAL true preprocessing
[lola][.] FireWire-PT-09-CTLCardinality-2024-12: AGEFAG false tscc_search
[lola][.] FireWire-PT-09-CTLCardinality-2024-13: INITIAL false preprocessing
[lola][.] FireWire-PT-09-CTLCardinality-2024-15: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] FireWire-PT-09-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-09-CTLCardinality-2024-04: CTL 0 0 1 0 1 0 0 0
[lola][.] FireWire-PT-09-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] FireWire-PT-09-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 13 CTL EXCL 7/890 7/2000 FireWire-PT-09-CTLCardinality-2024-04 1516015 m, 195006 m/sec, 8663057 t fired, .
[lola][.]
[lola][.] Time elapsed: 47 secs. Pages in use: 7
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I] FINISHED task # 13 (type EXCL) for FireWire-PT-09-CTLCardinality-2024-04
[lola][I] result : false
[lola][I] markings : 1758532
[lola][I] fired transitions : 10097075
[lola][I] time used : 9
[lola][I] memory pages used : 8
[lola][I] LAUNCH task # 10 (type EXCL) for 9 FireWire-PT-09-CTLCardinality-2024-03
[lola][I] time limit : 1183 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 10 (type EXCL) for FireWire-PT-09-CTLCardinality-2024-03
[lola][I] result : true
[lola][I] markings : 722998
[lola][I] fired transitions : 4312049
[lola][I] time used : 3
[lola][I] memory pages used : 4
[lola][I] LAUNCH task # 34 (type EXCL) for 33 FireWire-PT-09-CTLCardinality-2024-11
[lola][I] time limit : 1774 sec
[lola][I] memory limit: 2000 pages
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] FireWire-PT-09-CTLCardinality-2024-00: INITIAL false preprocessing
[lola][.] FireWire-PT-09-CTLCardinality-2024-01: CTL false CTL model checker
[lola][.] FireWire-PT-09-CTLCardinality-2024-02: CTL true CTL model checker
[lola][.] FireWire-PT-09-CTLCardinality-2024-03: CTL true CTL model checker
[lola][.] FireWire-PT-09-CTLCardinality-2024-04: CTL false CTL model checker
[lola][.] FireWire-PT-09-CTLCardinality-2024-05: AG false findpath
[lola][.] FireWire-PT-09-CTLCardinality-2024-06: CTL true CTL model checker
[lola][.] FireWire-PT-09-CTLCardinality-2024-07: CTL true CTL model checker
[lola][.] FireWire-PT-09-CTLCardinality-2024-08: EFEG true state space /EFEG
[lola][.] FireWire-PT-09-CTLCardinality-2024-09: CTL false CTL model checker
[lola][.] FireWire-PT-09-CTLCardinality-2024-10: INITIAL true preprocessing
[lola][.] FireWire-PT-09-CTLCardinality-2024-12: AGEFAG false tscc_search
[lola][.] FireWire-PT-09-CTLCardinality-2024-13: INITIAL false preprocessing
[lola][.] FireWire-PT-09-CTLCardinality-2024-15: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] FireWire-PT-09-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[lola][.] FireWire-PT-09-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 34 CTL EXCL 0/1774 1/2000 FireWire-PT-09-CTLCardinality-2024-11 66502 m, 13300 m/sec, 289458 t fired, .
[lola][.]
[lola][.] Time elapsed: 52 secs. Pages in use: 8
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] FireWire-PT-09-CTLCardinality-2024-00: INITIAL false preprocessing
[lola][.] FireWire-PT-09-CTLCardinality-2024-01: CTL false CTL model checker
[lola][.] FireWire-PT-09-CTLCardinality-2024-02: CTL true CTL model checker
[lola][.] FireWire-PT-09-CTLCardinality-2024-03: CTL true CTL model checker
[lola][.] FireWire-PT-09-CTLCardinality-2024-04: CTL false CTL model checker
[lola][.] FireWire-PT-09-CTLCardinality-2024-05: AG false findpath
[lola][.] FireWire-PT-09-CTLCardinality-2024-06: CTL true CTL model checker
[lola][.] FireWire-PT-09-CTLCardinality-2024-07: CTL true CTL model checker
[lola][.] FireWire-PT-09-CTLCardinality-2024-08: EFEG true state space /EFEG
[lola][.] FireWire-PT-09-CTLCardinality-2024-09: CTL false CTL model checker
[lola][.] FireWire-PT-09-CTLCardinality-2024-10: INITIAL true preprocessing
[lola][.] FireWire-PT-09-CTLCardinality-2024-12: AGEFAG false tscc_search
[lola][.] FireWire-PT-09-CTLCardinality-2024-13: INITIAL false preprocessing
[lola][.] FireWire-PT-09-CTLCardinality-2024-15: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] FireWire-PT-09-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[lola][.] FireWire-PT-09-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 34 CTL EXCL 5/1774 6/2000 FireWire-PT-09-CTLCardinality-2024-11 1280702 m, 242840 m/sec, 5754695 t fired, .
[lola][.]
[lola][.] Time elapsed: 57 secs. Pages in use: 8
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I] FINISHED task # 34 (type EXCL) for FireWire-PT-09-CTLCardinality-2024-11
[lola][I] result : true
[lola][I] markings : 1728731
[lola][I] fired transitions : 8045899
[lola][I] time used : 8
[lola][I] memory pages used : 8
[lola][I] LAUNCH task # 43 (type EXCL) for 42 FireWire-PT-09-CTLCardinality-2024-14
[lola][I] time limit : 3540 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 43 (type EXCL) for FireWire-PT-09-CTLCardinality-2024-14
[lola][I] result : false
[lola][I] markings : 270773
[lola][I] fired transitions : 1775617
[lola][I] time used : 1
[lola][I] memory pages used : 2
[lola][I] Portfolio finished: no open formulas

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="FireWire-PT-09"
export BK_EXAMINATION="CTLCardinality"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is FireWire-PT-09, examination is CTLCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r551-tall-171734899700233"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/FireWire-PT-09.tgz
mv FireWire-PT-09 execution
cd execution
if [ "CTLCardinality" = "ReachabilityDeadlock" ] || [ "CTLCardinality" = "UpperBounds" ] || [ "CTLCardinality" = "QuasiLiveness" ] || [ "CTLCardinality" = "StableMarking" ] || [ "CTLCardinality" = "Liveness" ] || [ "CTLCardinality" = "OneSafe" ] || [ "CTLCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLCardinality" = "ReachabilityDeadlock" ] || [ "CTLCardinality" = "QuasiLiveness" ] || [ "CTLCardinality" = "StableMarking" ] || [ "CTLCardinality" = "Liveness" ] || [ "CTLCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;