About the Execution of LoLA for FireWire-PT-06
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 1439.596 | 141962.00 | 146000.00 | 496.20 | TFTTFTTFFTTTFTTT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r551-tall-171734899600210.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is FireWire-PT-06, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r551-tall-171734899600210
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 504K
-rw-r--r-- 1 mcc users 6.8K Jun 2 17:16 CTLCardinality.txt
-rw-r--r-- 1 mcc users 76K Jun 2 17:16 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.2K Jun 2 17:16 CTLFireability.txt
-rw-r--r-- 1 mcc users 48K Jun 2 17:16 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.4K Jun 2 17:12 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Jun 2 17:12 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Jun 2 17:12 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Jun 2 17:12 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 Jun 2 16:33 NewModel
-rw-r--r-- 1 mcc users 9.9K Jun 2 17:16 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 109K Jun 2 17:16 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.3K Jun 2 17:16 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 62K Jun 2 17:16 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Jun 2 17:12 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Jun 2 17:12 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Jun 2 16:33 equiv_col
-rw-r--r-- 1 mcc users 3 Jun 2 16:33 instance
-rw-r--r-- 1 mcc users 6 Jun 2 16:33 iscolored
-rw-r--r-- 1 mcc users 90K Jun 2 16:33 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME FireWire-PT-06-CTLFireability-2024-00
FORMULA_NAME FireWire-PT-06-CTLFireability-2024-01
FORMULA_NAME FireWire-PT-06-CTLFireability-2024-02
FORMULA_NAME FireWire-PT-06-CTLFireability-2024-03
FORMULA_NAME FireWire-PT-06-CTLFireability-2024-04
FORMULA_NAME FireWire-PT-06-CTLFireability-2024-05
FORMULA_NAME FireWire-PT-06-CTLFireability-2024-06
FORMULA_NAME FireWire-PT-06-CTLFireability-2024-07
FORMULA_NAME FireWire-PT-06-CTLFireability-2024-08
FORMULA_NAME FireWire-PT-06-CTLFireability-2024-09
FORMULA_NAME FireWire-PT-06-CTLFireability-2024-10
FORMULA_NAME FireWire-PT-06-CTLFireability-2024-11
FORMULA_NAME FireWire-PT-06-CTLFireability-2024-12
FORMULA_NAME FireWire-PT-06-CTLFireability-2024-13
FORMULA_NAME FireWire-PT-06-CTLFireability-2024-14
FORMULA_NAME FireWire-PT-06-CTLFireability-2024-15
=== Now, execution of the tool begins
BK_START 1717415431211
starting LoLA
BK_EXAMINATION: CTLFireability
BK_TIME_CONFINEMENT: 3600
BK_MEMORY_CONFINEMENT: 16384
BK_BIN_PATH: /home/mcc/BenchKit/bin/
current directory: /home/mcc/execution
FORMULA FireWire-PT-06-CTLFireability-2024-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-06-CTLFireability-2024-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-06-CTLFireability-2024-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-06-CTLFireability-2024-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-06-CTLFireability-2024-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-06-CTLFireability-2024-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-06-CTLFireability-2024-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-06-CTLFireability-2024-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-06-CTLFireability-2024-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-06-CTLFireability-2024-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-06-CTLFireability-2024-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-06-CTLFireability-2024-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-06-CTLFireability-2024-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-06-CTLFireability-2024-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-06-CTLFireability-2024-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-06-CTLFireability-2024-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[[35mlola[0m] [1mFINAL RESULTS[0m
[[35mlola[0m] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m] [1m[32mFireWire-PT-06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mFireWire-PT-06-CTLFireability-2024-01: DISJ false DISJ[0m
[[35mlola[0m] [1m[32mFireWire-PT-06-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mFireWire-PT-06-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mFireWire-PT-06-CTLFireability-2024-04: SP ECTL false LTL model checker[0m
[[35mlola[0m] [1m[32mFireWire-PT-06-CTLFireability-2024-05: EF true findpath[0m
[[35mlola[0m] [1m[32mFireWire-PT-06-CTLFireability-2024-06: EFEG true state space /EFEG[0m
[[35mlola[0m] [1m[31mFireWire-PT-06-CTLFireability-2024-07: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mFireWire-PT-06-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mFireWire-PT-06-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mFireWire-PT-06-CTLFireability-2024-10: DISJ true CTL model checker[0m
[[35mlola[0m] [1m[32mFireWire-PT-06-CTLFireability-2024-11: EF true findpath[0m
[[35mlola[0m] [1m[31mFireWire-PT-06-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mFireWire-PT-06-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m] [1m[32mFireWire-PT-06-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mFireWire-PT-06-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m]
[[35mlola[0m] Time elapsed: 142 secs. Pages in use: 25
BK_STOP 1717415573173
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 22 (type EXCL) for 21 FireWire-PT-06-CTLFireability-2024-03
[[35mlola[0m][I] time limit : 133 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 67 (type EQUN) for 30 FireWire-PT-06-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 69 (type EQUN) for 30 FireWire-PT-06-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 22 (type EXCL) for FireWire-PT-06-CTLFireability-2024-03
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 3960
[[35mlola[0m][I] fired transitions : 13076
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 64 (type EXCL) for 30 FireWire-PT-06-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 144 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 64 (type EXCL) for FireWire-PT-06-CTLFireability-2024-06
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 21
[[35mlola[0m][I] fired transitions : 21
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 67 (type EQUN) for FireWire-PT-06-CTLFireability-2024-06 (obsolete)
[[35mlola[0m][W] CANCELED task # 69 (type EQUN) for FireWire-PT-06-CTLFireability-2024-06 (obsolete)
[[35mlola[0m][I] FINISHED task # 67 (type EQUN) for FireWire-PT-06-CTLFireability-2024-06
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] LAUNCH task # 1 (type EXCL) for 0 FireWire-PT-06-CTLFireability-2024-00
[[35mlola[0m][I] time limit : 150 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 69 (type EQUN) for FireWire-PT-06-CTLFireability-2024-06
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 74 (type EQUN) for 55 FireWire-PT-06-CTLFireability-2024-13
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 75 (type FNDP) for 27 FireWire-PT-06-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 76 (type EQUN) for 27 FireWire-PT-06-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 74 (type EQUN) for FireWire-PT-06-CTLFireability-2024-13
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] FINISHED task # 76 (type EQUN) for FireWire-PT-06-CTLFireability-2024-05
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] LAUNCH task # 78 (type FNDP) for 49 FireWire-PT-06-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 79 (type EQUN) for 49 FireWire-PT-06-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 78 (type FNDP) for FireWire-PT-06-CTLFireability-2024-11
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 10
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 79 (type EQUN) for FireWire-PT-06-CTLFireability-2024-11 (obsolete)
[[35mlola[0m][I] FINISHED task # 79 (type EQUN) for FireWire-PT-06-CTLFireability-2024-11
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] FINISHED task # 75 (type FNDP) for FireWire-PT-06-CTLFireability-2024-05
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 19998
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] FINISHED task # 1 (type EXCL) for FireWire-PT-06-CTLFireability-2024-00
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 632763
[[35mlola[0m][I] fired transitions : 3968246
[[35mlola[0m][I] time used : 5
[[35mlola[0m][I] memory pages used : 3
[[35mlola[0m][I] LAUNCH task # 70 (type EXCL) for 55 FireWire-PT-06-CTLFireability-2024-13
[[35mlola[0m][I] time limit : 239 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 70 (type EXCL) for FireWire-PT-06-CTLFireability-2024-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 325
[[35mlola[0m][I] fired transitions : 620
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 62 (type EXCL) for 61 FireWire-PT-06-CTLFireability-2024-15
[[35mlola[0m][I] time limit : 256 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-06-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-06-CTLFireability-2024-05: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-06-CTLFireability-2024-06: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-06-CTLFireability-2024-11: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-06-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-06-CTLFireability-2024-01: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] FireWire-PT-06-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-06-CTLFireability-2024-04: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-06-CTLFireability-2024-10: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FireWire-PT-06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-06-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 CTL EXCL 0/256 1/2000 FireWire-PT-06-CTLFireability-2024-15 66580 m, 13316 m/sec, 271075 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-06-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-06-CTLFireability-2024-05: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-06-CTLFireability-2024-06: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-06-CTLFireability-2024-11: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-06-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-06-CTLFireability-2024-01: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] FireWire-PT-06-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-06-CTLFireability-2024-04: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-06-CTLFireability-2024-10: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FireWire-PT-06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-06-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 CTL EXCL 5/256 3/2000 FireWire-PT-06-CTLFireability-2024-15 548000 m, 96284 m/sec, 5793993 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-06-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-06-CTLFireability-2024-05: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-06-CTLFireability-2024-06: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-06-CTLFireability-2024-11: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-06-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-06-CTLFireability-2024-01: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] FireWire-PT-06-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-06-CTLFireability-2024-04: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-06-CTLFireability-2024-10: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FireWire-PT-06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-06-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
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[[35mlola[0m][.] FireWire-PT-06-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-06-CTLFireability-2024-04: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] FireWire-PT-06-CTLFireability-2024-10: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FireWire-PT-06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-06-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
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[[35mlola[0m][.] 62 CTL EXCL 60/256 23/2000 FireWire-PT-06-CTLFireability-2024-15 5375616 m, 105615 m/sec, 66336922 t fired, .
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[[35mlola[0m][I] FINISHED task # 62 (type EXCL) for FireWire-PT-06-CTLFireability-2024-15
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 5681364
[[35mlola[0m][I] fired transitions : 70142677
[[35mlola[0m][I] time used : 64
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[[35mlola[0m][I] LAUNCH task # 45 (type EXCL) for 42 FireWire-PT-06-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 271 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 45 (type EXCL) for FireWire-PT-06-CTLFireability-2024-10
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 3710
[[35mlola[0m][I] fired transitions : 12503
[[35mlola[0m][I] time used : 0
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[[35mlola[0m][I] LAUNCH task # 40 (type EXCL) for 39 FireWire-PT-06-CTLFireability-2024-09
[[35mlola[0m][I] time limit : 321 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 40 (type EXCL) for FireWire-PT-06-CTLFireability-2024-09
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 59
[[35mlola[0m][I] fired transitions : 114
[[35mlola[0m][I] time used : 0
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[[35mlola[0m][I] LAUNCH task # 37 (type EXCL) for 36 FireWire-PT-06-CTLFireability-2024-08
[[35mlola[0m][I] time limit : 353 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 37 (type EXCL) for FireWire-PT-06-CTLFireability-2024-08
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 3008
[[35mlola[0m][I] fired transitions : 10711
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 34 (type EXCL) for 33 FireWire-PT-06-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 392 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-06-CTLFireability-2024-00: CTL true CTL model checker[0m
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[[35mlola[0m][.] FireWire-PT-06-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-06-CTLFireability-2024-04: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-06-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 34 CTL EXCL 1/392 2/2000 FireWire-PT-06-CTLFireability-2024-07 364820 m, 72964 m/sec, 1662618 t fired, .
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[[35mlola[0m][I] FINISHED task # 34 (type EXCL) for FireWire-PT-06-CTLFireability-2024-07
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 512527
[[35mlola[0m][I] fired transitions : 2411232
[[35mlola[0m][I] time used : 2
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[[35mlola[0m][I] LAUNCH task # 16 (type EXCL) for 3 FireWire-PT-06-CTLFireability-2024-01
[[35mlola[0m][I] time limit : 441 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 16 (type EXCL) for FireWire-PT-06-CTLFireability-2024-01
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 57
[[35mlola[0m][I] fired transitions : 94
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 14 (type EXCL) for 3 FireWire-PT-06-CTLFireability-2024-01
[[35mlola[0m][I] time limit : 504 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 14 (type EXCL) for FireWire-PT-06-CTLFireability-2024-01
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] fired transitions : 1
[[35mlola[0m][I] time used : 0
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[[35mlola[0m][I] LAUNCH task # 72 (type EXCL) for 24 FireWire-PT-06-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 882 sec
[[35mlola[0m][I] memory limit: 2000 pages
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[[35mlola[0m][.] FireWire-PT-06-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-06-CTLFireability-2024-04: SP ECTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 72 LTL EXCL 4/882 2/2000 FireWire-PT-06-CTLFireability-2024-04 294031 m, 58806 m/sec, 1247085 t fired, .
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[[35mlola[0m][.] FireWire-PT-06-CTLFireability-2024-04: SP ECTL 0 0 1 0 1 0 0 0
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[[35mlola[0m][.] 72 LTL EXCL 9/882 5/2000 FireWire-PT-06-CTLFireability-2024-04 628776 m, 66949 m/sec, 2646996 t fired, .
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[[35mlola[0m][.] [1m[32mFireWire-PT-06-CTLFireability-2024-13: EXEF true state space /EXEF[0m
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[[35mlola[0m][.] FireWire-PT-06-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-06-CTLFireability-2024-04: SP ECTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 72 LTL EXCL 14/882 7/2000 FireWire-PT-06-CTLFireability-2024-04 973758 m, 68996 m/sec, 4004751 t fired, .
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[[35mlola[0m][.] FireWire-PT-06-CTLFireability-2024-04: SP ECTL 0 0 1 0 1 0 0 0
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[[35mlola[0m][.] 72 LTL EXCL 19/882 9/2000 FireWire-PT-06-CTLFireability-2024-04 1312315 m, 67711 m/sec, 5348709 t fired, .
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[[35mlola[0m][.] FireWire-PT-06-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-06-CTLFireability-2024-04: SP ECTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 72 LTL EXCL 24/882 11/2000 FireWire-PT-06-CTLFireability-2024-04 1643641 m, 66265 m/sec, 6607674 t fired, .
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[[35mlola[0m][.] FireWire-PT-06-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-06-CTLFireability-2024-04: SP ECTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
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[[35mlola[0m][.] 72 LTL EXCL 29/882 13/2000 FireWire-PT-06-CTLFireability-2024-04 1949904 m, 61252 m/sec, 7868798 t fired, .
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[[35mlola[0m][.] FireWire-PT-06-CTLFireability-2024-04: SP ECTL 0 0 1 0 1 0 0 0
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[[35mlola[0m][.] 72 LTL EXCL 34/882 16/2000 FireWire-PT-06-CTLFireability-2024-04 2291160 m, 68251 m/sec, 9171954 t fired, .
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[[35mlola[0m][.] FireWire-PT-06-CTLFireability-2024-04: SP ECTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 72 LTL EXCL 39/882 18/2000 FireWire-PT-06-CTLFireability-2024-04 2617793 m, 65326 m/sec, 10424231 t fired, .
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[[35mlola[0m][I] FINISHED task # 72 (type EXCL) for FireWire-PT-06-CTLFireability-2024-04
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 2930805
[[35mlola[0m][I] fired transitions : 11643447
[[35mlola[0m][I] time used : 44
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[[35mlola[0m][I] LAUNCH task # 59 (type EXCL) for 58 FireWire-PT-06-CTLFireability-2024-14
[[35mlola[0m][I] time limit : 1161 sec
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[[35mlola[0m][I] FINISHED task # 59 (type EXCL) for FireWire-PT-06-CTLFireability-2024-14
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 244
[[35mlola[0m][I] fired transitions : 419
[[35mlola[0m][I] time used : 0
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[[35mlola[0m][I] LAUNCH task # 53 (type EXCL) for 52 FireWire-PT-06-CTLFireability-2024-12
[[35mlola[0m][I] time limit : 1742 sec
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[[35mlola[0m][I] FINISHED task # 53 (type EXCL) for FireWire-PT-06-CTLFireability-2024-12
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 74
[[35mlola[0m][I] fired transitions : 268
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[[35mlola[0m][I] LAUNCH task # 19 (type EXCL) for 18 FireWire-PT-06-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 3485 sec
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[[35mlola[0m][.] 19 CTL EXCL 0/3485 1/2000 FireWire-PT-06-CTLFireability-2024-02 55245 m, 11049 m/sec, 378344 t fired, .
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[[35mlola[0m][.] 19 CTL EXCL 5/3485 5/2000 FireWire-PT-06-CTLFireability-2024-02 937071 m, 176365 m/sec, 6968451 t fired, .
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[[35mlola[0m][.] 19 CTL EXCL 10/3485 8/2000 FireWire-PT-06-CTLFireability-2024-02 1777323 m, 168050 m/sec, 13037688 t fired, .
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[[35mlola[0m][.] 19 CTL EXCL 15/3485 11/2000 FireWire-PT-06-CTLFireability-2024-02 2544838 m, 153503 m/sec, 18630033 t fired, .
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[[35mlola[0m][.] 19 CTL EXCL 20/3485 15/2000 FireWire-PT-06-CTLFireability-2024-02 3417684 m, 174569 m/sec, 24780696 t fired, .
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[[35mlola[0m][.] [1m[31mFireWire-PT-06-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-06-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-06-CTLFireability-2024-10: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-06-CTLFireability-2024-11: EF true findpath[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-06-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-06-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-06-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-06-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-06-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 25/3485 19/2000 FireWire-PT-06-CTLFireability-2024-02 4276044 m, 171672 m/sec, 30588209 t fired, .
[[35mlola[0m][.]
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[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 19 (type EXCL) for FireWire-PT-06-CTLFireability-2024-02
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 4450213
[[35mlola[0m][I] fired transitions : 31869603
[[35mlola[0m][I] time used : 27
[[35mlola[0m][I] memory pages used : 20
[[35mlola[0m][I] Portfolio finished: no open formulas
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="FireWire-PT-06"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is FireWire-PT-06, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r551-tall-171734899600210"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/FireWire-PT-06.tgz
mv FireWire-PT-06 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;