About the Execution of LoLA for FireWire-PT-03
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 1930.359 | 237646.00 | 337595.00 | 673.20 | FFTFFFTTFFFFTFFF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r551-tall-171734899500186.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is FireWire-PT-03, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r551-tall-171734899500186
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 564K
-rw-r--r-- 1 mcc users 6.9K Jun 2 17:16 CTLCardinality.txt
-rw-r--r-- 1 mcc users 79K Jun 2 17:16 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.3K Jun 2 17:16 CTLFireability.txt
-rw-r--r-- 1 mcc users 48K Jun 2 17:16 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.5K Jun 2 17:12 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Jun 2 17:12 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Jun 2 17:12 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Jun 2 17:12 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 Jun 2 16:33 NewModel
-rw-r--r-- 1 mcc users 13K Jun 2 17:16 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 141K Jun 2 17:16 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.8K Jun 2 17:16 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 78K Jun 2 17:16 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Jun 2 17:12 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Jun 2 17:12 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Jun 2 16:33 equiv_col
-rw-r--r-- 1 mcc users 3 Jun 2 16:33 instance
-rw-r--r-- 1 mcc users 6 Jun 2 16:33 iscolored
-rw-r--r-- 1 mcc users 86K Jun 2 16:33 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME FireWire-PT-03-CTLFireability-2024-00
FORMULA_NAME FireWire-PT-03-CTLFireability-2024-01
FORMULA_NAME FireWire-PT-03-CTLFireability-2024-02
FORMULA_NAME FireWire-PT-03-CTLFireability-2024-03
FORMULA_NAME FireWire-PT-03-CTLFireability-2024-04
FORMULA_NAME FireWire-PT-03-CTLFireability-2024-05
FORMULA_NAME FireWire-PT-03-CTLFireability-2024-06
FORMULA_NAME FireWire-PT-03-CTLFireability-2024-07
FORMULA_NAME FireWire-PT-03-CTLFireability-2024-08
FORMULA_NAME FireWire-PT-03-CTLFireability-2024-09
FORMULA_NAME FireWire-PT-03-CTLFireability-2024-10
FORMULA_NAME FireWire-PT-03-CTLFireability-2024-11
FORMULA_NAME FireWire-PT-03-CTLFireability-2024-12
FORMULA_NAME FireWire-PT-03-CTLFireability-2024-13
FORMULA_NAME FireWire-PT-03-CTLFireability-2024-14
FORMULA_NAME FireWire-PT-03-CTLFireability-2024-15
=== Now, execution of the tool begins
BK_START 1717414919216
starting LoLA
BK_EXAMINATION: CTLFireability
BK_TIME_CONFINEMENT: 3600
BK_MEMORY_CONFINEMENT: 16384
BK_BIN_PATH: /home/mcc/BenchKit/bin/
current directory: /home/mcc/execution
FORMULA FireWire-PT-03-CTLFireability-2024-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-03-CTLFireability-2024-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-03-CTLFireability-2024-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-03-CTLFireability-2024-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-03-CTLFireability-2024-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-03-CTLFireability-2024-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-03-CTLFireability-2024-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-03-CTLFireability-2024-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-03-CTLFireability-2024-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-03-CTLFireability-2024-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-03-CTLFireability-2024-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-03-CTLFireability-2024-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-03-CTLFireability-2024-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-03-CTLFireability-2024-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-03-CTLFireability-2024-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FireWire-PT-03-CTLFireability-2024-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[[35mlola[0m] [1mFINAL RESULTS[0m
[[35mlola[0m] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m] [1m[31mFireWire-PT-03-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mFireWire-PT-03-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mFireWire-PT-03-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m] [1m[31mFireWire-PT-03-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mFireWire-PT-03-CTLFireability-2024-04: DISJ false DISJ[0m
[[35mlola[0m] [1m[31mFireWire-PT-03-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mFireWire-PT-03-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mFireWire-PT-03-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mFireWire-PT-03-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mFireWire-PT-03-CTLFireability-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m] [1m[31mFireWire-PT-03-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mFireWire-PT-03-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mFireWire-PT-03-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mFireWire-PT-03-CTLFireability-2024-13: CONJ false CTL model checker[0m
[[35mlola[0m] [1m[31mFireWire-PT-03-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mFireWire-PT-03-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m]
[[35mlola[0m] Time elapsed: 237 secs. Pages in use: 27
BK_STOP 1717415156862
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 48 (type CNST) for 47 FireWire-PT-03-CTLFireability-2024-09
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 48 (type CNST) for FireWire-PT-03-CTLFireability-2024-09
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 4 (type EXCL) for 3 FireWire-PT-03-CTLFireability-2024-01
[[35mlola[0m][I] time limit : 156 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 72 (type FNDP) for 6 FireWire-PT-03-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 73 (type EQUN) for 6 FireWire-PT-03-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 77 (type FNDP) for 12 FireWire-PT-03-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 73 (type EQUN) for FireWire-PT-03-CTLFireability-2024-02
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] LAUNCH task # 76 (type FNDP) for 59 FireWire-PT-03-CTLFireability-2024-13
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 77 (type FNDP) for FireWire-PT-03-CTLFireability-2024-04
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] LAUNCH task # 89 (type EQUN) for 12 FireWire-PT-03-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 89 (type EQUN) for FireWire-PT-03-CTLFireability-2024-04
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] LAUNCH task # 96 (type EQUN) for 12 FireWire-PT-03-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 96 (type EQUN) for FireWire-PT-03-CTLFireability-2024-04
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] LAUNCH task # 79 (type EQUN) for 59 FireWire-PT-03-CTLFireability-2024-13
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 79 (type EQUN) for FireWire-PT-03-CTLFireability-2024-13
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] FINISHED task # 72 (type FNDP) for FireWire-PT-03-CTLFireability-2024-02
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1736
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-03-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-03-CTLFireability-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-04: DISJ 0 2 0 0 9 0 0 10
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-13: CONJ 0 2 1 0 3 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 5/225 3/2000 FireWire-PT-03-CTLFireability-2024-01 474726 m, 94945 m/sec, 5422069 t fired, .
[[35mlola[0m][.] 76 EF FNDP 5/3600 0/5 FireWire-PT-03-CTLFireability-2024-13 17900 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-03-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-03-CTLFireability-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-04: DISJ 0 2 0 0 9 0 0 10
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-13: CONJ 0 2 1 0 3 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 10/225 5/2000 FireWire-PT-03-CTLFireability-2024-01 937922 m, 92639 m/sec, 10713492 t fired, .
[[35mlola[0m][.] 76 EF FNDP 10/3600 0/5 FireWire-PT-03-CTLFireability-2024-13 35526 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs. Pages in use: 5
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-03-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-03-CTLFireability-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-04: DISJ 0 2 0 0 9 0 0 10
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-13: CONJ 0 2 1 0 3 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 15/225 7/2000 FireWire-PT-03-CTLFireability-2024-01 1448288 m, 102073 m/sec, 15773783 t fired, .
[[35mlola[0m][.] 76 EF FNDP 15/3600 0/5 FireWire-PT-03-CTLFireability-2024-13 52847 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 15 secs. Pages in use: 7
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-03-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-03-CTLFireability-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-04: DISJ 0 2 0 0 9 0 0 10
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 76 EF FNDP 20/3600 0/5 FireWire-PT-03-CTLFireability-2024-13 69867 attempts, .
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[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 65/225 25/2000 FireWire-PT-03-CTLFireability-2024-01 5631197 m, 73711 m/sec, 61582776 t fired, .
[[35mlola[0m][.] 76 EF FNDP 65/3600 0/5 FireWire-PT-03-CTLFireability-2024-13 220450 attempts, .
[[35mlola[0m][.]
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[[35mlola[0m][.]
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[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
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[[35mlola[0m][.] 4 CTL EXCL 70/225 26/2000 FireWire-PT-03-CTLFireability-2024-01 5943212 m, 62403 m/sec, 65610902 t fired, .
[[35mlola[0m][.] 76 EF FNDP 70/3600 0/5 FireWire-PT-03-CTLFireability-2024-13 237141 attempts, .
[[35mlola[0m][.]
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[[35mlola[0m][I] FINISHED task # 4 (type EXCL) for FireWire-PT-03-CTLFireability-2024-01
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 6204206
[[35mlola[0m][I] fired transitions : 69100070
[[35mlola[0m][I] time used : 74
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[[35mlola[0m][I] LAUNCH task # 70 (type EXCL) for 69 FireWire-PT-03-CTLFireability-2024-15
[[35mlola[0m][I] time limit : 235 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 70 (type EXCL) for FireWire-PT-03-CTLFireability-2024-15
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 476
[[35mlola[0m][I] fired transitions : 3950
[[35mlola[0m][I] time used : 0
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[[35mlola[0m][I] LAUNCH task # 67 (type EXCL) for 66 FireWire-PT-03-CTLFireability-2024-14
[[35mlola[0m][I] time limit : 251 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
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[[35mlola[0m][.]
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[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-04: DISJ 0 2 0 0 9 0 0 10
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[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-13: CONJ 0 2 1 0 3 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 67 CTL EXCL 1/251 2/2000 FireWire-PT-03-CTLFireability-2024-14 313624 m, 62724 m/sec, 1245583 t fired, .
[[35mlola[0m][.] 76 EF FNDP 75/3600 0/5 FireWire-PT-03-CTLFireability-2024-13 253725 attempts, .
[[35mlola[0m][.]
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[[35mlola[0m][.] [1m[31mFireWire-PT-03-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-03-CTLFireability-2024-02: EF true findpath[0m
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[[35mlola[0m][.] [1m[31mFireWire-PT-03-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
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[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-04: DISJ 0 2 0 0 9 0 0 10
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-13: CONJ 0 2 1 0 3 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 67 CTL EXCL 6/251 7/2000 FireWire-PT-03-CTLFireability-2024-14 1565011 m, 250277 m/sec, 6917628 t fired, .
[[35mlola[0m][.] 76 EF FNDP 80/3600 0/5 FireWire-PT-03-CTLFireability-2024-13 270062 attempts, .
[[35mlola[0m][.]
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[[35mlola[0m][.] [1m[31mFireWire-PT-03-CTLFireability-2024-01: CTL false CTL model checker[0m
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[[35mlola[0m][.]
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[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-04: DISJ 0 2 0 0 9 0 0 10
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-13: CONJ 0 2 1 0 3 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 67 CTL EXCL 11/251 12/2000 FireWire-PT-03-CTLFireability-2024-14 2622061 m, 211410 m/sec, 12122211 t fired, .
[[35mlola[0m][.] 76 EF FNDP 85/3600 0/5 FireWire-PT-03-CTLFireability-2024-13 286570 attempts, .
[[35mlola[0m][.]
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[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-03-CTLFireability-2024-01: CTL false CTL model checker[0m
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[[35mlola[0m][.]
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[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-13: CONJ 0 2 1 0 3 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 67 CTL EXCL 16/251 15/2000 FireWire-PT-03-CTLFireability-2024-14 3465556 m, 168699 m/sec, 17041924 t fired, .
[[35mlola[0m][.] 76 EF FNDP 90/3600 0/5 FireWire-PT-03-CTLFireability-2024-13 303243 attempts, .
[[35mlola[0m][.]
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[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-03-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-03-CTLFireability-2024-02: EF true findpath[0m
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[[35mlola[0m][.]
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[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-04: DISJ 0 2 0 0 9 0 0 10
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-13: CONJ 0 2 1 0 3 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 67 CTL EXCL 21/251 20/2000 FireWire-PT-03-CTLFireability-2024-14 4423421 m, 191573 m/sec, 21371604 t fired, .
[[35mlola[0m][.] 76 EF FNDP 95/3600 0/5 FireWire-PT-03-CTLFireability-2024-13 319604 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 95 secs. Pages in use: 27
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[[35mlola[0m][I] FINISHED task # 76 (type FNDP) for FireWire-PT-03-CTLFireability-2024-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 322447
[[35mlola[0m][I] time used : 96
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFireWire-PT-03-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFireWire-PT-03-CTLFireability-2024-02: EF true findpath[0m
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[[35mlola[0m][.]
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[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-04: DISJ 0 2 0 0 9 0 0 10
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[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-13: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 67 CTL EXCL 26/271 22/2000 FireWire-PT-03-CTLFireability-2024-14 5039055 m, 123126 m/sec, 25618178 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 100 secs. Pages in use: 27
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 67 (type EXCL) for FireWire-PT-03-CTLFireability-2024-14
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 5134801
[[35mlola[0m][I] fired transitions : 26130587
[[35mlola[0m][I] time used : 27
[[35mlola[0m][I] memory pages used : 23
[[35mlola[0m][I] LAUNCH task # 64 (type EXCL) for 59 FireWire-PT-03-CTLFireability-2024-13
[[35mlola[0m][I] time limit : 291 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 64 (type EXCL) for FireWire-PT-03-CTLFireability-2024-13
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 734
[[35mlola[0m][I] fired transitions : 1373
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 57 (type EXCL) for 56 FireWire-PT-03-CTLFireability-2024-12
[[35mlola[0m][I] time limit : 318 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 57 (type EXCL) for FireWire-PT-03-CTLFireability-2024-12
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 57169
[[35mlola[0m][I] fired transitions : 237588
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 54 (type EXCL) for 53 FireWire-PT-03-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 349 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 54 (type EXCL) for FireWire-PT-03-CTLFireability-2024-11
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 58
[[35mlola[0m][I] fired transitions : 151
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 51 (type EXCL) for 50 FireWire-PT-03-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 388 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 51 (type EXCL) for FireWire-PT-03-CTLFireability-2024-10
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 67319
[[35mlola[0m][I] fired transitions : 268863
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 45 (type EXCL) for 44 FireWire-PT-03-CTLFireability-2024-08
[[35mlola[0m][I] time limit : 437 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 45 (type EXCL) for FireWire-PT-03-CTLFireability-2024-08
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 4
[[35mlola[0m][I] fired transitions : 9
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 42 (type EXCL) for 41 FireWire-PT-03-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 499 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 42 (type EXCL) for FireWire-PT-03-CTLFireability-2024-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1870
[[35mlola[0m][I] fired transitions : 4844
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 39 (type EXCL) for 38 FireWire-PT-03-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 583 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 39 (type EXCL) for FireWire-PT-03-CTLFireability-2024-06
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 55884
[[35mlola[0m][I] fired transitions : 233886
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 36 (type EXCL) for 35 FireWire-PT-03-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 699 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
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[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-04: DISJ 0 2 0 0 9 0 0 10
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 4/699 3/2000 FireWire-PT-03-CTLFireability-2024-05 583247 m, 116649 m/sec, 5127498 t fired, .
[[35mlola[0m][.]
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[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
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[[35mlola[0m][.] 36 CTL EXCL 9/699 6/2000 FireWire-PT-03-CTLFireability-2024-05 1293270 m, 142004 m/sec, 11465061 t fired, .
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[[35mlola[0m][.]
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[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-04: DISJ 0 2 0 0 9 0 0 10
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 14/699 9/2000 FireWire-PT-03-CTLFireability-2024-05 1913017 m, 123949 m/sec, 17365608 t fired, .
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[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-04: DISJ 0 2 0 0 9 0 0 10
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 19/699 11/2000 FireWire-PT-03-CTLFireability-2024-05 2437472 m, 104891 m/sec, 22500047 t fired, .
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[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-04: DISJ 0 2 0 0 9 0 0 10
[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
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[[35mlola[0m][.] 36 CTL EXCL 24/699 13/2000 FireWire-PT-03-CTLFireability-2024-05 2906452 m, 93796 m/sec, 27591954 t fired, .
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[[35mlola[0m][.] FireWire-PT-03-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 36 CTL EXCL 29/699 16/2000 FireWire-PT-03-CTLFireability-2024-05 3492009 m, 117111 m/sec, 32776536 t fired, .
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[[35mlola[0m][.] 36 CTL EXCL 34/699 18/2000 FireWire-PT-03-CTLFireability-2024-05 3996293 m, 100856 m/sec, 37757386 t fired, .
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[[35mlola[0m][.] 36 CTL EXCL 39/699 20/2000 FireWire-PT-03-CTLFireability-2024-05 4457014 m, 92144 m/sec, 42689616 t fired, .
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[[35mlola[0m][.] 36 CTL EXCL 49/699 24/2000 FireWire-PT-03-CTLFireability-2024-05 5400350 m, 104160 m/sec, 52808855 t fired, .
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[[35mlola[0m][.] 36 CTL EXCL 54/699 25/2000 FireWire-PT-03-CTLFireability-2024-05 5812669 m, 82463 m/sec, 57595189 t fired, .
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[[35mlola[0m][.] 36 CTL EXCL 59/699 27/2000 FireWire-PT-03-CTLFireability-2024-05 6196198 m, 76705 m/sec, 62783767 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 5/1146 3/2000 FireWire-PT-03-CTLFireability-2024-00 668324 m, 133664 m/sec, 5002159 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 15/1146 9/2000 FireWire-PT-03-CTLFireability-2024-00 1898591 m, 117523 m/sec, 14715561 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 20/1146 11/2000 FireWire-PT-03-CTLFireability-2024-00 2433519 m, 106985 m/sec, 19262032 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 40/1146 20/2000 FireWire-PT-03-CTLFireability-2024-00 4490015 m, 93446 m/sec, 37058271 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 45/1146 22/2000 FireWire-PT-03-CTLFireability-2024-00 4892021 m, 80401 m/sec, 41131684 t fired, .
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[[35mlola[0m][.] 85 AGEF EXCL 4/1689 5/2000 FireWire-PT-03-CTLFireability-2024-04 1182742 m, 236548 m/sec, 5283532 t fired, .
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[[35mlola[0m][.] 85 AGEF EXCL 9/1689 9/2000 FireWire-PT-03-CTLFireability-2024-04 2218128 m, 207077 m/sec, 11101340 t fired, .
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[[35mlola[0m][.] 85 AGEF EXCL 14/1689 13/2000 FireWire-PT-03-CTLFireability-2024-04 3164149 m, 189204 m/sec, 16344143 t fired, .
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[[35mlola[0m][I] LAUNCH task # 10 (type EXCL) for 9 FireWire-PT-03-CTLFireability-2024-03
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[[35mlola[0m][I] FINISHED task # 10 (type EXCL) for FireWire-PT-03-CTLFireability-2024-03
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[[35mlola[0m][I] Portfolio finished: no open formulas
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="FireWire-PT-03"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is FireWire-PT-03, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r551-tall-171734899500186"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/FireWire-PT-03.tgz
mv FireWire-PT-03 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;