About the Execution of LoLA for CO4-PT-18
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 5477.867 | 3600000.00 | 917786.00 | 9940.80 | [undef] | Time out reached |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r551-tall-171734899400140.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is CO4-PT-18, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r551-tall-171734899400140
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 732K
-rw-r--r-- 1 mcc users 5.7K Jun 2 17:16 CTLCardinality.txt
-rw-r--r-- 1 mcc users 58K Jun 2 17:16 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.4K Jun 2 17:16 CTLFireability.txt
-rw-r--r-- 1 mcc users 63K Jun 2 17:16 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.6K Jun 2 17:12 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Jun 2 17:12 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.0K Jun 2 17:12 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Jun 2 17:12 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 Jun 2 16:33 NewModel
-rw-r--r-- 1 mcc users 14K Jun 2 17:16 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 157K Jun 2 17:16 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.2K Jun 2 17:16 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 81K Jun 2 17:16 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.5K Jun 2 17:12 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.5K Jun 2 17:12 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Jun 2 16:33 equiv_col
-rw-r--r-- 1 mcc users 3 Jun 2 16:33 instance
-rw-r--r-- 1 mcc users 6 Jun 2 16:33 iscolored
-rw-r--r-- 1 mcc users 239K Jun 2 16:33 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME CO4-PT-18-LTLFireability-00
FORMULA_NAME CO4-PT-18-LTLFireability-01
FORMULA_NAME CO4-PT-18-LTLFireability-02
FORMULA_NAME CO4-PT-18-LTLFireability-03
FORMULA_NAME CO4-PT-18-LTLFireability-04
FORMULA_NAME CO4-PT-18-LTLFireability-05
FORMULA_NAME CO4-PT-18-LTLFireability-06
FORMULA_NAME CO4-PT-18-LTLFireability-07
FORMULA_NAME CO4-PT-18-LTLFireability-08
FORMULA_NAME CO4-PT-18-LTLFireability-09
FORMULA_NAME CO4-PT-18-LTLFireability-10
FORMULA_NAME CO4-PT-18-LTLFireability-11
FORMULA_NAME CO4-PT-18-LTLFireability-12
FORMULA_NAME CO4-PT-18-LTLFireability-13
FORMULA_NAME CO4-PT-18-LTLFireability-14
FORMULA_NAME CO4-PT-18-LTLFireability-15
=== Now, execution of the tool begins
BK_START 1717408294111
BK_TIME_CONFINEMENT_REACHED
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mLTLFireability.xml[0m
[[35mlola[0m][I] LAUNCH task # 34 (type CNST) for 31 CO4-PT-18-LTLFireability-09
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 34 (type CNST) for CO4-PT-18-LTLFireability-09
[[35mlola[0m][I] result : false
[[35mlola[0m][I] Rule S: 177 transitions removed,157 places removed
[*** LOG ERROR #0001 ***] [2024-06-03 09:51:35] [status_logger] string pointer is null
[[35mlola[0m][I] LAUNCH task # 54 (type EXCL) for 53 CO4-PT-18-LTLFireability-15
[[35mlola[0m][I] time limit : 224 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 54 (type EXCL) for CO4-PT-18-LTLFireability-15
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 2
[[35mlola[0m][I] fired transitions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 48 (type EXCL) for 47 CO4-PT-18-LTLFireability-13
[[35mlola[0m][I] time limit : 239 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 48 (type EXCL) for CO4-PT-18-LTLFireability-13
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 35
[[35mlola[0m][I] fired transitions : 35
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 3 (type EXCL) for 0 CO4-PT-18-LTLFireability-00
[[35mlola[0m][I] time limit : 257 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 3 (type EXCL) for CO4-PT-18-LTLFireability-00
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 2
[[35mlola[0m][I] fired transitions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 26 (type EXCL) for 25 CO4-PT-18-LTLFireability-07
[[35mlola[0m][I] time limit : 276 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 26 (type EXCL) for CO4-PT-18-LTLFireability-07
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 35
[[35mlola[0m][I] fired transitions : 35
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 17 (type EXCL) for 16 CO4-PT-18-LTLFireability-04
[[35mlola[0m][I] time limit : 299 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-18-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-18-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mCO4-PT-18-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-18-LTLFireability-15: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-18-LTLFireability-00: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] CO4-PT-18-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-18-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-18-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-18-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-18-LTLFireability-05: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-18-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-18-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-18-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-18-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-18-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-18-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 5/299 3/2000 CO4-PT-18-LTLFireability-04 402981 m, 80596 m/sec, 1391464 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 6 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-18-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-18-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mCO4-PT-18-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-18-LTLFireability-15: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-18-LTLFireability-00: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] CO4-PT-18-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-18-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-18-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-18-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-18-LTLFireability-05: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-18-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-18-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-18-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-18-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-18-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-18-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 10/299 6/2000 CO4-PT-18-LTLFireability-04 789133 m, 77230 m/sec, 3022516 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 11 secs. Pages in use: 6
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 17 (type EXCL) for CO4-PT-18-LTLFireability-04
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 993684
[[35mlola[0m][I] fired transitions : 3987841
[[35mlola[0m][I] time used : 13
[[35mlola[0m][I] memory pages used : 7
[[35mlola[0m][I] LAUNCH task # 51 (type EXCL) for 50 CO4-PT-18-LTLFireability-14
[[35mlola[0m][I] time limit : 326 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 51 (type EXCL) for CO4-PT-18-LTLFireability-14
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 2
[[35mlola[0m][I] fired transitions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 45 (type EXCL) for 44 CO4-PT-18-LTLFireability-12
[[35mlola[0m][I] time limit : 358 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 45 (type EXCL) for CO4-PT-18-LTLFireability-12
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 67
[[35mlola[0m][I] fired transitions : 68
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 42 (type EXCL) for 41 CO4-PT-18-LTLFireability-11
[[35mlola[0m][I] time limit : 398 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-18-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-18-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-18-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mCO4-PT-18-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-18-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-18-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-18-LTLFireability-15: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-18-LTLFireability-00: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] CO4-PT-18-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-18-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-18-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-18-LTLFireability-05: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-18-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-18-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-18-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-18-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 42 LTL EXCL 2/398 2/2000 CO4-PT-18-LTLFireability-11 217368 m, 43473 m/sec, 677530 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 16 secs. Pages in use: 7
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-18-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-18-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-18-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mCO4-PT-18-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-18-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-18-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-18-LTLFireability-15: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-18-LTLFireability-00: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] CO4-PT-18-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-18-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-18-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-18-LTLFireability-05: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-18-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-18-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-18-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-18-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 42 LTL EXCL 7/398 5/2000 CO4-PT-18-LTLFireability-11 639085 m, 84343 m/sec, 2333047 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 21 secs. Pages in use: 7
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-18-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-18-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-18-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mCO4-PT-18-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-18-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-18-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-18-LTLFireability-15: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-18-LTLFireability-00: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] CO4-PT-18-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-18-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
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========== file over 1MB has been truncated ======
retrieve it from the run archives if needed
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="CO4-PT-18"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is CO4-PT-18, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r551-tall-171734899400140"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/CO4-PT-18.tgz
mv CO4-PT-18 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;