Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r551-tall-171734899400132.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is CO4-PT-17, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r551-tall-171734899400132
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 684K
-rw-r--r-- 1 mcc users 6.3K Jun 2 17:16 CTLCardinality.txt
-rw-r--r-- 1 mcc users 67K Jun 2 17:16 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.9K Jun 2 17:16 CTLFireability.txt
-rw-r--r-- 1 mcc users 56K Jun 2 17:16 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.5K Jun 2 17:12 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Jun 2 17:12 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Jun 2 17:12 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Jun 2 17:12 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 Jun 2 16:33 NewModel
-rw-r--r-- 1 mcc users 9.9K Jun 2 17:16 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 102K Jun 2 17:16 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.4K Jun 2 17:16 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 85K Jun 2 17:16 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.5K Jun 2 17:12 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.5K Jun 2 17:12 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Jun 2 16:33 equiv_col
-rw-r--r-- 1 mcc users 3 Jun 2 16:33 instance
-rw-r--r-- 1 mcc users 6 Jun 2 16:33 iscolored
-rw-r--r-- 1 mcc users 248K Jun 2 16:33 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME CO4-PT-17-LTLFireability-00
FORMULA_NAME CO4-PT-17-LTLFireability-01
FORMULA_NAME CO4-PT-17-LTLFireability-02
FORMULA_NAME CO4-PT-17-LTLFireability-03
FORMULA_NAME CO4-PT-17-LTLFireability-04
FORMULA_NAME CO4-PT-17-LTLFireability-05
FORMULA_NAME CO4-PT-17-LTLFireability-06
FORMULA_NAME CO4-PT-17-LTLFireability-07
FORMULA_NAME CO4-PT-17-LTLFireability-08
FORMULA_NAME CO4-PT-17-LTLFireability-09
FORMULA_NAME CO4-PT-17-LTLFireability-10
FORMULA_NAME CO4-PT-17-LTLFireability-11
FORMULA_NAME CO4-PT-17-LTLFireability-12
FORMULA_NAME CO4-PT-17-LTLFireability-13
FORMULA_NAME CO4-PT-17-LTLFireability-14
FORMULA_NAME CO4-PT-17-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1717406209269

FORMULA CO4-PT-17-LTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-17-LTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-17-LTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-17-LTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-17-LTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_TIME_CONFINEMENT_REACHED

--------------------
content from stderr:

[lola][I] LoLA will run for 3600 seconds at most (--timelimit)
[lola][W] unknown unit in memory specification: using default
[lola][I] MEM LIMIT 5
[lola][I] NET
[lola][I] reading net from model.pnml
[lola][I] input: PNML file (--pnmlnet)
[lola][I] reading pnml
[lola][I] PNML file contains place/transition net
[lola][I] closed net file model.pnml
[lola][I] finished parsing
[lola][I] Reading formula.
[lola][I] Using XML format (--xmlformula)
[lola][I] reading XML formula
[lola][I] reading formula from LTLFireability.xml
[lola][I] LAUNCH task # 4 (type CNST) for 3 CO4-PT-17-LTLFireability-01
[lola][I] time limit : 0 sec
[lola][I] memory limit: 0 pages
[lola][I] Rule S: 238 transitions removed,198 places removed
[lola][I] FINISHED task # 4 (type CNST) for CO4-PT-17-LTLFireability-01
[lola][I] result : false
[lola][I] LAUNCH task # 23 (type CNST) for 22 CO4-PT-17-LTLFireability-06
[lola][I] time limit : 0 sec
[lola][I] memory limit: 0 pages
[lola][I] LAUNCH task # 26 (type CNST) for 25 CO4-PT-17-LTLFireability-07
[lola][I] time limit : 0 sec
[lola][I] memory limit: 0 pages
[lola][I] LAUNCH task # 38 (type CNST) for 35 CO4-PT-17-LTLFireability-09
[lola][I] time limit : 0 sec
[lola][I] memory limit: 0 pages
[lola][I] LAUNCH task # 59 (type CNST) for 58 CO4-PT-17-LTLFireability-14
[lola][I] time limit : 0 sec
[lola][I] memory limit: 0 pages
[lola][I] FINISHED task # 23 (type CNST) for CO4-PT-17-LTLFireability-06
[lola][I] result : true
[lola][I] FINISHED task # 26 (type CNST) for CO4-PT-17-LTLFireability-07
[lola][I] result : true
[lola][I] FINISHED task # 38 (type CNST) for CO4-PT-17-LTLFireability-09
[lola][I] result : true
[lola][I] FINISHED task # 59 (type CNST) for CO4-PT-17-LTLFireability-14
[lola][I] result : false
[lola][I] LAUNCH task # 14 (type EXCL) for 9 CO4-PT-17-LTLFireability-03
[lola][I] time limit : 171 sec
[lola][I] memory limit: 2000 pages
[lola][I] LAUNCH task # 70 (type FNDP) for 28 CO4-PT-17-LTLFireability-08
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 71 (type EQUN) for 28 CO4-PT-17-LTLFireability-08
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 69 (type EQUN) for 35 CO4-PT-17-LTLFireability-09
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 70 (type FNDP) for CO4-PT-17-LTLFireability-08
[lola][I] result : true
[lola][I] tried executions : 1
[lola][I] time used : 0
[lola][I] memory pages used : 0
[lola][W] CANCELED task # 71 (type EQUN) for CO4-PT-17-LTLFireability-08 (obsolete)
[lola][I] FINISHED task # 71 (type EQUN) for CO4-PT-17-LTLFireability-08
[lola][I] result : true
[lola][I] FINISHED task # 69 (type EQUN) for CO4-PT-17-LTLFireability-09
[lola][I] result : true
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] CO4-PT-17-LTLFireability-01: INITIAL false preprocessing
[lola][.] CO4-PT-17-LTLFireability-06: INITIAL true preprocessing
[lola][.] CO4-PT-17-LTLFireability-07: INITIAL true preprocessing
[lola][.] CO4-PT-17-LTLFireability-08: CONJ false findpath
[lola][.] CO4-PT-17-LTLFireability-14: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] CO4-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-17-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-17-LTLFireability-03: CONJ 0 1 1 0 2 0 0 0
[lola][.] CO4-PT-17-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-17-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-17-LTLFireability-09: CONJ 0 2 0 0 3 0 0 0
[lola][.] CO4-PT-17-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-17-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-17-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-17-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 14 LTL EXCL 5/276 8/2000 CO4-PT-17-LTLFireability-03 1131396 m, 226279 m/sec, 2233508 t fired, .
[lola][.]
[lola][.] Time elapsed: 6 secs. Pages in use: 8
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I] FINISHED task # 14 (type EXCL) for CO4-PT-17-LTLFireability-03
[lola][I] result : false
[lola][I] markings : 1487876
[lola][I] fired transitions : 2957157
[lola][I] time used : 7
[lola][I] memory pages used : 10
[lola][I] LAUNCH task # 53 (type EXCL) for 52 CO4-PT-17-LTLFireability-12
[lola][I] time limit : 326 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 53 (type EXCL) for CO4-PT-17-LTLFireability-12
[lola][I] result : true
[lola][I] markings : 9
[lola][I] fired transitions : 9
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 50 (type EXCL) for 49 CO4-PT-17-LTLFireability-11
[lola][I] time limit : 359 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 50 (type EXCL) for CO4-PT-17-LTLFireability-11
[lola][I] result : true
[lola][I] markings : 1
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 47 (type EXCL) for 46 CO4-PT-17-LTLFireability-10
[lola][I] time limit : 399 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 47 (type EXCL) for CO4-PT-17-LTLFireability-10
[lola][I] result : true
[lola][I] markings : 10
[lola][I] fired transitions : 10
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 44 (type EXCL) for 35 CO4-PT-17-LTLFireability-09
[lola][I] time limit : 449 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 44 (type EXCL) for CO4-PT-17-LTLFireability-09
[lola][I] result : false
[lola][I] markings : 112461
[lola][I] fired transitions : 376030
[lola][I] time used : 1
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 20 (type EXCL) for 19 CO4-PT-17-LTLFireability-05
[lola][I] time limit : 598 sec
[lola][I] memory limit: 2000 pages
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] CO4-PT-17-LTLFireability-01: INITIAL false preprocessing
[lola][.] CO4-PT-17-LTLFireability-03: CONJ false LTL model checker
[lola][.] CO4-PT-17-LTLFireability-06: INITIAL true preprocessing
[lola][.] CO4-PT-17-LTLFireability-07: INITIAL true preprocessing
[lola][.] CO4-PT-17-LTLFireability-08: CONJ false findpath
[lola][.] CO4-PT-17-LTLFireability-09: CONJ false LTL model checker
[lola][.] CO4-PT-17-LTLFireability-10: LTL true LTL model checker
[lola][.] CO4-PT-17-LTLFireability-11: LTL true LTL model checker
[lola][.] CO4-PT-17-LTLFireability-12: LTL true LTL model checker
[lola][.] CO4-PT-17-LTLFireability-14: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] CO4-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-17-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-17-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-17-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[lola][.] CO4-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-17-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 20 LTL EXCL 2/598 2/2000 CO4-PT-17-LTLFireability-05 245818 m, 49163 m/sec, 888983 t fired, .
[lola][.]
[lola][.] Time elapsed: 11 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] CO4-PT-17-LTLFireability-01: INITIAL false preprocessing
[lola][.] CO4-PT-17-LTLFireability-03: CONJ false LTL model checker
[lola][.] CO4-PT-17-LTLFireability-06: INITIAL true preprocessing
[lola][.] CO4-PT-17-LTLFireability-07: INITIAL true preprocessing
[lola][.] CO4-PT-17-LTLFireability-08: CONJ false findpath
[lola][.] CO4-PT-17-LTLFireability-09: CONJ false LTL model checker
[lola][.] CO4-PT-17-LTLFireability-10: LTL true LTL model checker
[lola][.] CO4-PT-17-LTLFireability-11: LTL true LTL model checker
[lola][.] CO4-PT-17-LTLFireability-12: LTL true LTL model checker
[lola][.] CO4-PT-17-LTLFireability-14: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] CO4-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-17-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-17-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-17-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[lola][.] CO4-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-17-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 20 LTL EXCL 7/598 4/2000 CO4-PT-17-LTLFireability-05 595639 m, 69964 m/sec, 2667444 t fired, .
[lola][.]
[lola][.] Time elapsed: 16 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] CO4-PT-17-LTLFireability-01: INITIAL false preprocessing
[lola][.] CO4-PT-17-LTLFireability-03: CONJ false LTL model checker
[lola][.] CO4-PT-17-LTLFireability-06: INITIAL true preprocessing
[lola][.] CO4-PT-17-LTLFireability-07: INITIAL true preprocessing
[lola][.] CO4-PT-17-LTLFireability-08: CONJ false findpath
[lola][.] CO4-PT-17-LTLFireability-09: CONJ false LTL model checker
[lola][.] CO4-PT-17-LTLFireability-10: LTL true LTL model checker
[lola][.] CO4-PT-17-LTLFireability-11: LTL true LTL model checker
[lola][.] CO4-PT-17-LTLFireability-12: LTL true LTL model checker
[lola][.] CO4-PT-17-LTLFireability-14: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] CO4-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-17-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-17-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-17-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[lola][.] CO4-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-17-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 20 LTL EXCL 12/598 7/2000 CO4-PT-17-LTLFireability-05 919021 m, 64676 m/sec, 4400177 t fired, .
[lola][.]
[lola][.] Time elapsed: 21 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] CO4-PT-17-LTLFireability-01: INITIAL false preprocessing
[lola][.] CO4-PT-17-LTLFireability-03: CONJ false LTL model checker
[lola][.] CO4-PT-17-LTLFireability-06: INITIAL true preprocessing
[lola][.] CO4-PT-17-LTLFireability-07: INITIAL true preprocessing
[lola][.] CO4-PT-17-LTLFireability-08: CONJ false findpath
[lola][.] CO4-PT-17-LTLFireability-09: CONJ false LTL model checker
[lola][.] CO4-PT-17-LTLFireability-10: LTL true LTL model checker
[lola][.] CO4-PT-17-LTLFireability-11: LTL true LTL model checker
[lola][.] CO4-PT-17-LTLFireability-12: LTL true LTL model checker
[lola][.] CO4-PT-17-LTLFireability-14: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] CO4-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-17-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-17-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-17-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[lola][.] CO4-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-17-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 20 LTL EXCL 17/598 9/2000 CO4-PT-17-LTLFireability-05 1233249 m, 62845 m/sec, 6116701 t fired, .
[lola][.]
[lola][.] Time elapsed: 26 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] CO4-PT-17-LTLFireability-01: INITIAL false preprocessing
[lola][.] CO4-PT-17-LTLFireability-03: CONJ false LTL model checker
[lola][.] CO4-PT-17-LTLFireability-06: INITIAL true preprocessing
[lola][.] CO4-PT-17-LTLFireability-07: INITIAL true preprocessing
[lola][.] CO4-PT-17-LTLFireability-08: CONJ false findpath
[lola][.] CO4-PT-17-LTLFireability-09: CONJ false LTL model checker
[lola][.] CO4-PT-17-LTLFireability-10: LTL true LTL model checker
[lola][.] CO4-PT-17-LTLFireability-11: LTL true LTL model checker
[lola][.] CO4-PT-17-LTLFireability-12: LTL true LTL model checker
[lola][.] CO4-PT-17-LTLFireability-14: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] CO4-PT-17-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-17-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-17-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-17-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[lola][.] CO4-PT-17-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-17-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 20 LTL EXCL 22/598 10/2000 CO4-PT-17-LTLFireability-05 1486597 m, 50669 m/sec, 7831801 t fired, .
[lola][.]
[lola][.] Time elapsed: 31 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] CO4-PT-17-LTLFireability-01: INITIAL false preprocessing
[lola][.] CO4-PT-17-LTLFireability-03: CONJ false LTL model checker
[lola][.] CO4-PT-17-LTLFireability-06: INITIAL true preprocessing
[lola][.] CO4-PT-17-LTLFireability-07: INITIAL true preprocessing
[lola][.] CO4-PT-17-LTLFireability-08: CONJ false findpath
[lola][.] CO4-PT-17-LTLFireability-09: CONJ false LTL model checker
[lola][.] CO4-PT-17-LTLFireability-10: LTL true LTL model checker
[lola][.] CO4-PT-17-LTLFireability-11: LTL true LTL model checker
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[lola][.] 20 LTL EXCL 27/598 12/2000 CO4-PT-17-LTLFireability-05 1759886 m, 54657 m/sec, 9554617 t fired, .
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[lola][.] 20 LTL EXCL 32/598 14/2000 CO4-PT-17-LTLFireability-05 2081865 m, 64395 m/sec, 11282299 t fired, .
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[lola][.] 20 LTL EXCL 37/598 16/2000 CO4-PT-17-LTLFireability-05 2338528 m, 51332 m/sec, 13003568 t fired, .
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[lola][.] 20 LTL EXCL 42/598 18/2000 CO4-PT-17-LTLFireability-05 2616846 m, 55663 m/sec, 14752670 t fired, .
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[lola][.] 20 LTL EXCL 87/598 42/2000 CO4-PT-17-LTLFireability-05 6013550 m, 75035 m/sec, 28822435 t fired, .
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[lola][.] 7 LTL EXCL 119/875 54/2000 CO4-PT-17-LTLFireability-02 7736514 m, 48466 m/sec, 34377074 t fired, .
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[lola][.] 7 LTL EXCL 179/875 76/2000 CO4-PT-17-LTLFireability-02 11075223 m, 43926 m/sec, 48904167 t fired, .
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