MCC'2024- Execution of r551-tall-171734899400131

About the Execution of LoLA for CO4-PT-17

Execution Summary
Max Memory Used (MB)	Time wait (ms)	CPU Usage (ms)	I/O Wait (ms)	Computed Result	Execution Status
12482.031	3600000.00	2060374.00	8967.20	??T????TTFF??F?F	normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r551-tall-171734899400131.qcow2',
Waiting for the VM to be ready (probing ssh)
..........................................................
====================================
Generated by BenchKit 2-5568
Executing tool lola
Input is CO4-PT-17, examination is LTLCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r551-tall-171734899400131
==========================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 684K
-rw-r--r-- 1 mcc users 6.3K Jun 2 17:16 CTLCardinality.tx
-rw-r--r-- 1 mcc users 67K Jun 2 17:16 CTLCardinality.xm
-rw-r--r-- 1 mcc users 5.9K Jun 2 17:16 CTLFireability.tx
-rw-r--r-- 1 mcc users 56K Jun 2 17:16 CTLFireability.xm
-rw-r--r-- 1 mcc users 3.5K Jun 2 17:12 LTLCardinality.tx
-rw-r--r-- 1 mcc users 26K Jun 2 17:12 LTLCardinality.xm
-rw-r--r-- 1 mcc users 2.2K Jun 2 17:12 LTLFireability.tx
-rw-r--r-- 1 mcc users 18K Jun 2 17:12 LTLFireability.xm
-rw-r--r-- 1 mcc users 1 Jun 2 16:33 NewModel
-rw-r--r-- 1 mcc users 9.9K Jun 2 17:16 ReachabilityCardi
-rw-r--r-- 1 mcc users 102K Jun 2 17:16 ReachabilityCardi
-rw-r--r-- 1 mcc users 9.4K Jun 2 17:16 ReachabilityFirea
-rw-r--r-- 1 mcc users 85K Jun 2 17:16 ReachabilityFirea
-rw-r--r-- 1 mcc users 1.5K Jun 2 17:12 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.5K Jun 2 17:12 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Jun 2 16:33 equiv_col
-rw-r--r-- 1 mcc users 3 Jun 2 16:33 instance
-rw-r--r-- 1 mcc users 6 Jun 2 16:33 iscolored
-rw-r--r-- 1 mcc users 248K Jun 2 16:33 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from
FORMULA_NAME CO4-PT-17-LTLCardinality-00
FORMULA_NAME CO4-PT-17-LTLCardinality-01
FORMULA_NAME CO4-PT-17-LTLCardinality-02
FORMULA_NAME CO4-PT-17-LTLCardinality-03
FORMULA_NAME CO4-PT-17-LTLCardinality-04
FORMULA_NAME CO4-PT-17-LTLCardinality-05
FORMULA_NAME CO4-PT-17-LTLCardinality-06
FORMULA_NAME CO4-PT-17-LTLCardinality-07
FORMULA_NAME CO4-PT-17-LTLCardinality-08
FORMULA_NAME CO4-PT-17-LTLCardinality-09
FORMULA_NAME CO4-PT-17-LTLCardinality-10
FORMULA_NAME CO4-PT-17-LTLCardinality-11
FORMULA_NAME CO4-PT-17-LTLCardinality-12
FORMULA_NAME CO4-PT-17-LTLCardinality-13
FORMULA_NAME CO4-PT-17-LTLCardinality-14
FORMULA_NAME CO4-PT-17-LTLCardinality-15

=== Now, execution of the tool begins

BK_START 1717406117195

FORMULA CO4-PT-17-LTLCardinality-09 FALSE TECHNIQUES
FORMULA CO4-PT-17-LTLCardinality-07 TRUE
FORMULA CO4-PT-17-LTLCardinality-10 FALSE
FORMULA CO4-PT-17-LTLCardinality-02 TRUE
FORMULA CO4-PT-17-LTLCardinality-08 TRUE
FORMULA CO4-PT-17-LTLCardinality-13 FALSE
FORMULA CO4-PT-17-LTLCardinality-15 FALSE

BK_TIME_CONFINEMENT_REACHED

--------------------
content from stderr:

[[35mlola[0m][I] LoLA will run for 3600 seconds
[[35mlola[0m][W] [1m[33munknown unit in memory
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition
[[35mlola[0m][I] closed [1m[34mnet[0m file
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformu
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m
[[35mlola[0m][I] Rule S: 238 transitions removed,198
[[35mlola[0m][I] LAUNCH task # 28 (type CNST)
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 28 (type CNST)
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 22 (type CNST)
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 22 (type CNST)
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 31 (type CNST)
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 31 (type CNST)
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 7 (type CNST)
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 7 (type CNST)
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 53 (type EXCL)
[[35mlola[0m][I] time limit : 273 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 56 (type EQUN)
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 58 (type FNDP)
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 59 (type EQUN)
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 53 (type EXCL)
[[35mlola[0m][I] result : false
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 56 (type EQUN)
[[35mlola[0m][I] LAUNCH task # 60 (type EXCL)
[[35mlola[0m][I] time limit : 296 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 65 (type EQUN)
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 60 (type EXCL)
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 7
[[35mlola[0m][I] fired transitions : 6
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 58 (type FNDP)
[[35mlola[0m][W] CANCELED task # 59 (type EQUN)
[[35mlola[0m][I] LAUNCH task # 50 (type EXCL)
[[35mlola[0m][I] time limit : 323 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 50 (type EXCL)
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 39
[[35mlola[0m][I] fired transitions : 39
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 47 (type EXCL)
[[35mlola[0m][I] time limit : 355 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 58 (type FNDP)
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] FINISHED task # 56 (type EQUN)
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] FINISHED task # 65 (type EQUN)
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] FINISHED task # 59 (type EQUN)
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-02: INITIAL
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-07: INITIAL
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[[35mlola[0m][.] CO4-PT-17-LTLCardinality-00:
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[[35mlola[0m][.] CO4-PT-17-LTLCardinality-03:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-04: LTL/CTL
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-05:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-06:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-11:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-12:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-14:
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[[35mlola[0m][.] CO4-PT-17-LTLCardinality-00:
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[[35mlola[0m][.] CO4-PT-17-LTLCardinality-03:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-04: LTL/CTL
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-05:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-06:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-11:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-12:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-14:
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[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-08:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-09: INITIAL
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[[35mlola[0m][.] CO4-PT-17-LTLCardinality-05:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-06:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-11:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-12:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-14:
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[[35mlola[0m][.] CO4-PT-17-LTLCardinality-04: LTL/CTL
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-05:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-06:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-11:
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[[35mlola[0m][.] CO4-PT-17-LTLCardinality-14:
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[[35mlola[0m][.] 47 LTL EXCL 295/355
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[[35mlola[0m][.] CO4-PT-17-LTLCardinality-00:
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[[35mlola[0m][.] CO4-PT-17-LTLCardinality-05:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-06:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-11:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-12:
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[[35mlola[0m][.] CO4-PT-17-LTLCardinality-00:
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[[35mlola[0m][.] CO4-PT-17-LTLCardinality-05:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-06:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-11:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-12:
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[[35mlola[0m][.] CO4-PT-17-LTLCardinality-00:
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[[35mlola[0m][.] CO4-PT-17-LTLCardinality-11:
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[[35mlola[0m][.] CO4-PT-17-LTLCardinality-06:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-11:
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[[35mlola[0m][.] CO4-PT-17-LTLCardinality-00:
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[[35mlola[0m][.] CO4-PT-17-LTLCardinality-00:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-01:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-03:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-04: LTL/CTL
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-05:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-06:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-11:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-12:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 401 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 38 (type EXCL)
[[35mlola[0m][I] time limit : 355 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 47 (type EXCL)
[[35mlola[0m][I] time limit : 3199 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 38 (type EXCL)
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 84
[[35mlola[0m][I] fired transitions : 90
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-02: INITIAL
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-07: INITIAL
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-08:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-09: INITIAL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-10: INITIAL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-13:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-00:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-01:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-03:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-04: LTL/CTL
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-05:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-06:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-12:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 47 LTL EXCL 5/399
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 406 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 47 (type EXCL)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-02: INITIAL
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-07: INITIAL
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-08:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-09: INITIAL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-10: INITIAL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-13:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-00:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-01:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-03:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-04: LTL/CTL
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-05:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-06:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-12:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 411 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 19 (type EXCL)
[[35mlola[0m][I] time limit : 455 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 19 (type EXCL)
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 39
[[35mlola[0m][I] fired transitions : 39
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 16 (type EXCL)
[[35mlola[0m][I] time limit : 531 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 16 (type EXCL)
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 39
[[35mlola[0m][I] fired transitions : 39
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 13 (type EXCL)
[[35mlola[0m][I] time limit : 637 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 13 (type EXCL)
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 39
[[35mlola[0m][I] fired transitions : 39
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 10 (type EXCL)
[[35mlola[0m][I] time limit : 797 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 10 (type EXCL)
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 39
[[35mlola[0m][I] fired transitions : 39
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 4 (type EXCL)
[[35mlola[0m][I] time limit : 1063 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 4 (type EXCL)
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 2
[[35mlola[0m][I] fired transitions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 1 (type EXCL)
[[35mlola[0m][I] time limit : 1594 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-01:
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-02: INITIAL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-04: LTL/CTL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-05:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-06:
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-07: INITIAL
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-08:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-09: INITIAL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-10: INITIAL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-13:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-00:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-12:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 5/1594
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 416 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-01:
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-02: INITIAL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-04: LTL/CTL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-05:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-06:
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-07: INITIAL
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-08:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-09: INITIAL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-10: INITIAL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-13:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-00:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-12:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 10/1594
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 421 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-01:
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-02: INITIAL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-04: LTL/CTL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-05:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-06:
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-07: INITIAL
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-08:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-09: INITIAL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-10: INITIAL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-13:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-00:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-12:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 15/1594
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 426 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-01:
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-02: INITIAL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-04: LTL/CTL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-05:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-06:
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-07: INITIAL
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-08:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-09: INITIAL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-10: INITIAL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-13:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-00:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-12:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 20/1594
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 431 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-01:
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-02: INITIAL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-04: LTL/CTL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-05:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-06:
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-07: INITIAL
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-08:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-09: INITIAL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-10: INITIAL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-11:
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[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-00:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-12:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 25/1594
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 436 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-01:
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-02: INITIAL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-04: LTL/CTL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-05:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-06:
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-07: INITIAL
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-08:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-09: INITIAL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-10: INITIAL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-11:
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[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-00:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-12:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-14:
[[35mlola[0m][.]
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[[35mlola[0m][.] 1 LTL EXCL 30/1594
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 441 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-01:
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-02: INITIAL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-04: LTL/CTL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-05:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-06:
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-07: INITIAL
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-08:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-09: INITIAL
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[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-11:
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[[35mlola[0m][.] CO4-PT-17-LTLCardinality-00:
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[[35mlola[0m][.] 1 LTL EXCL 35/1594
[[35mlola[0m][.]
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[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
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[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-01:
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-02: INITIAL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-04: LTL/CTL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-05:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-06:
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-07: INITIAL
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-08:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-09: INITIAL
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[[35mlola[0m][.] CO4-PT-17-LTLCardinality-00:
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[[35mlola[0m][.] 1 LTL EXCL 40/1594
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 451 secs.
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[[35mlola[0m][.] 1 LTL EXCL 45/1594
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[[35mlola[0m][.] Time elapsed: 456 secs.
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[[35mlola[0m][.] Time elapsed: 461 secs.
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[[35mlola[0m][.] 1 LTL EXCL 105/1594
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[[35mlola[0m][.] 1 LTL EXCL 165/1594
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[[35mlola[0m][.] 1 LTL EXCL 225/1594
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[[35mlola[0m][.] 1 LTL EXCL 285/1594
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[[35mlola[0m][.] 1 LTL EXCL 345/1594
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[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 405/1594
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[[35mlola[0m][.] 1 LTL EXCL 410/1594
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[[35mlola[0m][.] 1 LTL EXCL 425/1594
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[[35mlola[0m][.] 1 LTL EXCL 465/1594
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[[35mlola[0m][.] 1 LTL EXCL 525/1594
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[[35mlola[0m][.] 1 LTL EXCL 585/1594
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[[35mlola[0m][.] 1 LTL EXCL 590/1594
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[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 645/1594
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1056 secs.
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[[35mlola[0m][.] 1 LTL EXCL 650/1594
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[[35mlola[0m][.] Time elapsed: 1061 secs.
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[[35mlola[0m][.] 1 LTL EXCL 655/1594
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[[35mlola[0m][.] 1 LTL EXCL 665/1594
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[[35mlola[0m][.] 1 LTL EXCL 670/1594
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[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 705/1594
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[[35mlola[0m][.] 1 LTL EXCL 710/1594
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[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 765/1594
[[35mlola[0m][.]
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[[35mlola[0m][.] 1 LTL EXCL 770/1594
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[[35mlola[0m][.] 1 LTL EXCL 775/1594
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[[35mlola[0m][.] 1 LTL EXCL 780/1594
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[[35mlola[0m][.] 1 LTL EXCL 785/1594
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[[35mlola[0m][.] 1 LTL EXCL 790/1594
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[[35mlola[0m][.] 1 LTL EXCL 795/1594
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[[35mlola[0m][.] 1 LTL EXCL 805/1594
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[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 825/1594
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1236 secs.
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[[35mlola[0m][.] 1 LTL EXCL 830/1594
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[[35mlola[0m][.] 1 LTL EXCL 835/1594
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[[35mlola[0m][.] 1 LTL EXCL 840/1594
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[[35mlola[0m][.] 1 LTL EXCL 845/1594
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[[35mlola[0m][.] 1 LTL EXCL 850/1594
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[[35mlola[0m][.] 1 LTL EXCL 855/1594
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[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 885/1594
[[35mlola[0m][.]
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[[35mlola[0m][.] 1 LTL EXCL 890/1594
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[[35mlola[0m][.] 1 LTL EXCL 895/1594
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[[35mlola[0m][.] 1 LTL EXCL 900/1594
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[[35mlola[0m][.] 1 LTL EXCL 905/1594
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[[35mlola[0m][.] 1 LTL EXCL 910/1594
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[[35mlola[0m][.] 1 LTL EXCL 915/1594
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[[35mlola[0m][.] 1 LTL EXCL 930/1594
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[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-04: LTL/CTL
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[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 945/1594
[[35mlola[0m][.]
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[[35mlola[0m][.] 1 LTL EXCL 950/1594
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[[35mlola[0m][.] 1 LTL EXCL 955/1594
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[[35mlola[0m][.] 1 LTL EXCL 960/1594
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[[35mlola[0m][.] 1 LTL EXCL 965/1594
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[[35mlola[0m][.] 1 LTL EXCL 970/1594
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[[35mlola[0m][.] 1 LTL EXCL 975/1594
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[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 1005/1594
[[35mlola[0m][.]
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[[35mlola[0m][.] 1 LTL EXCL 1010/1594
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[[35mlola[0m][.] 1 LTL EXCL 1015/1594
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[[35mlola[0m][.] 1 LTL EXCL 1020/1594
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[[35mlola[0m][.] 1 LTL EXCL 1025/1594
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[[35mlola[0m][.] 1 LTL EXCL 1030/1594
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[[35mlola[0m][.] 1 LTL EXCL 1035/1594
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[[35mlola[0m][.] 1 LTL EXCL 1040/1594
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[[35mlola[0m][.] 1 LTL EXCL 1045/1594
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[[35mlola[0m][.] 1 LTL EXCL 1050/1594
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[[35mlola[0m][.] 1 LTL EXCL 1055/1594
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[[35mlola[0m][.] 1 LTL EXCL 1060/1594
[[35mlola[0m][.]
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[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 1065/1594
[[35mlola[0m][.]
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[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 1070/1594
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[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 1075/1594
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[[35mlola[0m][.] 1 LTL EXCL 1080/1594
[[35mlola[0m][.]
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[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 1085/1594
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[[35mlola[0m][.] 1 LTL EXCL 1090/1594
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[[35mlola[0m][.] 1 LTL EXCL 1095/1594
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[[35mlola[0m][.] 1 LTL EXCL 1100/1594
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[[35mlola[0m][.] 1 LTL EXCL 1105/1594
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[[35mlola[0m][.] 1 LTL EXCL 1110/1594
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[[35mlola[0m][.] 1 LTL EXCL 1115/1594
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[[35mlola[0m][.] 1 LTL EXCL 1125/1594
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[[35mlola[0m][.] 1 LTL EXCL 1130/1594
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[[35mlola[0m][.] 1 LTL EXCL 1140/1594
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[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 1186/1594
[[35mlola[0m][.]
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[[35mlola[0m][.] 1 LTL EXCL 1191/1594
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[[35mlola[0m][.] 1 LTL EXCL 1196/1594
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[[35mlola[0m][.] 1 LTL EXCL 1201/1594
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[[35mlola[0m][.] 1 LTL EXCL 1206/1594
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[[35mlola[0m][.] 1 LTL EXCL 1211/1594
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[[35mlola[0m][.] 1 LTL EXCL 1216/1594
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[[35mlola[0m][.] 1 LTL EXCL 1231/1594
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[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 1246/1594
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1657 secs.
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[[35mlola[0m][.] 1 LTL EXCL 1251/1594
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[[35mlola[0m][.] Time elapsed: 1662 secs.
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[[35mlola[0m][.] 1 LTL EXCL 1256/1594
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[[35mlola[0m][.] 1 LTL EXCL 1261/1594
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[[35mlola[0m][.] 1 LTL EXCL 1266/1594
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[[35mlola[0m][.] 1 LTL EXCL 1271/1594
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[[35mlola[0m][.] 1 LTL EXCL 1276/1594
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[[35mlola[0m][.] 1 LTL EXCL 1296/1594
[[35mlola[0m][.]
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[[35mlola[0m][.]
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[[35mlola[0m][.] 1 LTL EXCL 1306/1594
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[[35mlola[0m][.] 1 LTL EXCL 1311/1594
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[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 1366/1594
[[35mlola[0m][.]
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[[35mlola[0m][.] 1 LTL EXCL 1371/1594
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[[35mlola[0m][.] 1 LTL EXCL 1376/1594
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[[35mlola[0m][.] 1 LTL EXCL 1381/1594
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[[35mlola[0m][.] 1 LTL EXCL 1386/1594
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[[35mlola[0m][.] 1 LTL EXCL 1391/1594
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[[35mlola[0m][.] 1 LTL EXCL 1396/1594
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[[35mlola[0m][.] 1 LTL EXCL 1411/1594
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[[35mlola[0m][.] 1 LTL EXCL 1421/1594
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[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-04: LTL/CTL
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[[35mlola[0m][.] CO4-PT-17-LTLCardinality-00:
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[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 1426/1594
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1837 secs.
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[[35mlola[0m][.] 1 LTL EXCL 1431/1594
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1842 secs.
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[[35mlola[0m][.] 1 LTL EXCL 1436/1594
[[35mlola[0m][.]
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[[35mlola[0m][.] 1 LTL EXCL 1441/1594
[[35mlola[0m][.]
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[[35mlola[0m][.] 1 LTL EXCL 1446/1594
[[35mlola[0m][.]
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[[35mlola[0m][.] 1 LTL EXCL 1451/1594
[[35mlola[0m][.]
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[[35mlola[0m][.] 1 LTL EXCL 1456/1594
[[35mlola[0m][.]
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[[35mlola[0m][.] 1 LTL EXCL 1461/1594
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[[35mlola[0m][.]
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[[35mlola[0m][.] 1 LTL EXCL 1471/1594
[[35mlola[0m][.]
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[[35mlola[0m][.] 1 LTL EXCL 1476/1594
[[35mlola[0m][.]
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[[35mlola[0m][.] CO4-PT-17-LTLCardinality-00:
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[[35mlola[0m][.]
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[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-02: INITIAL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-04: LTL/CTL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-05:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-06:
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-07: INITIAL
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-08:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-09: INITIAL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-10: INITIAL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-13:
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[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-00:
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[[35mlola[0m][.] CO4-PT-17-LTLCardinality-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 1486/1594
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1897 secs.
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[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-04: LTL/CTL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-05:
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[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-09: INITIAL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-10: INITIAL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-11:
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[[35mlola[0m][.] CO4-PT-17-LTLCardinality-00:
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[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 1491/1594
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1902 secs.
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[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-04: LTL/CTL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-05:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-06:
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-07: INITIAL
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-08:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-09: INITIAL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-10: INITIAL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-11:
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[[35mlola[0m][.] CO4-PT-17-LTLCardinality-00:
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[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 1496/1594
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1907 secs.
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[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-04: LTL/CTL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-05:
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[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 1501/1594
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1912 secs.
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[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 1506/1594
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1917 secs.
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[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 1511/1594
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1922 secs.
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[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 1516/1594
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1927 secs.
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[[35mlola[0m][.]
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[[35mlola[0m][.] 1 LTL EXCL 1521/1594
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1932 secs.
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[[35mlola[0m][.]
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[[35mlola[0m][.] 1 LTL EXCL 1526/1594
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1937 secs.
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[[35mlola[0m][.] CO4-PT-17-LTLCardinality-00:
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[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 1531/1594
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1942 secs.
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[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-06:
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[[35mlola[0m][.] CO4-PT-17-LTLCardinality-00:
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[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 1536/1594
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1947 secs.
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[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-03:
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[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-06:
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[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-08:
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[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-11:
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[[35mlola[0m][.] CO4-PT-17-LTLCardinality-00:
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[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 1541/1594
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1952 secs.
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[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-01:
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-02: INITIAL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-04: LTL/CTL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-05:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-06:
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-07: INITIAL
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-08:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-09: INITIAL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-10: INITIAL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-13:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-00:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-12:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 1546/1594
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1957 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-01:
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-02: INITIAL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-04: LTL/CTL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-05:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-06:
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-07: INITIAL
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-08:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-09: INITIAL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-10: INITIAL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-13:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-00:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-12:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 1551/1594
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1962 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-01:
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-02: INITIAL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-04: LTL/CTL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-05:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-06:
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-07: INITIAL
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-08:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-09: INITIAL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-10: INITIAL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-13:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-00:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-12:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 1556/1594
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1967 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-01:
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-02: INITIAL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-04: LTL/CTL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-05:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-06:
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-07: INITIAL
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-08:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-09: INITIAL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-10: INITIAL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-13:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-00:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-12:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 1561/1594
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1972 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-01:
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-02: INITIAL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-04: LTL/CTL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-05:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-06:
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-07: INITIAL
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-08:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-09: INITIAL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-10: INITIAL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-13:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-00:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-12:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 1566/1594
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1977 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-01:
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-02: INITIAL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-04: LTL/CTL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-05:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-06:
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-07: INITIAL
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-08:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-09: INITIAL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-10: INITIAL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-13:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-00:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-12:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 1571/1594
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1982 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-01:
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-02: INITIAL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-04: LTL/CTL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-05:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-06:
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-07: INITIAL
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-08:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-09: INITIAL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-10: INITIAL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-13:
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[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-00:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-12:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 1576/1594
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1987 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-01:
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-02: INITIAL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-04: LTL/CTL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-05:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-06:
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-07: INITIAL
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-08:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-09: INITIAL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-10: INITIAL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-11:
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[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-00:
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[[35mlola[0m][.] CO4-PT-17-LTLCardinality-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 1581/1594
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1992 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-01:
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-02: INITIAL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-04: LTL/CTL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-05:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-06:
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-07: INITIAL
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-08:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-09: INITIAL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-10: INITIAL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-11:
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[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-00:
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[[35mlola[0m][.] CO4-PT-17-LTLCardinality-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 1586/1594
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1997 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-01:
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-02: INITIAL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-04: LTL/CTL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-05:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-06:
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-07: INITIAL
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-08:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-09: INITIAL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-10: INITIAL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-11:
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[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-00:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-12:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 1591/1594
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2002 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 1 (type EXCL)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-01:
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-02: INITIAL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-04: LTL/CTL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-05:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-06:
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-07: INITIAL
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-08:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-09: INITIAL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-10: INITIAL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-13:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-00:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-12:
[[35mlola[0m][.] CO4-PT-17-LTLCardinality-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2007 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 41 (type EXCL)
[[35mlola[0m][I] time limit : 1593 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 1 (type EXCL)
[[35mlola[0m][I] time limit : 1593 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 41 (type EXCL)
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 29098
[[35mlola[0m][I] fired transitions : 67358
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-01:
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-02: INITIAL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-04: LTL/CTL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-05:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-06:
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-07: INITIAL
[[35mlola[0m][.] [1m[32mCO4-PT-17-LTLCardinality-08:
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-09: INITIAL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-10: INITIAL
[[35mlola[0m][.] [1m[31mCO4-PT-17-LTLCardinality-11:
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[[35mlola[0m][.] 1 LTL EXCL 5/1593
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================================= =========== t l t l t l t l nality.txt nality.xml bility.txt bility.xml (invocation template) text file) COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT at most ([1m[36m--timelimit[0m) specification: using default[0m [4m[34mmodel.pnml[0m [0m) net [4m[34mmodel.pnml[0m la[0m) from [4m[34mLTLCardinality.xml[0m places removed for 27 CO4-PT-17-LTLCardinality-09 for CO4-PT-17-LTLCardinality-09 for 21 CO4-PT-17-LTLCardinality-07 for CO4-PT-17-LTLCardinality-07 for 30 CO4-PT-17-LTLCardinality-10 for CO4-PT-17-LTLCardinality-10 for 6 CO4-PT-17-LTLCardinality-02 for CO4-PT-17-LTLCardinality-02 for 24 CO4-PT-17-LTLCardinality-08 for 24 CO4-PT-17-LTLCardinality-08 for 43 CO4-PT-17-LTLCardinality-13 for 43 CO4-PT-17-LTLCardinality-13 for CO4-PT-17-LTLCardinality-08 for CO4-PT-17-LTLCardinality-08 (obsolete) for 43 CO4-PT-17-LTLCardinality-13 for 33 CO4-PT-17-LTLCardinality-11 for CO4-PT-17-LTLCardinality-13 for CO4-PT-17-LTLCardinality-13 (obsolete) for CO4-PT-17-LTLCardinality-13 (obsolete) for 49 CO4-PT-17-LTLCardinality-15 for CO4-PT-17-LTLCardinality-15 for 46 CO4-PT-17-LTLCardinality-14 for CO4-PT-17-LTLCardinality-13 for CO4-PT-17-LTLCardinality-08 for CO4-PT-17-LTLCardinality-11 for CO4-PT-17-LTLCardinality-13 VALUE PRODUCED BY[0m true preprocessing[0m true preprocessing[0m AU true state space /ER[0m false preprocessing[0m false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 CONJ 0 2 0 0 3 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 3/2000 CO4-PT-17-LTLCardinality-14 364292 m, 72858 m/sec, 1521181 t fired, . in use: 3 VALUE PRODUCED BY[0m true preprocessing[0m true preprocessing[0m AU true state space /ER[0m false preprocessing[0m false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 CONJ 0 2 0 0 3 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 5/2000 CO4-PT-17-LTLCardinality-14 713709 m, 69883 m/sec, 3192198 t fired, . in use: 5 VALUE PRODUCED BY[0m true preprocessing[0m true preprocessing[0m AU true state space /ER[0m false preprocessing[0m false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 CONJ 0 2 0 0 3 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 9/2000 CO4-PT-17-LTLCardinality-14 1148472 m, 86952 m/sec, 4899021 t fired, . in use: 9 VALUE PRODUCED BY[0m true preprocessing[0m true preprocessing[0m AU true state space /ER[0m false preprocessing[0m false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 CONJ 0 2 0 0 3 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 12/2000 CO4-PT-17-LTLCardinality-14 1609908 m, 92287 m/sec, 6497542 t fired, . in use: 12 VALUE PRODUCED BY[0m true preprocessing[0m true preprocessing[0m AU true state space /ER[0m false preprocessing[0m false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 CONJ 0 2 0 0 3 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 14/2000 CO4-PT-17-LTLCardinality-14 2007615 m, 79541 m/sec, 8143403 t fired, . in use: 14 VALUE PRODUCED BY[0m true preprocessing[0m true preprocessing[0m AU true state space /ER[0m false preprocessing[0m false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 CONJ 0 2 0 0 3 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 17/2000 CO4-PT-17-LTLCardinality-14 2402696 m, 79016 m/sec, 9762912 t fired, . in use: 17 VALUE PRODUCED BY[0m true preprocessing[0m true preprocessing[0m AU true state space /ER[0m false preprocessing[0m false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 CONJ 0 2 0 0 3 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 20/2000 CO4-PT-17-LTLCardinality-14 2768492 m, 73159 m/sec, 11272369 t fired, . in use: 20 VALUE PRODUCED BY[0m true preprocessing[0m true preprocessing[0m AU true state space /ER[0m false preprocessing[0m false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 CONJ 0 2 0 0 3 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 22/2000 CO4-PT-17-LTLCardinality-14 3085244 m, 63350 m/sec, 12755382 t fired, . in use: 22 VALUE PRODUCED BY[0m true preprocessing[0m true preprocessing[0m AU true state space /ER[0m false preprocessing[0m false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 CONJ 0 2 0 0 3 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 24/2000 CO4-PT-17-LTLCardinality-14 3422207 m, 67392 m/sec, 14390413 t fired, . in use: 24 VALUE PRODUCED BY[0m true preprocessing[0m true preprocessing[0m AU true state space /ER[0m false preprocessing[0m false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 CONJ 0 2 0 0 3 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 27/2000 CO4-PT-17-LTLCardinality-14 3773599 m, 70278 m/sec, 16087040 t fired, . in use: 27 VALUE PRODUCED BY[0m true preprocessing[0m true preprocessing[0m AU true state space /ER[0m false preprocessing[0m false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 CONJ 0 2 0 0 3 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 30/2000 CO4-PT-17-LTLCardinality-14 4127428 m, 70765 m/sec, 17349142 t fired, . in use: 30 VALUE PRODUCED BY[0m true preprocessing[0m true preprocessing[0m AU true state space /ER[0m false preprocessing[0m false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 CONJ 0 2 0 0 3 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 32/2000 CO4-PT-17-LTLCardinality-14 4458631 m, 66240 m/sec, 18741366 t fired, . Pages in use: 32 VALUE PRODUCED BY[0m true preprocessing[0m true preprocessing[0m AU true state space /ER[0m false preprocessing[0m false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 CONJ 0 2 0 0 3 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 34/2000 CO4-PT-17-LTLCardinality-14 4749713 m, 58216 m/sec, 20044494 t fired, . Pages in use: 34 VALUE PRODUCED BY[0m true preprocessing[0m true preprocessing[0m AU true state space /ER[0m false preprocessing[0m false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 CONJ 0 2 0 0 3 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 36/2000 CO4-PT-17-LTLCardinality-14 5011359 m, 52329 m/sec, 21374234 t fired, . Pages in use: 36 VALUE PRODUCED BY[0m true preprocessing[0m true preprocessing[0m AU true state space /ER[0m false preprocessing[0m false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 CONJ 0 2 0 0 3 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 38/2000 CO4-PT-17-LTLCardinality-14 5318670 m, 61462 m/sec, 22790128 t fired, . Pages in use: 38 VALUE PRODUCED BY[0m true preprocessing[0m true preprocessing[0m AU true state space /ER[0m false preprocessing[0m false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 CONJ 0 2 0 0 3 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 40/2000 CO4-PT-17-LTLCardinality-14 5577392 m, 51744 m/sec, 24011872 t fired, . Pages in use: 40 VALUE PRODUCED BY[0m true preprocessing[0m true preprocessing[0m AU true state space /ER[0m false preprocessing[0m false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 CONJ 0 2 0 0 3 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 42/2000 CO4-PT-17-LTLCardinality-14 5867146 m, 57950 m/sec, 25441016 t fired, . Pages in use: 42 VALUE PRODUCED BY[0m true preprocessing[0m true preprocessing[0m AU true state space /ER[0m false preprocessing[0m false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 CONJ 0 2 0 0 3 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 44/2000 CO4-PT-17-LTLCardinality-14 6147144 m, 55999 m/sec, 26718690 t fired, . Pages in use: 44 VALUE PRODUCED BY[0m true preprocessing[0m true preprocessing[0m AU true state space /ER[0m false preprocessing[0m false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 CONJ 0 2 0 0 3 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 45/2000 CO4-PT-17-LTLCardinality-14 6400166 m, 50604 m/sec, 28021051 t fired, . Pages in use: 45 VALUE PRODUCED BY[0m true preprocessing[0m true preprocessing[0m AU true state space /ER[0m false preprocessing[0m false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 CONJ 0 2 0 0 3 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 47/2000 CO4-PT-17-LTLCardinality-14 6704551 m, 60877 m/sec, 29388962 t fired, . Pages in use: 47 VALUE PRODUCED BY[0m true preprocessing[0m true preprocessing[0m AU true state space /ER[0m false preprocessing[0m false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 CONJ 0 2 0 0 3 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 49/2000 CO4-PT-17-LTLCardinality-14 6953036 m, 49697 m/sec, 30580578 t fired, . Pages in use: 49 VALUE PRODUCED BY[0m true preprocessing[0m true preprocessing[0m AU true state space /ER[0m false preprocessing[0m false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 CONJ 0 2 0 0 3 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 51/2000 CO4-PT-17-LTLCardinality-14 7235795 m, 56551 m/sec, 31975797 t fired, . Pages in use: 51 VALUE PRODUCED BY[0m true preprocessing[0m true preprocessing[0m AU true state space /ER[0m false preprocessing[0m false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 CONJ 0 2 0 0 3 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 53/2000 CO4-PT-17-LTLCardinality-14 7509076 m, 54656 m/sec, 33222150 t fired, . Pages in use: 53 VALUE PRODUCED BY[0m true preprocessing[0m true preprocessing[0m AU true state space /ER[0m false preprocessing[0m false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 CONJ 0 2 0 0 3 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 55/2000 CO4-PT-17-LTLCardinality-14 7754694 m, 49123 m/sec, 34474721 t fired, . Pages in use: 55 VALUE PRODUCED BY[0m true preprocessing[0m true preprocessing[0m AU true state space /ER[0m false preprocessing[0m false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 CONJ 0 2 0 0 3 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 57/2000 CO4-PT-17-LTLCardinality-14 8047927 m, 58646 m/sec, 35815863 t fired, . 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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="CO4-PT-17"
export BK_EXAMINATION="LTLCardinality"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is CO4-PT-17, examination is LTLCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r551-tall-171734899400131"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/CO4-PT-17.tgz
mv CO4-PT-17 execution
cd execution
if [ "LTLCardinality" = "ReachabilityDeadlock" ] || [ "LTLCardinality" = "UpperBounds" ] || [ "LTLCardinality" = "QuasiLiveness" ] || [ "LTLCardinality" = "StableMarking" ] || [ "LTLCardinality" = "Liveness" ] || [ "LTLCardinality" = "OneSafe" ] || [ "LTLCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "LTLCardinality" = "ReachabilityDeadlock" ] || [ "LTLCardinality" = "QuasiLiveness" ] || [ "LTLCardinality" = "StableMarking" ] || [ "LTLCardinality" = "Liveness" ] || [ "LTLCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;