About the Execution of LoLA for CO4-PT-17
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 8413.088 | 2095166.00 | 2128191.00 | 6009.10 | FT?T?TFTFT??FT?T | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r551-tall-171734899400130.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is CO4-PT-17, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r551-tall-171734899400130
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 684K
-rw-r--r-- 1 mcc users 6.3K Jun 2 17:16 CTLCardinality.txt
-rw-r--r-- 1 mcc users 67K Jun 2 17:16 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.9K Jun 2 17:16 CTLFireability.txt
-rw-r--r-- 1 mcc users 56K Jun 2 17:16 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.5K Jun 2 17:12 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Jun 2 17:12 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Jun 2 17:12 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Jun 2 17:12 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 Jun 2 16:33 NewModel
-rw-r--r-- 1 mcc users 9.9K Jun 2 17:16 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 102K Jun 2 17:16 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.4K Jun 2 17:16 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 85K Jun 2 17:16 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.5K Jun 2 17:12 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.5K Jun 2 17:12 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Jun 2 16:33 equiv_col
-rw-r--r-- 1 mcc users 3 Jun 2 16:33 instance
-rw-r--r-- 1 mcc users 6 Jun 2 16:33 iscolored
-rw-r--r-- 1 mcc users 248K Jun 2 16:33 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME CO4-PT-17-CTLFireability-2024-00
FORMULA_NAME CO4-PT-17-CTLFireability-2024-01
FORMULA_NAME CO4-PT-17-CTLFireability-2024-02
FORMULA_NAME CO4-PT-17-CTLFireability-2024-03
FORMULA_NAME CO4-PT-17-CTLFireability-2024-04
FORMULA_NAME CO4-PT-17-CTLFireability-2024-05
FORMULA_NAME CO4-PT-17-CTLFireability-2024-06
FORMULA_NAME CO4-PT-17-CTLFireability-2024-07
FORMULA_NAME CO4-PT-17-CTLFireability-2024-08
FORMULA_NAME CO4-PT-17-CTLFireability-2024-09
FORMULA_NAME CO4-PT-17-CTLFireability-2024-10
FORMULA_NAME CO4-PT-17-CTLFireability-2024-11
FORMULA_NAME CO4-PT-17-CTLFireability-2024-12
FORMULA_NAME CO4-PT-17-CTLFireability-2024-13
FORMULA_NAME CO4-PT-17-CTLFireability-2024-14
FORMULA_NAME CO4-PT-17-CTLFireability-2024-15
=== Now, execution of the tool begins
BK_START 1717405928395
FORMULA CO4-PT-17-CTLFireability-2024-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-17-CTLFireability-2024-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-17-CTLFireability-2024-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-17-CTLFireability-2024-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-17-CTLFireability-2024-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-17-CTLFireability-2024-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-17-CTLFireability-2024-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-17-CTLFireability-2024-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-17-CTLFireability-2024-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-17-CTLFireability-2024-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-17-CTLFireability-2024-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[[35mlola[0m] [1mFINAL RESULTS[0m
[[35mlola[0m] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mCO4-PT-17-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m] [1m[33mCO4-PT-17-CTLFireability-2024-02: CTL unknown AGGR[0m
[[35mlola[0m] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m] [1m[33mCO4-PT-17-CTLFireability-2024-04: CTL unknown AGGR[0m
[[35mlola[0m] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mCO4-PT-17-CTLFireability-2024-08: F false state space / EG[0m
[[35mlola[0m] [1m[32mCO4-PT-17-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m] [1m[33mCO4-PT-17-CTLFireability-2024-10: CTL unknown AGGR[0m
[[35mlola[0m] [1m[33mCO4-PT-17-CTLFireability-2024-11: CTL unknown AGGR[0m
[[35mlola[0m] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m] [1m[33mCO4-PT-17-CTLFireability-2024-14: CTL unknown AGGR[0m
[[35mlola[0m] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m]
[[35mlola[0m] Time elapsed: 2095 secs. Pages in use: 114
BK_STOP 1717408023561
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 238 transitions removed,198 places removed
[[35mlola[0m][I] LAUNCH task # 52 (type EXCL) for 18 CO4-PT-17-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 179 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 50 (type FNDP) for 18 CO4-PT-17-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 51 (type EQUN) for 18 CO4-PT-17-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 50 (type FNDP) for CO4-PT-17-CTLFireability-2024-06
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 51 (type EQUN) for CO4-PT-17-CTLFireability-2024-06 (obsolete)
[[35mlola[0m][W] CANCELED task # 52 (type EXCL) for CO4-PT-17-CTLFireability-2024-06 (obsolete)
[[35mlola[0m][I] LAUNCH task # 22 (type EXCL) for 21 CO4-PT-17-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 188 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 22 (type EXCL) for CO4-PT-17-CTLFireability-2024-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 39
[[35mlola[0m][I] fired transitions : 80
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 16 (type EXCL) for 15 CO4-PT-17-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 199 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 16 (type EXCL) for CO4-PT-17-CTLFireability-2024-05
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 110
[[35mlola[0m][I] fired transitions : 148
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 1 (type EXCL) for 0 CO4-PT-17-CTLFireability-2024-00
[[35mlola[0m][I] time limit : 211 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 1 (type EXCL) for CO4-PT-17-CTLFireability-2024-00
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 11
[[35mlola[0m][I] fired transitions : 32
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] FINISHED task # 51 (type EQUN) for CO4-PT-17-CTLFireability-2024-06
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] LAUNCH task # 34 (type EXCL) for 33 CO4-PT-17-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 239 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 56 (type EQUN) for 24 CO4-PT-17-CTLFireability-2024-08
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 56 (type EQUN) for CO4-PT-17-CTLFireability-2024-08
[[35mlola[0m][I] result : true
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 5/299 2/2000 CO4-PT-17-CTLFireability-2024-11 333158 m, 66631 m/sec, 1347232 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 15 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 10/299 3/2000 CO4-PT-17-CTLFireability-2024-11 634242 m, 60216 m/sec, 2855741 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 20 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 15/299 5/2000 CO4-PT-17-CTLFireability-2024-11 1037578 m, 80667 m/sec, 4458656 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 25 secs. Pages in use: 5
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 20/299 7/2000 CO4-PT-17-CTLFireability-2024-11 1443535 m, 81191 m/sec, 5897264 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 30 secs. Pages in use: 7
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 25/299 9/2000 CO4-PT-17-CTLFireability-2024-11 1828153 m, 76923 m/sec, 7384851 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 35 secs. Pages in use: 9
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 30/299 11/2000 CO4-PT-17-CTLFireability-2024-11 2195356 m, 73440 m/sec, 8870824 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 40 secs. Pages in use: 11
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 35/299 12/2000 CO4-PT-17-CTLFireability-2024-11 2521326 m, 65194 m/sec, 10250858 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 45 secs. Pages in use: 12
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 40/299 14/2000 CO4-PT-17-CTLFireability-2024-11 2831981 m, 62131 m/sec, 11548735 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 50 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 45/299 15/2000 CO4-PT-17-CTLFireability-2024-11 3110604 m, 55724 m/sec, 12884528 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 55 secs. Pages in use: 15
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 50/299 16/2000 CO4-PT-17-CTLFireability-2024-11 3418917 m, 61662 m/sec, 14362280 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 60 secs. Pages in use: 16
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 55/299 18/2000 CO4-PT-17-CTLFireability-2024-11 3724274 m, 61071 m/sec, 15925682 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 65 secs. Pages in use: 18
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 60/299 20/2000 CO4-PT-17-CTLFireability-2024-11 4071654 m, 69476 m/sec, 17135210 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 70 secs. Pages in use: 20
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 65/299 21/2000 CO4-PT-17-CTLFireability-2024-11 4366445 m, 58958 m/sec, 18344571 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 75 secs. Pages in use: 21
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 70/299 22/2000 CO4-PT-17-CTLFireability-2024-11 4655987 m, 57908 m/sec, 19600131 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 80 secs. Pages in use: 22
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 75/299 23/2000 CO4-PT-17-CTLFireability-2024-11 4888634 m, 46529 m/sec, 20712957 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 85 secs. Pages in use: 23
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 80/299 25/2000 CO4-PT-17-CTLFireability-2024-11 5154336 m, 53140 m/sec, 22050252 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 90 secs. Pages in use: 25
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 85/299 26/2000 CO4-PT-17-CTLFireability-2024-11 5418936 m, 52920 m/sec, 23239336 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 95 secs. Pages in use: 26
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 90/299 27/2000 CO4-PT-17-CTLFireability-2024-11 5643455 m, 44903 m/sec, 24367581 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 100 secs. Pages in use: 27
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 95/299 28/2000 CO4-PT-17-CTLFireability-2024-11 5926737 m, 56656 m/sec, 25690840 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 105 secs. Pages in use: 28
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 100/299 29/2000 CO4-PT-17-CTLFireability-2024-11 6168732 m, 48399 m/sec, 26814819 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 110 secs. Pages in use: 29
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 105/299 30/2000 CO4-PT-17-CTLFireability-2024-11 6405788 m, 47411 m/sec, 28043747 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 115 secs. Pages in use: 30
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 110/299 32/2000 CO4-PT-17-CTLFireability-2024-11 6683010 m, 55444 m/sec, 29293838 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 120 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 115/299 33/2000 CO4-PT-17-CTLFireability-2024-11 6919267 m, 47251 m/sec, 30394305 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 125 secs. Pages in use: 33
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 120/299 34/2000 CO4-PT-17-CTLFireability-2024-11 7167700 m, 49686 m/sec, 31680174 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 130 secs. Pages in use: 34
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 125/299 35/2000 CO4-PT-17-CTLFireability-2024-11 7445040 m, 55468 m/sec, 32909486 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 135 secs. Pages in use: 35
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 130/299 36/2000 CO4-PT-17-CTLFireability-2024-11 7669007 m, 44793 m/sec, 34013464 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 140 secs. Pages in use: 36
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 135/299 37/2000 CO4-PT-17-CTLFireability-2024-11 7937656 m, 53729 m/sec, 35316301 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 145 secs. Pages in use: 37
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 140/299 38/2000 CO4-PT-17-CTLFireability-2024-11 8188991 m, 50267 m/sec, 36459416 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 150 secs. Pages in use: 38
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 145/299 39/2000 CO4-PT-17-CTLFireability-2024-11 8416952 m, 45592 m/sec, 37616264 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 155 secs. Pages in use: 39
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 150/299 40/2000 CO4-PT-17-CTLFireability-2024-11 8690755 m, 54760 m/sec, 38877045 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 160 secs. Pages in use: 40
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 155/299 41/2000 CO4-PT-17-CTLFireability-2024-11 8926386 m, 47126 m/sec, 39980537 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 165 secs. Pages in use: 41
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 160/299 42/2000 CO4-PT-17-CTLFireability-2024-11 9157461 m, 46215 m/sec, 41190396 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 170 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 165/299 43/2000 CO4-PT-17-CTLFireability-2024-11 9482515 m, 65010 m/sec, 42340606 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 175 secs. Pages in use: 43
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 170/299 44/2000 CO4-PT-17-CTLFireability-2024-11 9740979 m, 51692 m/sec, 43373392 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 180 secs. Pages in use: 44
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 175/299 46/2000 CO4-PT-17-CTLFireability-2024-11 10065616 m, 64927 m/sec, 44562116 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 185 secs. Pages in use: 46
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 180/299 47/2000 CO4-PT-17-CTLFireability-2024-11 10350603 m, 56997 m/sec, 45622343 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 190 secs. Pages in use: 47
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 185/299 48/2000 CO4-PT-17-CTLFireability-2024-11 10636277 m, 57134 m/sec, 46849892 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 195 secs. Pages in use: 48
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 190/299 49/2000 CO4-PT-17-CTLFireability-2024-11 10894933 m, 51731 m/sec, 48010880 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 200 secs. Pages in use: 49
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 195/299 50/2000 CO4-PT-17-CTLFireability-2024-11 11115684 m, 44150 m/sec, 49117915 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 205 secs. Pages in use: 50
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 200/299 51/2000 CO4-PT-17-CTLFireability-2024-11 11415500 m, 59963 m/sec, 50349439 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 210 secs. Pages in use: 51
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 205/299 53/2000 CO4-PT-17-CTLFireability-2024-11 11701168 m, 57133 m/sec, 51404300 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 215 secs. Pages in use: 53
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 210/299 54/2000 CO4-PT-17-CTLFireability-2024-11 11979333 m, 55633 m/sec, 52586875 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 220 secs. Pages in use: 54
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 215/299 55/2000 CO4-PT-17-CTLFireability-2024-11 12246806 m, 53494 m/sec, 53780255 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 225 secs. Pages in use: 55
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 220/299 56/2000 CO4-PT-17-CTLFireability-2024-11 12458134 m, 42265 m/sec, 54817063 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 230 secs. Pages in use: 56
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 225/299 57/2000 CO4-PT-17-CTLFireability-2024-11 12711124 m, 50598 m/sec, 56064961 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 235 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 230/299 58/2000 CO4-PT-17-CTLFireability-2024-11 12955381 m, 48851 m/sec, 57096400 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 240 secs. Pages in use: 58
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 235/299 60/2000 CO4-PT-17-CTLFireability-2024-11 13320049 m, 72933 m/sec, 58465411 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 245 secs. Pages in use: 60
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 240/299 61/2000 CO4-PT-17-CTLFireability-2024-11 13642181 m, 64426 m/sec, 59925452 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 250 secs. Pages in use: 61
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 245/299 63/2000 CO4-PT-17-CTLFireability-2024-11 13955981 m, 62760 m/sec, 61382105 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 255 secs. Pages in use: 63
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 250/299 64/2000 CO4-PT-17-CTLFireability-2024-11 14251481 m, 59100 m/sec, 62723706 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 260 secs. Pages in use: 64
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 255/299 65/2000 CO4-PT-17-CTLFireability-2024-11 14478053 m, 45314 m/sec, 63725458 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 265 secs. Pages in use: 65
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 260/299 66/2000 CO4-PT-17-CTLFireability-2024-11 14678916 m, 40172 m/sec, 64649331 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 270 secs. Pages in use: 66
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 265/299 67/2000 CO4-PT-17-CTLFireability-2024-11 14972376 m, 58692 m/sec, 65977987 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 275 secs. Pages in use: 67
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 270/299 69/2000 CO4-PT-17-CTLFireability-2024-11 15301348 m, 65794 m/sec, 67361602 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 280 secs. Pages in use: 69
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 275/299 70/2000 CO4-PT-17-CTLFireability-2024-11 15589671 m, 57664 m/sec, 68734415 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 285 secs. Pages in use: 70
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 280/299 72/2000 CO4-PT-17-CTLFireability-2024-11 15916877 m, 65441 m/sec, 70102787 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 290 secs. Pages in use: 72
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 285/299 73/2000 CO4-PT-17-CTLFireability-2024-11 16174917 m, 51608 m/sec, 71325659 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 295 secs. Pages in use: 73
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 290/299 74/2000 CO4-PT-17-CTLFireability-2024-11 16456841 m, 56384 m/sec, 72570880 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 300 secs. Pages in use: 74
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 295/299 76/2000 CO4-PT-17-CTLFireability-2024-11 16739458 m, 56523 m/sec, 73868420 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 305 secs. Pages in use: 76
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 34 (type EXCL) for CO4-PT-17-CTLFireability-2024-11 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 310 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 46 (type EXCL) for 45 CO4-PT-17-CTLFireability-2024-15
[[35mlola[0m][I] time limit : 299 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 34 (type EXCL) for 33 CO4-PT-17-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 3290 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 46 (type EXCL) for CO4-PT-17-CTLFireability-2024-15
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 39
[[35mlola[0m][I] fired transitions : 38
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 5/299 2/5 CO4-PT-17-CTLFireability-2024-11 375904 m, -3272710 m/sec, 1587602 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 315 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 10/299 4/5 CO4-PT-17-CTLFireability-2024-11 719538 m, 68726 m/sec, 3223627 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 320 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 34 (type EXCL) for CO4-PT-17-CTLFireability-2024-11 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 325 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 43 (type EXCL) for 42 CO4-PT-17-CTLFireability-2024-14
[[35mlola[0m][I] time limit : 327 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 5/327 3/2000 CO4-PT-17-CTLFireability-2024-14 476146 m, 95229 m/sec, 1859719 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 330 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 10/327 5/2000 CO4-PT-17-CTLFireability-2024-14 958846 m, 96540 m/sec, 3730946 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 335 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 15/327 6/2000 CO4-PT-17-CTLFireability-2024-14 1372347 m, 82700 m/sec, 5540635 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 340 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 20/327 8/2000 CO4-PT-17-CTLFireability-2024-14 1739684 m, 73467 m/sec, 7221046 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 345 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 25/327 9/2000 CO4-PT-17-CTLFireability-2024-14 2097035 m, 71470 m/sec, 8954364 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 350 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 30/327 11/2000 CO4-PT-17-CTLFireability-2024-14 2410939 m, 62780 m/sec, 10638260 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 355 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 35/327 12/2000 CO4-PT-17-CTLFireability-2024-14 2785275 m, 74867 m/sec, 12363884 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 360 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 40/327 14/2000 CO4-PT-17-CTLFireability-2024-14 3165494 m, 76043 m/sec, 14146572 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 365 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 45/327 16/2000 CO4-PT-17-CTLFireability-2024-14 3616353 m, 90171 m/sec, 15818275 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 370 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 50/327 18/2000 CO4-PT-17-CTLFireability-2024-14 4023719 m, 81473 m/sec, 17578677 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 375 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 55/327 20/2000 CO4-PT-17-CTLFireability-2024-14 4484550 m, 92166 m/sec, 19325710 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 380 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 60/327 22/2000 CO4-PT-17-CTLFireability-2024-14 4943239 m, 91737 m/sec, 20929538 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 385 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 65/327 24/2000 CO4-PT-17-CTLFireability-2024-14 5294999 m, 70352 m/sec, 22265816 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 390 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 70/327 26/2000 CO4-PT-17-CTLFireability-2024-14 5641633 m, 69326 m/sec, 23675854 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 395 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 75/327 27/2000 CO4-PT-17-CTLFireability-2024-14 5927165 m, 57106 m/sec, 25108181 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 400 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 80/327 28/2000 CO4-PT-17-CTLFireability-2024-14 6183762 m, 51319 m/sec, 26483079 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 405 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 85/327 29/2000 CO4-PT-17-CTLFireability-2024-14 6481475 m, 59542 m/sec, 27966484 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 410 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 90/327 31/2000 CO4-PT-17-CTLFireability-2024-14 6847290 m, 73163 m/sec, 29228829 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 415 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 95/327 32/2000 CO4-PT-17-CTLFireability-2024-14 7208170 m, 72176 m/sec, 30480155 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 420 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 100/327 34/2000 CO4-PT-17-CTLFireability-2024-14 7500525 m, 58471 m/sec, 31909567 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 425 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 105/327 35/2000 CO4-PT-17-CTLFireability-2024-14 7781560 m, 56207 m/sec, 33367032 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 430 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 110/327 36/2000 CO4-PT-17-CTLFireability-2024-14 8030471 m, 49782 m/sec, 34748639 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 435 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 115/327 37/2000 CO4-PT-17-CTLFireability-2024-14 8298828 m, 53671 m/sec, 36257560 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 440 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 120/327 38/2000 CO4-PT-17-CTLFireability-2024-14 8560285 m, 52291 m/sec, 37638874 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 445 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 125/327 39/2000 CO4-PT-17-CTLFireability-2024-14 8795522 m, 47047 m/sec, 38978186 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 450 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 130/327 41/2000 CO4-PT-17-CTLFireability-2024-14 9096928 m, 60281 m/sec, 40438131 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 455 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 135/327 42/2000 CO4-PT-17-CTLFireability-2024-14 9391668 m, 58948 m/sec, 41810082 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 460 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 140/327 43/2000 CO4-PT-17-CTLFireability-2024-14 9638688 m, 49404 m/sec, 43102217 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 465 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 145/327 44/2000 CO4-PT-17-CTLFireability-2024-14 9901303 m, 52523 m/sec, 44523346 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 470 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 150/327 45/2000 CO4-PT-17-CTLFireability-2024-14 10180756 m, 55890 m/sec, 45811634 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 475 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 155/327 46/2000 CO4-PT-17-CTLFireability-2024-14 10458817 m, 55612 m/sec, 47124591 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 480 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 160/327 47/2000 CO4-PT-17-CTLFireability-2024-14 10696698 m, 47576 m/sec, 48380157 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 485 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 165/327 48/2000 CO4-PT-17-CTLFireability-2024-14 10956538 m, 51968 m/sec, 49785051 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 490 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 170/327 50/2000 CO4-PT-17-CTLFireability-2024-14 11209763 m, 50645 m/sec, 51148706 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 495 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 175/327 51/2000 CO4-PT-17-CTLFireability-2024-14 11454926 m, 49032 m/sec, 52507002 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 500 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 180/327 52/2000 CO4-PT-17-CTLFireability-2024-14 11703371 m, 49689 m/sec, 53942608 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 505 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 185/327 53/2000 CO4-PT-17-CTLFireability-2024-14 11974161 m, 54158 m/sec, 55365259 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 510 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 190/327 54/2000 CO4-PT-17-CTLFireability-2024-14 12221525 m, 49472 m/sec, 56761137 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 515 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 195/327 55/2000 CO4-PT-17-CTLFireability-2024-14 12480136 m, 51722 m/sec, 58230441 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 520 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 200/327 56/2000 CO4-PT-17-CTLFireability-2024-14 12741666 m, 52306 m/sec, 59606233 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 525 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 205/327 57/2000 CO4-PT-17-CTLFireability-2024-14 12978701 m, 47407 m/sec, 60947016 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 530 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 210/327 59/2000 CO4-PT-17-CTLFireability-2024-14 13273933 m, 59046 m/sec, 62389389 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 535 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 215/327 60/2000 CO4-PT-17-CTLFireability-2024-14 13679743 m, 81162 m/sec, 64014544 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 540 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 220/327 62/2000 CO4-PT-17-CTLFireability-2024-14 14037513 m, 71554 m/sec, 65484479 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 545 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 225/327 64/2000 CO4-PT-17-CTLFireability-2024-14 14352231 m, 62943 m/sec, 66977763 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 550 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 230/327 65/2000 CO4-PT-17-CTLFireability-2024-14 14688386 m, 67231 m/sec, 68421523 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 555 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 235/327 67/2000 CO4-PT-17-CTLFireability-2024-14 15063427 m, 75008 m/sec, 69928864 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 560 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 240/327 68/2000 CO4-PT-17-CTLFireability-2024-14 15397785 m, 66871 m/sec, 71268625 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 565 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 245/327 70/2000 CO4-PT-17-CTLFireability-2024-14 15705293 m, 61501 m/sec, 72525845 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 570 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 250/327 71/2000 CO4-PT-17-CTLFireability-2024-14 16004219 m, 59785 m/sec, 73767074 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 575 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 255/327 73/2000 CO4-PT-17-CTLFireability-2024-14 16401797 m, 79515 m/sec, 75308766 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 580 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 260/327 74/2000 CO4-PT-17-CTLFireability-2024-14 16725633 m, 64767 m/sec, 76646649 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 585 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 265/327 76/2000 CO4-PT-17-CTLFireability-2024-14 17073032 m, 69479 m/sec, 78157733 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 590 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 270/327 78/2000 CO4-PT-17-CTLFireability-2024-14 17430835 m, 71560 m/sec, 79618551 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 595 secs. Pages in use: 78
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 275/327 79/2000 CO4-PT-17-CTLFireability-2024-14 17725973 m, 59027 m/sec, 80880689 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 600 secs. Pages in use: 79
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 280/327 80/2000 CO4-PT-17-CTLFireability-2024-14 18024561 m, 59717 m/sec, 82119126 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 605 secs. Pages in use: 80
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 285/327 82/2000 CO4-PT-17-CTLFireability-2024-14 18375515 m, 70190 m/sec, 83494963 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 610 secs. Pages in use: 82
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 290/327 83/2000 CO4-PT-17-CTLFireability-2024-14 18648695 m, 54636 m/sec, 84616628 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 615 secs. Pages in use: 83
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 295/327 84/2000 CO4-PT-17-CTLFireability-2024-14 18898287 m, 49918 m/sec, 85705761 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 620 secs. Pages in use: 84
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 300/327 86/2000 CO4-PT-17-CTLFireability-2024-14 19209161 m, 62174 m/sec, 87044771 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 625 secs. Pages in use: 86
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 305/327 87/2000 CO4-PT-17-CTLFireability-2024-14 19532941 m, 64756 m/sec, 88413366 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 630 secs. Pages in use: 87
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 310/327 88/2000 CO4-PT-17-CTLFireability-2024-14 19760505 m, 45512 m/sec, 89722894 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 635 secs. Pages in use: 88
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 315/327 90/2000 CO4-PT-17-CTLFireability-2024-14 20110228 m, 69944 m/sec, 91255468 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 640 secs. Pages in use: 90
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 320/327 92/2000 CO4-PT-17-CTLFireability-2024-14 20483929 m, 74740 m/sec, 92680500 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 645 secs. Pages in use: 92
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 325/327 94/2000 CO4-PT-17-CTLFireability-2024-14 20850502 m, 73314 m/sec, 94086362 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 650 secs. Pages in use: 94
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 43 (type EXCL) for CO4-PT-17-CTLFireability-2024-14 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 655 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 40 (type EXCL) for 39 CO4-PT-17-CTLFireability-2024-13
[[35mlola[0m][I] time limit : 327 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 43 (type EXCL) for 42 CO4-PT-17-CTLFireability-2024-14
[[35mlola[0m][I] time limit : 2945 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 40 (type EXCL) for CO4-PT-17-CTLFireability-2024-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 274
[[35mlola[0m][I] fired transitions : 644
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 5/327 3/5 CO4-PT-17-CTLFireability-2024-14 475887 m, -4074923 m/sec, 1858348 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 660 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 10/327 5/5 CO4-PT-17-CTLFireability-2024-14 954842 m, 95791 m/sec, 3712658 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 665 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 43 (type EXCL) for CO4-PT-17-CTLFireability-2024-14 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 670 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 37 (type EXCL) for 36 CO4-PT-17-CTLFireability-2024-12
[[35mlola[0m][I] time limit : 366 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 5/366 3/2000 CO4-PT-17-CTLFireability-2024-12 555844 m, 111168 m/sec, 1772127 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 675 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 10/366 5/2000 CO4-PT-17-CTLFireability-2024-12 1107403 m, 110311 m/sec, 3529488 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 680 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 15/366 7/2000 CO4-PT-17-CTLFireability-2024-12 1552355 m, 88990 m/sec, 5173210 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 685 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 20/366 9/2000 CO4-PT-17-CTLFireability-2024-12 1955375 m, 80604 m/sec, 6848542 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 690 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 25/366 10/2000 CO4-PT-17-CTLFireability-2024-12 2330877 m, 75100 m/sec, 8530384 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 695 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 30/366 12/2000 CO4-PT-17-CTLFireability-2024-12 2770530 m, 87930 m/sec, 10213403 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 700 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 35/366 14/2000 CO4-PT-17-CTLFireability-2024-12 3232792 m, 92452 m/sec, 11885372 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 705 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 40/366 17/2000 CO4-PT-17-CTLFireability-2024-12 3791680 m, 111777 m/sec, 13484573 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 710 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 45/366 18/2000 CO4-PT-17-CTLFireability-2024-12 4101795 m, 62023 m/sec, 14684799 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 715 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 37 (type EXCL) for CO4-PT-17-CTLFireability-2024-12
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 4248147
[[35mlola[0m][I] fired transitions : 15227994
[[35mlola[0m][I] time used : 47
[[35mlola[0m][I] memory pages used : 19
[[35mlola[0m][I] LAUNCH task # 31 (type EXCL) for 30 CO4-PT-17-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 411 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 3/411 2/2000 CO4-PT-17-CTLFireability-2024-10 330419 m, 66083 m/sec, 890744 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 720 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 8/411 4/2000 CO4-PT-17-CTLFireability-2024-10 922964 m, 118509 m/sec, 2665557 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 725 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 13/411 7/2000 CO4-PT-17-CTLFireability-2024-10 1444650 m, 104337 m/sec, 4393599 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 730 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 18/411 9/2000 CO4-PT-17-CTLFireability-2024-10 1901981 m, 91466 m/sec, 5997970 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 735 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 23/411 10/2000 CO4-PT-17-CTLFireability-2024-10 2304635 m, 80530 m/sec, 7647561 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 740 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 28/411 12/2000 CO4-PT-17-CTLFireability-2024-10 2755405 m, 90154 m/sec, 9314088 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 745 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 33/411 14/2000 CO4-PT-17-CTLFireability-2024-10 3228617 m, 94642 m/sec, 11026855 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 750 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 38/411 16/2000 CO4-PT-17-CTLFireability-2024-10 3589895 m, 72255 m/sec, 12221996 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 755 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 43/411 17/2000 CO4-PT-17-CTLFireability-2024-10 3791367 m, 40294 m/sec, 13340895 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 760 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 48/411 17/2000 CO4-PT-17-CTLFireability-2024-10 3895351 m, 20796 m/sec, 14755769 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 765 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 53/411 18/2000 CO4-PT-17-CTLFireability-2024-10 4067479 m, 34425 m/sec, 16490357 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 770 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 58/411 19/2000 CO4-PT-17-CTLFireability-2024-10 4235005 m, 33505 m/sec, 18218560 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 775 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 63/411 19/2000 CO4-PT-17-CTLFireability-2024-10 4415622 m, 36123 m/sec, 19829231 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 780 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 68/411 20/2000 CO4-PT-17-CTLFireability-2024-10 4621673 m, 41210 m/sec, 21506846 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 785 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 73/411 21/2000 CO4-PT-17-CTLFireability-2024-10 4848304 m, 45326 m/sec, 23204412 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 790 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 78/411 22/2000 CO4-PT-17-CTLFireability-2024-10 5014739 m, 33287 m/sec, 24965922 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 795 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 83/411 23/2000 CO4-PT-17-CTLFireability-2024-10 5195148 m, 36081 m/sec, 26644296 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 800 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 88/411 24/2000 CO4-PT-17-CTLFireability-2024-10 5352744 m, 31519 m/sec, 28287986 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 805 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 93/411 25/2000 CO4-PT-17-CTLFireability-2024-10 5508669 m, 31185 m/sec, 29894136 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 810 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 98/411 25/2000 CO4-PT-17-CTLFireability-2024-10 5656798 m, 29625 m/sec, 31473133 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 815 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 103/411 26/2000 CO4-PT-17-CTLFireability-2024-10 5807039 m, 30048 m/sec, 33006173 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 820 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 108/411 27/2000 CO4-PT-17-CTLFireability-2024-10 5934542 m, 25500 m/sec, 34484511 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 825 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 113/411 27/2000 CO4-PT-17-CTLFireability-2024-10 6069844 m, 27060 m/sec, 35996816 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 830 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 118/411 28/2000 CO4-PT-17-CTLFireability-2024-10 6209527 m, 27936 m/sec, 37564413 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 835 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 123/411 28/2000 CO4-PT-17-CTLFireability-2024-10 6349569 m, 28008 m/sec, 39176491 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 840 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 128/411 29/2000 CO4-PT-17-CTLFireability-2024-10 6486252 m, 27336 m/sec, 40807495 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 845 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 133/411 30/2000 CO4-PT-17-CTLFireability-2024-10 6622687 m, 27287 m/sec, 42485301 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 850 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 138/411 30/2000 CO4-PT-17-CTLFireability-2024-10 6775765 m, 30615 m/sec, 44335371 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 855 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 143/411 31/2000 CO4-PT-17-CTLFireability-2024-10 6956298 m, 36106 m/sec, 45854836 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 860 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 148/411 32/2000 CO4-PT-17-CTLFireability-2024-10 7110964 m, 30933 m/sec, 47234048 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 865 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 153/411 33/2000 CO4-PT-17-CTLFireability-2024-10 7234861 m, 24779 m/sec, 48435319 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 870 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 158/411 33/2000 CO4-PT-17-CTLFireability-2024-10 7360656 m, 25159 m/sec, 49804089 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 875 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 163/411 34/2000 CO4-PT-17-CTLFireability-2024-10 7513532 m, 30575 m/sec, 51311676 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 880 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 168/411 35/2000 CO4-PT-17-CTLFireability-2024-10 7654575 m, 28208 m/sec, 52729124 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 885 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 173/411 36/2000 CO4-PT-17-CTLFireability-2024-10 7787798 m, 26644 m/sec, 54112154 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 890 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 178/411 36/2000 CO4-PT-17-CTLFireability-2024-10 7895794 m, 21599 m/sec, 55338931 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 895 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 183/411 37/2000 CO4-PT-17-CTLFireability-2024-10 8006732 m, 22187 m/sec, 56667290 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 900 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 188/411 37/2000 CO4-PT-17-CTLFireability-2024-10 8124135 m, 23480 m/sec, 58124806 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 905 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 193/411 38/2000 CO4-PT-17-CTLFireability-2024-10 8273473 m, 29867 m/sec, 59673864 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 910 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 198/411 38/2000 CO4-PT-17-CTLFireability-2024-10 8404005 m, 26106 m/sec, 61154546 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 915 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 203/411 39/2000 CO4-PT-17-CTLFireability-2024-10 8521874 m, 23573 m/sec, 62495819 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 920 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 208/411 39/2000 CO4-PT-17-CTLFireability-2024-10 8629954 m, 21616 m/sec, 63780988 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 925 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 213/411 40/2000 CO4-PT-17-CTLFireability-2024-10 8739898 m, 21988 m/sec, 65213446 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 930 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 218/411 40/2000 CO4-PT-17-CTLFireability-2024-10 8870192 m, 26058 m/sec, 66767221 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 935 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 223/411 41/2000 CO4-PT-17-CTLFireability-2024-10 9014891 m, 28939 m/sec, 68291362 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 940 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 228/411 42/2000 CO4-PT-17-CTLFireability-2024-10 9142948 m, 25611 m/sec, 69725084 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 945 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 233/411 42/2000 CO4-PT-17-CTLFireability-2024-10 9249616 m, 21333 m/sec, 70987112 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 950 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 238/411 43/2000 CO4-PT-17-CTLFireability-2024-10 9356618 m, 21400 m/sec, 72305663 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 955 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 243/411 43/2000 CO4-PT-17-CTLFireability-2024-10 9472248 m, 23126 m/sec, 73799400 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 960 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 248/411 44/2000 CO4-PT-17-CTLFireability-2024-10 9615006 m, 28551 m/sec, 75380103 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 965 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 253/411 44/2000 CO4-PT-17-CTLFireability-2024-10 9764173 m, 29833 m/sec, 76811138 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 970 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 258/411 45/2000 CO4-PT-17-CTLFireability-2024-10 9869814 m, 21128 m/sec, 78194403 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 975 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 263/411 45/2000 CO4-PT-17-CTLFireability-2024-10 9974823 m, 21001 m/sec, 79445419 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 980 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 268/411 46/2000 CO4-PT-17-CTLFireability-2024-10 10085126 m, 22060 m/sec, 80842572 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 985 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 273/411 46/2000 CO4-PT-17-CTLFireability-2024-10 10202914 m, 23557 m/sec, 82356949 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 990 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 278/411 47/2000 CO4-PT-17-CTLFireability-2024-10 10355638 m, 30544 m/sec, 83864451 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 995 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 283/411 48/2000 CO4-PT-17-CTLFireability-2024-10 10488346 m, 26541 m/sec, 85289967 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1000 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 288/411 48/2000 CO4-PT-17-CTLFireability-2024-10 10589711 m, 20273 m/sec, 86597302 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1005 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 293/411 48/2000 CO4-PT-17-CTLFireability-2024-10 10696930 m, 21443 m/sec, 87857181 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1010 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 298/411 49/2000 CO4-PT-17-CTLFireability-2024-10 10805090 m, 21632 m/sec, 89268584 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1015 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 303/411 49/2000 CO4-PT-17-CTLFireability-2024-10 10940742 m, 27130 m/sec, 90790766 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1020 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 308/411 50/2000 CO4-PT-17-CTLFireability-2024-10 11077320 m, 27315 m/sec, 92275430 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1025 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 313/411 51/2000 CO4-PT-17-CTLFireability-2024-10 11201305 m, 24797 m/sec, 93682383 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1030 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 318/411 51/2000 CO4-PT-17-CTLFireability-2024-10 11305780 m, 20895 m/sec, 94924626 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1035 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 323/411 51/2000 CO4-PT-17-CTLFireability-2024-10 11413271 m, 21498 m/sec, 96225097 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1040 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 328/411 52/2000 CO4-PT-17-CTLFireability-2024-10 11526751 m, 22696 m/sec, 97704465 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1045 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 333/411 52/2000 CO4-PT-17-CTLFireability-2024-10 11665239 m, 27697 m/sec, 99251564 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1050 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 338/411 53/2000 CO4-PT-17-CTLFireability-2024-10 11801411 m, 27234 m/sec, 100653978 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1055 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 343/411 54/2000 CO4-PT-17-CTLFireability-2024-10 11916272 m, 22972 m/sec, 102033979 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1060 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 348/411 54/2000 CO4-PT-17-CTLFireability-2024-10 12016693 m, 20084 m/sec, 103218223 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1065 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 353/411 54/2000 CO4-PT-17-CTLFireability-2024-10 12123788 m, 21419 m/sec, 104550899 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1070 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 358/411 55/2000 CO4-PT-17-CTLFireability-2024-10 12237228 m, 22688 m/sec, 106012806 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1075 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 363/411 56/2000 CO4-PT-17-CTLFireability-2024-10 12397057 m, 31965 m/sec, 107416518 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1080 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 368/411 56/2000 CO4-PT-17-CTLFireability-2024-10 12549985 m, 30585 m/sec, 108695032 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1085 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 373/411 57/2000 CO4-PT-17-CTLFireability-2024-10 12662552 m, 22513 m/sec, 109833087 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1090 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 378/411 57/2000 CO4-PT-17-CTLFireability-2024-10 12777032 m, 22896 m/sec, 111009612 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1095 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 383/411 58/2000 CO4-PT-17-CTLFireability-2024-10 12901292 m, 24852 m/sec, 112361434 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1100 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 388/411 58/2000 CO4-PT-17-CTLFireability-2024-10 13062674 m, 32276 m/sec, 113754351 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1105 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 393/411 59/2000 CO4-PT-17-CTLFireability-2024-10 13212462 m, 29957 m/sec, 115038141 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1110 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 398/411 59/2000 CO4-PT-17-CTLFireability-2024-10 13331623 m, 23832 m/sec, 116180510 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1115 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 403/411 60/2000 CO4-PT-17-CTLFireability-2024-10 13446906 m, 23056 m/sec, 117328269 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1120 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 408/411 60/2000 CO4-PT-17-CTLFireability-2024-10 13566221 m, 23863 m/sec, 118634611 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1125 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 31 (type EXCL) for CO4-PT-17-CTLFireability-2024-10 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1130 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 13 (type EXCL) for 12 CO4-PT-17-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 411 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 31 (type EXCL) for 30 CO4-PT-17-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 2470 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 5/411 2/2000 CO4-PT-17-CTLFireability-2024-04 290261 m, 58052 m/sec, 1713993 t fired, .
[[35mlola[0m][.] 31 CTL EXCL 5/2470 3/5 CO4-PT-17-CTLFireability-2024-10 586266 m, -2595991 m/sec, 1750780 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1135 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 10/411 3/2000 CO4-PT-17-CTLFireability-2024-04 531718 m, 48291 m/sec, 3368720 t fired, .
[[35mlola[0m][.] 31 CTL EXCL 10/352 5/5 CO4-PT-17-CTLFireability-2024-10 1161283 m, 115003 m/sec, 3468736 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1140 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 31 (type EXCL) for CO4-PT-17-CTLFireability-2024-10 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 15/411 4/2000 CO4-PT-17-CTLFireability-2024-04 795913 m, 52839 m/sec, 5115623 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1145 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 20/411 6/2000 CO4-PT-17-CTLFireability-2024-04 1077941 m, 56405 m/sec, 6794996 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1150 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 25/411 7/2000 CO4-PT-17-CTLFireability-2024-04 1368262 m, 58064 m/sec, 8393490 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1155 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 30/411 8/2000 CO4-PT-17-CTLFireability-2024-04 1664608 m, 59269 m/sec, 10065049 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1160 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 35/411 9/2000 CO4-PT-17-CTLFireability-2024-04 1933471 m, 53772 m/sec, 11715436 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1165 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 40/411 11/2000 CO4-PT-17-CTLFireability-2024-04 2204489 m, 54203 m/sec, 13328499 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1170 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 45/411 12/2000 CO4-PT-17-CTLFireability-2024-04 2475308 m, 54163 m/sec, 15010754 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1175 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 50/411 13/2000 CO4-PT-17-CTLFireability-2024-04 2738709 m, 52680 m/sec, 16615192 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1180 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 55/411 14/2000 CO4-PT-17-CTLFireability-2024-04 2969140 m, 46086 m/sec, 18157973 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1185 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 60/411 15/2000 CO4-PT-17-CTLFireability-2024-04 3202798 m, 46731 m/sec, 19815021 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1190 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 65/411 16/2000 CO4-PT-17-CTLFireability-2024-04 3449713 m, 49383 m/sec, 21527619 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1195 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 70/411 18/2000 CO4-PT-17-CTLFireability-2024-04 3704290 m, 50915 m/sec, 23370886 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1200 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 75/411 19/2000 CO4-PT-17-CTLFireability-2024-04 3982056 m, 55553 m/sec, 24872679 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1205 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 80/411 20/2000 CO4-PT-17-CTLFireability-2024-04 4189800 m, 41548 m/sec, 26085525 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1210 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 85/411 21/2000 CO4-PT-17-CTLFireability-2024-04 4417724 m, 45584 m/sec, 27531425 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1215 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 90/411 22/2000 CO4-PT-17-CTLFireability-2024-04 4636859 m, 43827 m/sec, 28931906 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1220 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 95/411 23/2000 CO4-PT-17-CTLFireability-2024-04 4819886 m, 36605 m/sec, 30161427 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1225 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 100/411 24/2000 CO4-PT-17-CTLFireability-2024-04 5008668 m, 37756 m/sec, 31527452 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1230 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 105/411 25/2000 CO4-PT-17-CTLFireability-2024-04 5232098 m, 44686 m/sec, 33008700 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1235 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 110/411 26/2000 CO4-PT-17-CTLFireability-2024-04 5433093 m, 40199 m/sec, 34341262 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1240 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 115/411 27/2000 CO4-PT-17-CTLFireability-2024-04 5612496 m, 35880 m/sec, 35603419 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1245 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 120/411 28/2000 CO4-PT-17-CTLFireability-2024-04 5822936 m, 42088 m/sec, 37081499 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1250 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 125/411 29/2000 CO4-PT-17-CTLFireability-2024-04 6041418 m, 43696 m/sec, 38483644 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1255 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 130/411 30/2000 CO4-PT-17-CTLFireability-2024-04 6221169 m, 35950 m/sec, 39705922 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1260 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 135/411 30/2000 CO4-PT-17-CTLFireability-2024-04 6410849 m, 37936 m/sec, 41104558 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1265 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 140/411 31/2000 CO4-PT-17-CTLFireability-2024-04 6631864 m, 44203 m/sec, 42530854 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1270 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 145/411 32/2000 CO4-PT-17-CTLFireability-2024-04 6823427 m, 38312 m/sec, 43810616 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1275 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 150/411 33/2000 CO4-PT-17-CTLFireability-2024-04 7008685 m, 37051 m/sec, 45128832 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1280 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 155/411 34/2000 CO4-PT-17-CTLFireability-2024-04 7227331 m, 43729 m/sec, 46629606 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1285 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 160/411 35/2000 CO4-PT-17-CTLFireability-2024-04 7443039 m, 43141 m/sec, 48030169 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1290 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 165/411 36/2000 CO4-PT-17-CTLFireability-2024-04 7622782 m, 35948 m/sec, 49264288 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1295 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 170/411 36/2000 CO4-PT-17-CTLFireability-2024-04 7823125 m, 40068 m/sec, 50736603 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1300 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 175/411 37/2000 CO4-PT-17-CTLFireability-2024-04 8046701 m, 44715 m/sec, 52165423 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1305 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 180/411 38/2000 CO4-PT-17-CTLFireability-2024-04 8237401 m, 38140 m/sec, 53442635 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1310 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 185/411 39/2000 CO4-PT-17-CTLFireability-2024-04 8425548 m, 37629 m/sec, 54796973 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1315 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 190/411 40/2000 CO4-PT-17-CTLFireability-2024-04 8648724 m, 44635 m/sec, 56280423 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1320 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 195/411 41/2000 CO4-PT-17-CTLFireability-2024-04 8850332 m, 40321 m/sec, 57616719 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1325 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 200/411 41/2000 CO4-PT-17-CTLFireability-2024-04 9026491 m, 35231 m/sec, 58847480 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1330 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 205/411 42/2000 CO4-PT-17-CTLFireability-2024-04 9237737 m, 42249 m/sec, 60294036 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1335 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 210/411 43/2000 CO4-PT-17-CTLFireability-2024-04 9484482 m, 49349 m/sec, 61634925 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1340 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 215/411 44/2000 CO4-PT-17-CTLFireability-2024-04 9682960 m, 39695 m/sec, 62812752 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1345 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 220/411 45/2000 CO4-PT-17-CTLFireability-2024-04 9908385 m, 45085 m/sec, 64196142 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1350 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 225/411 46/2000 CO4-PT-17-CTLFireability-2024-04 10153431 m, 49009 m/sec, 65532533 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1355 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 230/411 47/2000 CO4-PT-17-CTLFireability-2024-04 10357465 m, 40806 m/sec, 66715051 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1360 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 235/411 48/2000 CO4-PT-17-CTLFireability-2024-04 10569724 m, 42451 m/sec, 68068936 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1365 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 240/411 49/2000 CO4-PT-17-CTLFireability-2024-04 10786211 m, 43297 m/sec, 69447014 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1370 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 245/411 50/2000 CO4-PT-17-CTLFireability-2024-04 10969568 m, 36671 m/sec, 70674075 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1375 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 250/411 50/2000 CO4-PT-17-CTLFireability-2024-04 11147949 m, 35676 m/sec, 71960942 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1380 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 255/411 51/2000 CO4-PT-17-CTLFireability-2024-04 11377490 m, 45908 m/sec, 73366743 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1385 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 260/411 52/2000 CO4-PT-17-CTLFireability-2024-04 11599781 m, 44458 m/sec, 74609268 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1390 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 265/411 53/2000 CO4-PT-17-CTLFireability-2024-04 11793533 m, 38750 m/sec, 75790373 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1395 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 270/411 54/2000 CO4-PT-17-CTLFireability-2024-04 12012498 m, 43793 m/sec, 77166376 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1400 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 275/411 55/2000 CO4-PT-17-CTLFireability-2024-04 12217698 m, 41040 m/sec, 78486255 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1405 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 280/411 56/2000 CO4-PT-17-CTLFireability-2024-04 12386663 m, 33793 m/sec, 79638251 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1410 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 285/411 56/2000 CO4-PT-17-CTLFireability-2024-04 12563529 m, 35373 m/sec, 80940079 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1415 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 290/411 57/2000 CO4-PT-17-CTLFireability-2024-04 12764501 m, 40194 m/sec, 82245944 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1420 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 295/411 58/2000 CO4-PT-17-CTLFireability-2024-04 12936959 m, 34491 m/sec, 83318187 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1425 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 300/411 59/2000 CO4-PT-17-CTLFireability-2024-04 13181838 m, 48975 m/sec, 84737744 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1430 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 305/411 60/2000 CO4-PT-17-CTLFireability-2024-04 13433893 m, 50411 m/sec, 86293951 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1435 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 310/411 61/2000 CO4-PT-17-CTLFireability-2024-04 13683307 m, 49882 m/sec, 87914062 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1440 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 315/411 63/2000 CO4-PT-17-CTLFireability-2024-04 13922376 m, 47813 m/sec, 89488591 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1445 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 320/411 64/2000 CO4-PT-17-CTLFireability-2024-04 14153482 m, 46221 m/sec, 91074344 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1450 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 325/411 65/2000 CO4-PT-17-CTLFireability-2024-04 14380204 m, 45344 m/sec, 92495062 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1455 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 330/411 65/2000 CO4-PT-17-CTLFireability-2024-04 14520941 m, 28147 m/sec, 93458141 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1460 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 335/411 66/2000 CO4-PT-17-CTLFireability-2024-04 14712838 m, 38379 m/sec, 94700826 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1465 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 340/411 67/2000 CO4-PT-17-CTLFireability-2024-04 14937705 m, 44973 m/sec, 96195674 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1470 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 345/411 68/2000 CO4-PT-17-CTLFireability-2024-04 15186706 m, 49800 m/sec, 97680448 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1475 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 350/411 69/2000 CO4-PT-17-CTLFireability-2024-04 15415521 m, 45763 m/sec, 99232740 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1480 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 355/411 71/2000 CO4-PT-17-CTLFireability-2024-04 15650267 m, 46949 m/sec, 100745682 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1485 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 360/411 72/2000 CO4-PT-17-CTLFireability-2024-04 15892194 m, 48385 m/sec, 102264997 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1490 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 365/411 73/2000 CO4-PT-17-CTLFireability-2024-04 16110981 m, 43757 m/sec, 103740693 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1495 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 370/411 74/2000 CO4-PT-17-CTLFireability-2024-04 16301884 m, 38180 m/sec, 104980737 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1500 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 375/411 75/2000 CO4-PT-17-CTLFireability-2024-04 16512993 m, 42221 m/sec, 106399574 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1505 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 380/411 76/2000 CO4-PT-17-CTLFireability-2024-04 16738562 m, 45113 m/sec, 107839601 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1510 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 385/411 77/2000 CO4-PT-17-CTLFireability-2024-04 16972425 m, 46772 m/sec, 109342080 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1515 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 390/411 78/2000 CO4-PT-17-CTLFireability-2024-04 17190383 m, 43591 m/sec, 110811578 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1520 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 395/411 79/2000 CO4-PT-17-CTLFireability-2024-04 17422157 m, 46354 m/sec, 112205327 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1525 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 400/411 80/2000 CO4-PT-17-CTLFireability-2024-04 17659992 m, 47567 m/sec, 113609040 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1530 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 405/411 81/2000 CO4-PT-17-CTLFireability-2024-04 17881892 m, 44380 m/sec, 115079891 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1535 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 410/411 82/2000 CO4-PT-17-CTLFireability-2024-04 18103782 m, 44378 m/sec, 116577067 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1540 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 13 (type EXCL) for CO4-PT-17-CTLFireability-2024-04 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1545 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 10 (type EXCL) for 9 CO4-PT-17-CTLFireability-2024-03
[[35mlola[0m][I] time limit : 411 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 13 (type EXCL) for 12 CO4-PT-17-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 2055 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 5/411 2/2000 CO4-PT-17-CTLFireability-2024-03 288129 m, 57625 m/sec, 1696887 t fired, .
[[35mlola[0m][.] 13 CTL EXCL 5/2055 2/5 CO4-PT-17-CTLFireability-2024-04 290984 m, -3562559 m/sec, 1718844 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1550 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 10/411 3/2000 CO4-PT-17-CTLFireability-2024-03 534706 m, 49315 m/sec, 3385249 t fired, .
[[35mlola[0m][.] 13 CTL EXCL 10/342 3/5 CO4-PT-17-CTLFireability-2024-04 537345 m, 49272 m/sec, 3411538 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1555 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 10 (type EXCL) for CO4-PT-17-CTLFireability-2024-03
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 638531
[[35mlola[0m][I] fired transitions : 4156225
[[35mlola[0m][I] time used : 12
[[35mlola[0m][I] memory pages used : 3
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 15/411 4/5 CO4-PT-17-CTLFireability-2024-04 814623 m, 55455 m/sec, 5217908 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1560 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 13 (type EXCL) for CO4-PT-17-CTLFireability-2024-04 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1565 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 7 (type EXCL) for 6 CO4-PT-17-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 508 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 5/508 2/2000 CO4-PT-17-CTLFireability-2024-02 338700 m, 67740 m/sec, 1718903 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1570 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 10/508 3/2000 CO4-PT-17-CTLFireability-2024-02 621064 m, 56472 m/sec, 3406479 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1575 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 15/508 5/2000 CO4-PT-17-CTLFireability-2024-02 973483 m, 70483 m/sec, 5174262 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1580 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 20/508 7/2000 CO4-PT-17-CTLFireability-2024-02 1314637 m, 68230 m/sec, 6749644 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1585 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 25/508 8/2000 CO4-PT-17-CTLFireability-2024-02 1657326 m, 68537 m/sec, 8334339 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1590 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 30/508 10/2000 CO4-PT-17-CTLFireability-2024-02 1966106 m, 61756 m/sec, 9924982 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1595 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 35/508 11/2000 CO4-PT-17-CTLFireability-2024-02 2269484 m, 60675 m/sec, 11454049 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1600 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 40/508 12/2000 CO4-PT-17-CTLFireability-2024-02 2551211 m, 56345 m/sec, 12922285 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1605 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 45/508 13/2000 CO4-PT-17-CTLFireability-2024-02 2820115 m, 53780 m/sec, 14316441 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1610 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 50/508 15/2000 CO4-PT-17-CTLFireability-2024-02 3060622 m, 48101 m/sec, 15690887 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1615 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 55/508 16/2000 CO4-PT-17-CTLFireability-2024-02 3321488 m, 52173 m/sec, 17212234 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1620 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 60/508 17/2000 CO4-PT-17-CTLFireability-2024-02 3594499 m, 54602 m/sec, 18880814 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1625 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 65/508 19/2000 CO4-PT-17-CTLFireability-2024-02 3899883 m, 61076 m/sec, 20398491 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1630 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 70/508 20/2000 CO4-PT-17-CTLFireability-2024-02 4150924 m, 50208 m/sec, 21586653 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1635 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 75/508 21/2000 CO4-PT-17-CTLFireability-2024-02 4410251 m, 51865 m/sec, 22944002 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1640 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 80/508 22/2000 CO4-PT-17-CTLFireability-2024-02 4659720 m, 49893 m/sec, 24278006 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1645 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 85/508 23/2000 CO4-PT-17-CTLFireability-2024-02 4866374 m, 41330 m/sec, 25461091 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1650 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 90/508 24/2000 CO4-PT-17-CTLFireability-2024-02 5105434 m, 47812 m/sec, 26945378 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1655 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 95/508 26/2000 CO4-PT-17-CTLFireability-2024-02 5372572 m, 53427 m/sec, 28382477 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1660 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 100/508 27/2000 CO4-PT-17-CTLFireability-2024-02 5588169 m, 43119 m/sec, 29654381 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1665 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 105/508 28/2000 CO4-PT-17-CTLFireability-2024-02 5839772 m, 50320 m/sec, 31161956 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1670 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 110/508 29/2000 CO4-PT-17-CTLFireability-2024-02 6077500 m, 47545 m/sec, 32460129 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1675 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 115/508 30/2000 CO4-PT-17-CTLFireability-2024-02 6270571 m, 38614 m/sec, 33592961 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1680 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 120/508 31/2000 CO4-PT-17-CTLFireability-2024-02 6501831 m, 46252 m/sec, 34993637 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1685 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 125/508 32/2000 CO4-PT-17-CTLFireability-2024-02 6750750 m, 49783 m/sec, 36342387 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1690 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 130/508 33/2000 CO4-PT-17-CTLFireability-2024-02 6955393 m, 40928 m/sec, 37543220 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1695 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 135/508 34/2000 CO4-PT-17-CTLFireability-2024-02 7185097 m, 45940 m/sec, 38939286 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1700 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 140/508 35/2000 CO4-PT-17-CTLFireability-2024-02 7438325 m, 50645 m/sec, 40311983 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1705 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 145/508 36/2000 CO4-PT-17-CTLFireability-2024-02 7636485 m, 39632 m/sec, 41475495 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1710 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 150/508 37/2000 CO4-PT-17-CTLFireability-2024-02 7880140 m, 48731 m/sec, 42951726 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1715 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 155/508 38/2000 CO4-PT-17-CTLFireability-2024-02 8137382 m, 51448 m/sec, 44349064 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1720 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 160/508 39/2000 CO4-PT-17-CTLFireability-2024-02 8344553 m, 41434 m/sec, 45574998 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1725 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 165/508 40/2000 CO4-PT-17-CTLFireability-2024-02 8584266 m, 47942 m/sec, 47006550 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1730 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 170/508 41/2000 CO4-PT-17-CTLFireability-2024-02 8825688 m, 48284 m/sec, 48329911 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1735 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 175/508 41/2000 CO4-PT-17-CTLFireability-2024-02 9024093 m, 39681 m/sec, 49496417 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1740 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 180/508 42/2000 CO4-PT-17-CTLFireability-2024-02 9269806 m, 49142 m/sec, 50882648 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1745 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 185/508 44/2000 CO4-PT-17-CTLFireability-2024-02 9528651 m, 51769 m/sec, 52052945 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1750 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 190/508 44/2000 CO4-PT-17-CTLFireability-2024-02 9755613 m, 45392 m/sec, 53193126 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1755 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 195/508 46/2000 CO4-PT-17-CTLFireability-2024-02 10039335 m, 56744 m/sec, 54511969 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1760 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 200/508 47/2000 CO4-PT-17-CTLFireability-2024-02 10287669 m, 49666 m/sec, 55678475 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1765 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 205/508 48/2000 CO4-PT-17-CTLFireability-2024-02 10529720 m, 48410 m/sec, 56930395 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1770 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 210/508 49/2000 CO4-PT-17-CTLFireability-2024-02 10781755 m, 50407 m/sec, 58261348 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1775 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 215/508 50/2000 CO4-PT-17-CTLFireability-2024-02 10987137 m, 41076 m/sec, 59437843 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1780 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 220/508 51/2000 CO4-PT-17-CTLFireability-2024-02 11192087 m, 40990 m/sec, 60710419 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1785 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 225/508 52/2000 CO4-PT-17-CTLFireability-2024-02 11466292 m, 54841 m/sec, 61996794 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1790 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 230/508 53/2000 CO4-PT-17-CTLFireability-2024-02 11705510 m, 47843 m/sec, 63123870 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1795 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 235/508 54/2000 CO4-PT-17-CTLFireability-2024-02 11942242 m, 47346 m/sec, 64378068 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1800 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 240/508 55/2000 CO4-PT-17-CTLFireability-2024-02 12183479 m, 48247 m/sec, 65674150 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1805 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 245/508 56/2000 CO4-PT-17-CTLFireability-2024-02 12381131 m, 39530 m/sec, 66798002 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1810 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 250/508 56/2000 CO4-PT-17-CTLFireability-2024-02 12583074 m, 40388 m/sec, 68071265 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1815 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 255/508 57/2000 CO4-PT-17-CTLFireability-2024-02 12802879 m, 43961 m/sec, 69282797 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1820 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 260/508 58/2000 CO4-PT-17-CTLFireability-2024-02 13028531 m, 45130 m/sec, 70401296 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1825 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 265/508 60/2000 CO4-PT-17-CTLFireability-2024-02 13345037 m, 63301 m/sec, 71918035 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1830 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 270/508 61/2000 CO4-PT-17-CTLFireability-2024-02 13620320 m, 55056 m/sec, 73443353 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1835 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 275/508 62/2000 CO4-PT-17-CTLFireability-2024-02 13903826 m, 56701 m/sec, 75006076 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1840 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 280/508 64/2000 CO4-PT-17-CTLFireability-2024-02 14166572 m, 52549 m/sec, 76530214 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1845 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 285/508 65/2000 CO4-PT-17-CTLFireability-2024-02 14411434 m, 48972 m/sec, 77848963 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1850 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 290/508 66/2000 CO4-PT-17-CTLFireability-2024-02 14569804 m, 31674 m/sec, 78766348 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1855 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 295/508 67/2000 CO4-PT-17-CTLFireability-2024-02 14827568 m, 51552 m/sec, 80142416 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1860 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 300/508 68/2000 CO4-PT-17-CTLFireability-2024-02 15103671 m, 55220 m/sec, 81574717 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1865 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 305/508 69/2000 CO4-PT-17-CTLFireability-2024-02 15377613 m, 54788 m/sec, 83102409 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1870 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 310/508 70/2000 CO4-PT-17-CTLFireability-2024-02 15637969 m, 52071 m/sec, 84550770 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1875 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 315/508 72/2000 CO4-PT-17-CTLFireability-2024-02 15921593 m, 56724 m/sec, 86042261 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1880 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 320/508 73/2000 CO4-PT-17-CTLFireability-2024-02 16156169 m, 46915 m/sec, 87395633 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1885 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 325/508 74/2000 CO4-PT-17-CTLFireability-2024-02 16393531 m, 47472 m/sec, 88696339 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1890 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 330/508 75/2000 CO4-PT-17-CTLFireability-2024-02 16615913 m, 44476 m/sec, 90040208 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1895 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 335/508 76/2000 CO4-PT-17-CTLFireability-2024-02 16899204 m, 56658 m/sec, 91469741 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1900 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 340/508 78/2000 CO4-PT-17-CTLFireability-2024-02 17161046 m, 52368 m/sec, 92931434 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1905 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 345/508 79/2000 CO4-PT-17-CTLFireability-2024-02 17424283 m, 52647 m/sec, 94292241 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1910 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 350/508 80/2000 CO4-PT-17-CTLFireability-2024-02 17697812 m, 54705 m/sec, 95669093 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1915 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 355/508 81/2000 CO4-PT-17-CTLFireability-2024-02 17966867 m, 53811 m/sec, 97158319 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1920 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 360/508 82/2000 CO4-PT-17-CTLFireability-2024-02 18208409 m, 48308 m/sec, 98582279 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1925 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 365/508 83/2000 CO4-PT-17-CTLFireability-2024-02 18435528 m, 45423 m/sec, 99933218 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1930 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 370/508 85/2000 CO4-PT-17-CTLFireability-2024-02 18670600 m, 47014 m/sec, 101237988 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1935 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 375/508 86/2000 CO4-PT-17-CTLFireability-2024-02 18930567 m, 51993 m/sec, 102592237 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1940 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 380/508 87/2000 CO4-PT-17-CTLFireability-2024-02 19187609 m, 51408 m/sec, 103959950 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1945 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 385/508 88/2000 CO4-PT-17-CTLFireability-2024-02 19416672 m, 45812 m/sec, 105303294 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1950 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 390/508 89/2000 CO4-PT-17-CTLFireability-2024-02 19640292 m, 44724 m/sec, 106598456 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1955 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 395/508 90/2000 CO4-PT-17-CTLFireability-2024-02 19875019 m, 46945 m/sec, 107849817 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1960 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 400/508 91/2000 CO4-PT-17-CTLFireability-2024-02 20109093 m, 46814 m/sec, 109240644 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1965 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 405/508 92/2000 CO4-PT-17-CTLFireability-2024-02 20337947 m, 45770 m/sec, 110494789 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1970 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 410/508 93/2000 CO4-PT-17-CTLFireability-2024-02 20595252 m, 51461 m/sec, 111963556 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1975 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 415/508 94/2000 CO4-PT-17-CTLFireability-2024-02 20791722 m, 39294 m/sec, 113235928 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1980 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 420/508 95/2000 CO4-PT-17-CTLFireability-2024-02 20979031 m, 37461 m/sec, 114469316 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1985 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 425/508 96/2000 CO4-PT-17-CTLFireability-2024-02 21141390 m, 32471 m/sec, 115776862 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1990 secs. Pages in use: 96
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 430/508 97/2000 CO4-PT-17-CTLFireability-2024-02 21333429 m, 38407 m/sec, 117141679 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1995 secs. Pages in use: 97
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 435/508 98/2000 CO4-PT-17-CTLFireability-2024-02 21552556 m, 43825 m/sec, 118601787 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2000 secs. Pages in use: 98
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 440/508 99/2000 CO4-PT-17-CTLFireability-2024-02 21737038 m, 36896 m/sec, 119873181 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2005 secs. Pages in use: 99
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 445/508 100/2000 CO4-PT-17-CTLFireability-2024-02 21959343 m, 44461 m/sec, 121262018 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2010 secs. Pages in use: 100
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 450/508 101/2000 CO4-PT-17-CTLFireability-2024-02 22168053 m, 41742 m/sec, 122538491 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2015 secs. Pages in use: 101
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 455/508 102/2000 CO4-PT-17-CTLFireability-2024-02 22421021 m, 50593 m/sec, 123811358 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2020 secs. Pages in use: 102
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 460/508 103/2000 CO4-PT-17-CTLFireability-2024-02 22681346 m, 52065 m/sec, 125249564 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2025 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 465/508 104/2000 CO4-PT-17-CTLFireability-2024-02 22942448 m, 52220 m/sec, 126546759 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2030 secs. Pages in use: 104
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 470/508 105/2000 CO4-PT-17-CTLFireability-2024-02 23183907 m, 48291 m/sec, 127890393 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2035 secs. Pages in use: 105
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 475/508 107/2000 CO4-PT-17-CTLFireability-2024-02 23424944 m, 48207 m/sec, 129203283 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2040 secs. Pages in use: 107
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 480/508 108/2000 CO4-PT-17-CTLFireability-2024-02 23635423 m, 42095 m/sec, 130492748 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2045 secs. Pages in use: 108
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 485/508 109/2000 CO4-PT-17-CTLFireability-2024-02 23877471 m, 48409 m/sec, 131824974 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2050 secs. Pages in use: 109
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 490/508 110/2000 CO4-PT-17-CTLFireability-2024-02 24150027 m, 54511 m/sec, 133114365 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2055 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 495/508 111/2000 CO4-PT-17-CTLFireability-2024-02 24387882 m, 47571 m/sec, 134387187 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2060 secs. Pages in use: 111
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 500/508 112/2000 CO4-PT-17-CTLFireability-2024-02 24629846 m, 48392 m/sec, 135696889 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2065 secs. Pages in use: 112
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 505/508 113/2000 CO4-PT-17-CTLFireability-2024-02 24849349 m, 43900 m/sec, 136920868 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2070 secs. Pages in use: 113
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 7 (type EXCL) for CO4-PT-17-CTLFireability-2024-02 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2075 secs. Pages in use: 114
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 4 (type EXCL) for 3 CO4-PT-17-CTLFireability-2024-01
[[35mlola[0m][I] time limit : 508 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 7 (type EXCL) for 6 CO4-PT-17-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 1525 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 4 (type EXCL) for CO4-PT-17-CTLFireability-2024-01
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 274
[[35mlola[0m][I] fired transitions : 644
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 5/508 2/5 CO4-PT-17-CTLFireability-2024-02 336554 m, -4902559 m/sec, 1704448 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2080 secs. Pages in use: 114
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 10/508 3/5 CO4-PT-17-CTLFireability-2024-02 617668 m, 56222 m/sec, 3386016 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2085 secs. Pages in use: 114
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 15/508 5/5 CO4-PT-17-CTLFireability-2024-02 972421 m, 70950 m/sec, 5169338 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2090 secs. Pages in use: 114
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 7 (type EXCL) for CO4-PT-17-CTLFireability-2024-02 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-06: AG false findpath[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-17-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-17-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CO4-PT-17-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2095 secs. Pages in use: 114
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 53 (type EXCL) for 24 CO4-PT-17-CTLFireability-2024-08
[[35mlola[0m][I] time limit : 752 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 53 (type EXCL) for CO4-PT-17-CTLFireability-2024-08
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 11
[[35mlola[0m][I] fired transitions : 11
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 28 (type EXCL) for 27 CO4-PT-17-CTLFireability-2024-09
[[35mlola[0m][I] time limit : 1505 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 28 (type EXCL) for CO4-PT-17-CTLFireability-2024-09
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 14
[[35mlola[0m][I] fired transitions : 13
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] Portfolio finished: no open tasks 16
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="CO4-PT-17"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is CO4-PT-17, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r551-tall-171734899400130"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/CO4-PT-17.tgz
mv CO4-PT-17 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;