MCC'2024- Execution of r551-tall-171734899400116

About the Execution of LoLA for CO4-PT-15

Execution Summary
Max Memory Used (MB)	Time wait (ms)	CPU Usage (ms)	I/O Wait (ms)	Computed Result	Execution Status
16207.188	1279846.00	2072809.00	4346.10	[undef]	Cannot compute

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r551-tall-17173
Waiting for the VM to be ready (probing ssh)
.................................................
===========================
Generated by BenchKit 2-5568
Executing tool lola
Input is CO4-PT-15, examination is LTLFireabi
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r551-tall-171734899400116
=================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 608K
-rw-r--r-- 1 mcc users 5.8K Jun 2 17:16
-rw-r--r-- 1 mcc users 60K Jun 2 17:16
-rw-r--r-- 1 mcc users 4.5K Jun 2 17:16
-rw-r--r-- 1 mcc users 39K Jun 2 17:16
-rw-r--r-- 1 mcc users 3.6K Jun 2 17:12
-rw-r--r-- 1 mcc users 26K Jun 2 17:12
-rw-r--r-- 1 mcc users 2.1K Jun 2 17:12
-rw-r--r-- 1 mcc users 17K Jun 2 17:12
-rw-r--r-- 1 mcc users 1 Jun 2 16:33 NewModel
-rw-r--r-- 1 mcc users 6.7K Jun 2 17:16
-rw-r--r-- 1 mcc users 64K Jun 2 17:16
-rw-r--r-- 1 mcc users 8.2K Jun 2 17:16
-rw-r--r-- 1 mcc users 71K Jun 2 17:16
-rw-r--r-- 1 mcc users 1.5K Jun 2 17:12
-rw-r--r-- 1 mcc users 3.5K Jun 2 17:12
-rw-r--r-- 1 mcc users 6 Jun 2 16:33
-rw-r--r-- 1 mcc users 3 Jun 2 16:33 instance
-rw-r--r-- 1 mcc users 6 Jun 2 16:33
-rw-r--r-- 1 mcc users 255K Jun 2 16:33

--------------------
content from stdout:

=== Data for post analysis generated by

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result
FORMULA_NAME CO4-PT-15-LTLFireability-00
FORMULA_NAME CO4-PT-15-LTLFireability-01
FORMULA_NAME CO4-PT-15-LTLFireability-02
FORMULA_NAME CO4-PT-15-LTLFireability-03
FORMULA_NAME CO4-PT-15-LTLFireability-04
FORMULA_NAME CO4-PT-15-LTLFireability-05
FORMULA_NAME CO4-PT-15-LTLFireability-06
FORMULA_NAME CO4-PT-15-LTLFireability-07
FORMULA_NAME CO4-PT-15-LTLFireability-08
FORMULA_NAME CO4-PT-15-LTLFireability-09
FORMULA_NAME CO4-PT-15-LTLFireability-10
FORMULA_NAME CO4-PT-15-LTLFireability-11
FORMULA_NAME CO4-PT-15-LTLFireability-12
FORMULA_NAME CO4-PT-15-LTLFireability-13
FORMULA_NAME CO4-PT-15-LTLFireability-14
FORMULA_NAME CO4-PT-15-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1717403628397

BK_STOP 1717404908243

--------------------
content from stderr:

[[35mlola[0m][I] LoLA will run for 3600
[[35mlola[0m][W] [1m[33munknown unit
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m
[[35mlola[0m][I] input: PNML file ([1m[36m-
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains
[[35mlola[0m][I] closed [1m[34mnet[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m-
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m
[[35mlola[0m][I] Rule S: 197 transitions
[[35mlola[0m][I] LAUNCH task # 51 (type
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 51
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 33 (type
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] LAUNCH task # 22 (type
[[35mlola[0m][I] time limit : 189 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 33
[[35mlola[0m][I] result : false
[[35mlola[0m][I] FINISHED task # 22
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings :
[[35mlola[0m][I] fired transitions :
[[35mlola[0m][I] time used :
[[35mlola[0m][I] memory pages used :
[[35mlola[0m][I] LAUNCH task # 48 (type
[[35mlola[0m][I] time limit : 276 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 48
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings :
[[35mlola[0m][I] fired transitions :
[[35mlola[0m][I] time used :
[[35mlola[0m][I] memory pages used :
[[35mlola[0m][I] LAUNCH task # 54 (type
[[35mlola[0m][I] time limit : 300 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mCO4-PT-15-LTLFireability-07:
[[35mlola[0m][.] [1m[31mCO4-PT-15-LTLFireability-10:
[[35mlola[0m][.] [1m[31mCO4-PT-15-LTLFireability-13:
[[35mlola[0m][.] [1m[31mCO4-PT-15-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-00:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-01:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-02:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-03:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-04:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-05:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-06:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-08:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-09:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-11:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-12:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 54 LTL EXCL 5/300
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs.
[[35mlola[0m][.] # running tasks: 1
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mCO4-PT-15-LTLFireability-07:
[[35mlola[0m][.] [1m[31mCO4-PT-15-LTLFireability-10:
[[35mlola[0m][.] [1m[31mCO4-PT-15-LTLFireability-13:
[[35mlola[0m][.] [1m[31mCO4-PT-15-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-00:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-01:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-02:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-03:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-04:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-05:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-06:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-08:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-09:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-11:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-12:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 54 LTL EXCL 10/300
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs.
[[35mlola[0m][.] # running tasks: 1
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mCO4-PT-15-LTLFireability-07:
[[35mlola[0m][.] [1m[31mCO4-PT-15-LTLFireability-10:
[[35mlola[0m][.] [1m[31mCO4-PT-15-LTLFireability-13:
[[35mlola[0m][.] [1m[31mCO4-PT-15-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-00:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-01:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-02:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-03:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-04:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-05:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-06:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-08:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-09:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-11:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-12:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 54 LTL EXCL 15/300
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 15 secs.
[[35mlola[0m][.] # running tasks: 1
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mCO4-PT-15-LTLFireability-07:
[[35mlola[0m][.] [1m[31mCO4-PT-15-LTLFireability-10:
[[35mlola[0m][.] [1m[31mCO4-PT-15-LTLFireability-13:
[[35mlola[0m][.] [1m[31mCO4-PT-15-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-00:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-01:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-02:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-03:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-04:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-05:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-06:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-08:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-09:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-11:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-12:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 54 LTL EXCL 20/300
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 20 secs.
[[35mlola[0m][.] # running tasks: 1
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mCO4-PT-15-LTLFireability-07:
[[35mlola[0m][.] [1m[31mCO4-PT-15-LTLFireability-10:
[[35mlola[0m][.] [1m[31mCO4-PT-15-LTLFireability-13:
[[35mlola[0m][.] [1m[31mCO4-PT-15-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-00:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-01:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-02:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-03:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-04:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-05:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-06:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-08:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-09:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-11:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-12:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 54 LTL EXCL 25/300
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 25 secs.
[[35mlola[0m][.] # running tasks: 1
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mCO4-PT-15-LTLFireability-07:
[[35mlola[0m][.] [1m[31mCO4-PT-15-LTLFireability-10:
[[35mlola[0m][.] [1m[31mCO4-PT-15-LTLFireability-13:
[[35mlola[0m][.] [1m[31mCO4-PT-15-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-00:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-01:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-02:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-03:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-04:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-05:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-06:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-08:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-09:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-11:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-12:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 54 LTL EXCL 30/300
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 30 secs.
[[35mlola[0m][.] # running tasks: 1
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mCO4-PT-15-LTLFireability-07:
[[35mlola[0m][.] [1m[31mCO4-PT-15-LTLFireability-10:
[[35mlola[0m][.] [1m[31mCO4-PT-15-LTLFireability-13:
[[35mlola[0m][.] [1m[31mCO4-PT-15-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-00:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-01:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-02:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-03:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-04:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-05:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-06:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-08:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-09:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-11:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-12:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 54 LTL EXCL 35/300
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 35 secs.
[[35mlola[0m][.] # running tasks: 1
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mCO4-PT-15-LTLFireability-07:
[[35mlola[0m][.] [1m[31mCO4-PT-15-LTLFireability-10:
[[35mlola[0m][.] [1m[31mCO4-PT-15-LTLFireability-13:
[[35mlola[0m][.] [1m[31mCO4-PT-15-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-00:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-01:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-02:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-03:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-04:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-05:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-06:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-08:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-09:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-11:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-12:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 54 LTL EXCL 40/300
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 40 secs.
[[35mlola[0m][.] # running tasks: 1
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mCO4-PT-15-LTLFireability-07:
[[35mlola[0m][.] [1m[31mCO4-PT-15-LTLFireability-10:
[[35mlola[0m][.] [1m[31mCO4-PT-15-LTLFireability-13:
[[35mlola[0m][.] [1m[31mCO4-PT-15-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-00:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-01:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-02:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-03:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-04:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-05:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-06:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-08:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-09:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-11:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-12:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 54 LTL EXCL 45/300
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 45 secs.
[[35mlola[0m][.] # running tasks: 1
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mCO4-PT-15-LTLFireability-07:
[[35mlola[0m][.] [1m[31mCO4-PT-15-LTLFireability-10:
[[35mlola[0m][.] [1m[31mCO4-PT-15-LTLFireability-13:
[[35mlola[0m][.] [1m[31mCO4-PT-15-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-00:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-01:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-02:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-03:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-04:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-05:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-06:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-08:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-09:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-11:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-12:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 54 LTL EXCL 50/300
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 50 secs.
[[35mlola[0m][.] # running tasks: 1
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mCO4-PT-15-LTLFireability-07:
[[35mlola[0m][.] [1m[31mCO4-PT-15-LTLFireability-10:
[[35mlola[0m][.] [1m[31mCO4-PT-15-LTLFireability-13:
[[35mlola[0m][.] [1m[31mCO4-PT-15-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-00:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-01:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-02:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-03:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-04:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-05:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-06:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-08:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-09:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-11:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-12:
[[35mlola[0m][.] CO4-PT-15-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 54 LTL EXCL 55/300
[[35mlola[0m][.]
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========================================== lity ==================== CTLCardinality.txt CTLCardinality.xml CTLFireability.txt CTLFireability.xml LTLCardinality.txt LTLCardinality.xml LTLFireability.txt LTLFireability.xml ReachabilityCardinality.txt ReachabilityCardinality.xml ReachabilityFireability.txt ReachabilityFireability.xml UpperBounds.txt UpperBounds.xml equiv_col iscolored model.pnml BenchKit (invocation template) vector(from text file) seconds at most ([1m[36m--timelimit[0m) in memory specification: using default[0m from [4m[34mmodel.pnml[0m -pnmlnet[0m) place/transition net file [4m[34mmodel.pnml[0m -xmlformula[0m) from [4m[34mLTLFireability.xml[0m removed,124 places removed CNST) for 50 CO4-PT-15-LTLFireability-14 (type CNST) for CO4-PT-15-LTLFireability-14 CNST) for 30 CO4-PT-15-LTLFireability-10 EXCL) for 21 CO4-PT-15-LTLFireability-07 (type CNST) for CO4-PT-15-LTLFireability-10 (type EXCL) for CO4-PT-15-LTLFireability-07 52 52 0 1 EXCL) for 47 CO4-PT-15-LTLFireability-13 (type EXCL) for CO4-PT-15-LTLFireability-13 52 52 0 1 EXCL) for 53 CO4-PT-15-LTLFireability-15 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m INITIAL false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 3/2000 CO4-PT-15-LTLFireability-15 395211 m, 79042 m/sec, 1710944 t fired, . Pages in use: 3 of 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m INITIAL false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 6/2000 CO4-PT-15-LTLFireability-15 840921 m, 89142 m/sec, 3573209 t fired, . Pages in use: 6 of 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m INITIAL false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 9/2000 CO4-PT-15-LTLFireability-15 1264764 m, 84768 m/sec, 5414807 t fired, . Pages in use: 9 of 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m INITIAL false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 12/2000 CO4-PT-15-LTLFireability-15 1653553 m, 77757 m/sec, 7135268 t fired, . Pages in use: 12 of 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m INITIAL false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 15/2000 CO4-PT-15-LTLFireability-15 2080401 m, 85369 m/sec, 8994075 t fired, . Pages in use: 15 of 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m INITIAL false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 17/2000 CO4-PT-15-LTLFireability-15 2458787 m, 75677 m/sec, 10832601 t fired, . Pages in use: 17 of 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m INITIAL false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 20/2000 CO4-PT-15-LTLFireability-15 2801358 m, 68514 m/sec, 12530925 t fired, . Pages in use: 20 of 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m INITIAL false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 22/2000 CO4-PT-15-LTLFireability-15 3143441 m, 68416 m/sec, 14369880 t fired, . Pages in use: 22 of 4. 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Visible: 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m INITIAL false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 31/2000 CO4-PT-15-LTLFireability-15 4372724 m, 67251 m/sec, 21016035 t fired, . Pages in use: 31 of 4. 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Visible: 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m LTL false LTL model checker[0m INITIAL false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 38/2000 CO4-PT-15-LTLFireability-03 5404674 m, 69742 m/sec, 23969667 t fired, . Pages in use: 610 of 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m LTL false LTL model checker[0m INITIAL false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 40/2000 CO4-PT-15-LTLFireability-03 5759685 m, 71002 m/sec, 25621568 t fired, . Pages in use: 617 of 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m LTL false LTL model checker[0m INITIAL false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 42/2000 CO4-PT-15-LTLFireability-03 6068394 m, 61741 m/sec, 27227514 t fired, . Pages in use: 623 of 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m LTL false LTL model checker[0m INITIAL false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 44/2000 CO4-PT-15-LTLFireability-03 6322728 m, 50866 m/sec, 28642838 t fired, . Pages in use: 629 of 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m LTL false LTL model checker[0m INITIAL false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 46/2000 CO4-PT-15-LTLFireability-03 6569258 m, 49306 m/sec, 29939479 t fired, . Pages in use: 635 of 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m LTL false LTL model checker[0m INITIAL false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 48/2000 CO4-PT-15-LTLFireability-03 6919040 m, 69956 m/sec, 31667964 t fired, . Pages in use: 643 of 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m LTL false LTL model checker[0m INITIAL false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 50/2000 CO4-PT-15-LTLFireability-03 7260805 m, 68353 m/sec, 33451321 t fired, . Pages in use: 649 of 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m LTL false LTL model checker[0m INITIAL false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 52/2000 CO4-PT-15-LTLFireability-03 7560301 m, 59899 m/sec, 35048227 t fired, . Pages in use: 654 of 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m LTL false LTL model checker[0m INITIAL false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 54/2000 CO4-PT-15-LTLFireability-03 7826960 m, 53331 m/sec, 36567931 t fired, . Pages in use: 661 of 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m LTL false LTL model checker[0m INITIAL false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 56/2000 CO4-PT-15-LTLFireability-03 8091393 m, 52886 m/sec, 38226200 t fired, . Pages in use: 667 of 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m LTL false LTL model checker[0m INITIAL false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 58/2000 CO4-PT-15-LTLFireability-03 8373457 m, 56412 m/sec, 39905287 t fired, . Pages in use: 673 of 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m LTL false LTL model checker[0m INITIAL false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 60/2000 CO4-PT-15-LTLFireability-03 8648377 m, 54984 m/sec, 41467569 t fired, . Pages in use: 678 of 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m LTL false LTL model checker[0m INITIAL false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 62/2000 CO4-PT-15-LTLFireability-03 8938357 m, 57996 m/sec, 42988525 t fired, . Pages in use: 684 of 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m LTL false LTL model checker[0m INITIAL false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 64/2000 CO4-PT-15-LTLFireability-03 9206199 m, 53568 m/sec, 44366769 t fired, . Pages in use: 689 of 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m LTL false LTL model checker[0m INITIAL false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 66/2000 CO4-PT-15-LTLFireability-03 9527665 m, 64293 m/sec, 45943837 t fired, . Pages in use: 696 of 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m LTL false LTL model checker[0m INITIAL false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 68/2000 CO4-PT-15-LTLFireability-03 9861764 m, 66819 m/sec, 47633501 t fired, . Pages in use: 702 of 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m LTL false LTL model checker[0m INITIAL false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 71/2000 CO4-PT-15-LTLFireability-03 10205268 m, 68700 m/sec, 49281153 t fired, . Pages in use: 709 of 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m LTL false LTL model checker[0m INITIAL false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 73/2000 CO4-PT-15-LTLFireability-03 10552877 m, 69521 m/sec, 50871197 t fired, . Pages in use: 716 of 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m LTL false LTL model checker[0m INITIAL false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 75/2000 CO4-PT-15-LTLFireability-03 10834171 m, 56258 m/sec, 52402753 t fired, . Pages in use: 722 of 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m LTL false LTL model checker[0m INITIAL false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 77/2000 CO4-PT-15-LTLFireability-03 11079781 m, 49122 m/sec, 53758194 t fired, . Pages in use: 728 of 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m LTL false LTL model checker[0m INITIAL false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 78/2000 CO4-PT-15-LTLFireability-03 11316378 m, 47319 m/sec, 55005934 t fired, . Pages in use: 733 of 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m LTL false LTL model checker[0m INITIAL false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 79/2000 CO4-PT-15-LTLFireability-03 11383924 m, 13509 m/sec, 55339992 t fired, . Pages in use: 735 of 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m LTL false LTL model checker[0m INITIAL false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 79/2000 CO4-PT-15-LTLFireability-03 11453179 m, 13851 m/sec, 55672965 t fired, . Pages in use: 736 of 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m LTL false LTL model checker[0m INITIAL false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 79/2000 CO4-PT-15-LTLFireability-03 11464965 m, 2357 m/sec, 55727395 t fired, . Pages in use: 736 of 4. Visible: 16 $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="CO4-PT-15"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is CO4-PT-15, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r551-tall-171734899400116"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/CO4-PT-15.tgz
mv CO4-PT-15 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;