fond
Model Checking Contest 2024
14th edition, Geneva, Switzerland, June 25, 2024
Execution of r551-tall-171734899300091
Last Updated
July 7, 2024

About the Execution of LoLA for CO4-PT-12

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
5287.640 3600000.00 442860.00 9235.50 [undef] Time out reached

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r551-tall-171734899300091.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is CO4-PT-12, examination is LTLCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r551-tall-171734899300091
=====================================================================


--------------------
preparation of the directory to be used:
/home/mcc/execution
total 640K
-rw-r--r-- 1 mcc users 8.2K Jun 2 17:16 CTLCardinality.txt
-rw-r--r-- 1 mcc users 94K Jun 2 17:16 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.3K Jun 2 17:16 CTLFireability.txt
-rw-r--r-- 1 mcc users 49K Jun 2 17:16 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.4K Jun 2 17:12 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Jun 2 17:12 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Jun 2 17:12 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Jun 2 17:12 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 Jun 2 16:33 NewModel
-rw-r--r-- 1 mcc users 12K Jun 2 17:16 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 126K Jun 2 17:16 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.1K Jun 2 17:16 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 61K Jun 2 17:16 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.5K Jun 2 17:12 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.5K Jun 2 17:12 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Jun 2 16:33 equiv_col
-rw-r--r-- 1 mcc users 3 Jun 2 16:33 instance
-rw-r--r-- 1 mcc users 6 Jun 2 16:33 iscolored
-rw-r--r-- 1 mcc users 177K Jun 2 16:33 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME CO4-PT-12-LTLCardinality-00
FORMULA_NAME CO4-PT-12-LTLCardinality-01
FORMULA_NAME CO4-PT-12-LTLCardinality-02
FORMULA_NAME CO4-PT-12-LTLCardinality-03
FORMULA_NAME CO4-PT-12-LTLCardinality-04
FORMULA_NAME CO4-PT-12-LTLCardinality-05
FORMULA_NAME CO4-PT-12-LTLCardinality-06
FORMULA_NAME CO4-PT-12-LTLCardinality-07
FORMULA_NAME CO4-PT-12-LTLCardinality-08
FORMULA_NAME CO4-PT-12-LTLCardinality-09
FORMULA_NAME CO4-PT-12-LTLCardinality-10
FORMULA_NAME CO4-PT-12-LTLCardinality-11
FORMULA_NAME CO4-PT-12-LTLCardinality-12
FORMULA_NAME CO4-PT-12-LTLCardinality-13
FORMULA_NAME CO4-PT-12-LTLCardinality-14
FORMULA_NAME CO4-PT-12-LTLCardinality-15

=== Now, execution of the tool begins

BK_START 1717400014982


BK_TIME_CONFINEMENT_REACHED

--------------------
content from stderr:

[lola][I] LoLA will run for 3600 seconds at most (--timelimit)
[lola][W] unknown unit in memory specification: using default
[lola][I] MEM LIMIT 5
[lola][I] NET
[lola][I] reading net from model.pnml
[lola][I] input: PNML file (--pnmlnet)
[lola][I] reading pnml
[lola][I] PNML file contains place/transition net
[lola][I] closed net file model.pnml
[lola][I] finished parsing
[lola][I] Reading formula.
[lola][I] Using XML format (--xmlformula)
[lola][I] reading XML formula
[lola][I] reading formula from LTLCardinality.xml
[lola][I] LAUNCH task # 7 (type CNST) for 6 CO4-PT-12-LTLCardinality-02
[lola][I] time limit : 0 sec
[lola][I] memory limit: 0 pages
[lola][I] FINISHED task # 7 (type CNST) for CO4-PT-12-LTLCardinality-02
[lola][I] result : true
[lola][I] Rule S: 219 transitions removed,172 places removed
[lola][I] LAUNCH task # 43 (type CNST) for 42 CO4-PT-12-LTLCardinality-14
[lola][I] time limit : 0 sec
[lola][I] memory limit: 0 pages
[lola][I] FINISHED task # 43 (type CNST) for CO4-PT-12-LTLCardinality-14
[lola][I] result : true
[lola][I] LAUNCH task # 10 (type EXCL) for 9 CO4-PT-12-LTLCardinality-03
[lola][I] time limit : 199 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 10 (type EXCL) for CO4-PT-12-LTLCardinality-03
[lola][I] result : false
[lola][I] markings : 10
[lola][I] fired transitions : 11
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 40 (type EXCL) for 39 CO4-PT-12-LTLCardinality-13
[lola][I] time limit : 224 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 40 (type EXCL) for CO4-PT-12-LTLCardinality-13
[lola][I] result : true
[lola][I] markings : 2
[lola][I] fired transitions : 1
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 22 (type CNST) for 21 CO4-PT-12-LTLCardinality-07
[lola][I] time limit : 0 sec
[lola][I] memory limit: 0 pages
[lola][I] LAUNCH task # 13 (type EXCL) for 12 CO4-PT-12-LTLCardinality-04
[lola][I] time limit : 299 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 22 (type CNST) for CO4-PT-12-LTLCardinality-07
[lola][I] result : false
[lola][I] FINISHED task # 13 (type EXCL) for CO4-PT-12-LTLCardinality-04
[lola][I] result : false
[lola][I] markings : 28
[lola][I] fired transitions : 28
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 28 (type EXCL) for 27 CO4-PT-12-LTLCardinality-09
[lola][I] time limit : 359 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 28 (type EXCL) for CO4-PT-12-LTLCardinality-09
[lola][I] result : true
[lola][I] markings : 4
[lola][I] fired transitions : 3
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 46 (type EXCL) for 45 CO4-PT-12-LTLCardinality-15
[lola][I] time limit : 399 sec
[lola][I] memory limit: 2000 pages
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] CO4-PT-12-LTLCardinality-02: INITIAL true preprocessing
[lola][.] CO4-PT-12-LTLCardinality-03: LTL false LTL model checker
[lola][.] CO4-PT-12-LTLCardinality-04: LTL/CTL false LTL model checker
[lola][.] CO4-PT-12-LTLCardinality-07: INITIAL false preprocessing
[lola][.] CO4-PT-12-LTLCardinality-09: LTL true LTL model checker
[lola][.] CO4-PT-12-LTLCardinality-13: LTL true LTL model checker
[lola][.] CO4-PT-12-LTLCardinality-14: INITIAL true preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] CO4-PT-12-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-12-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-12-LTLCardinality-05: LTL/CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-12-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-12-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-12-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-12-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-12-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-12-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 46 LTL EXCL 5/399 5/2000 CO4-PT-12-LTLCardinality-15 660092 m, 132018 m/sec, 3031691 t fired, .
[lola][.]
[lola][.] Time elapsed: 7 secs. Pages in use: 5
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] CO4-PT-12-LTLCardinality-02: INITIAL true preprocessing
[lola][.] CO4-PT-12-LTLCardinality-03: LTL false LTL model checker
[lola][.] CO4-PT-12-LTLCardinality-04: LTL/CTL false LTL model checker
[lola][.] CO4-PT-12-LTLCardinality-07: INITIAL false preprocessing
[lola][.] CO4-PT-12-LTLCardinality-09: LTL true LTL model checker
[lola][.] CO4-PT-12-LTLCardinality-13: LTL true LTL model checker
[lola][.] CO4-PT-12-LTLCardinality-14: INITIAL true preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] CO4-PT-12-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-12-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-12-LTLCardinality-05: LTL/CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-12-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-12-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-12-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-12-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-12-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-12-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 46 LTL EXCL 10/399 9/2000 CO4-PT-12-LTLCardinality-15 1320637 m, 132109 m/sec, 5768773 t fired, .
[lola][.]
[lola][.] Time elapsed: 12 secs. Pages in use: 9
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] CO4-PT-12-LTLCardinality-02: INITIAL true preprocessing
[lola][.] CO4-PT-12-LTLCardinality-03: LTL false LTL model checker
[lola][.] CO4-PT-12-LTLCardinality-04: LTL/CTL false LTL model checker
[lola][.] CO4-PT-12-LTLCardinality-07: INITIAL false preprocessing
[lola][.] CO4-PT-12-LTLCardinality-09: LTL true LTL model checker
[lola][.] CO4-PT-12-LTLCardinality-13: LTL true LTL model checker
[lola][.] CO4-PT-12-LTLCardinality-14: INITIAL true preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] CO4-PT-12-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-12-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-12-LTLCardinality-05: LTL/CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-12-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-12-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-12-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-12-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-12-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-12-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 46 LTL EXCL 15/399 13/2000 CO4-PT-12-LTLCardinality-15 1903651 m, 116602 m/sec, 8276370 t fired, .
[lola][.]
[lola][.] Time elapsed: 17 secs. Pages in use: 13
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] CO4-PT-12-LTLCardinality-02: INITIAL true preprocessing
[lola][.] CO4-PT-12-LTLCardinality-03: LTL false LTL model checker
[lola][.] CO4-PT-12-LTLCardinality-04: LTL/CTL false LTL model checker
[lola][.] CO4-PT-12-LTLCardinality-07: INITIAL false preprocessing
[lola][.] CO4-PT-12-LTLCardinality-09: LTL true LTL model checker
[lola][.] CO4-PT-12-LTLCardinality-13: LTL true LTL model checker
[lola][.] CO4-PT-12-LTLCardinality-14: INITIAL true preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] CO4-PT-12-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-12-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-12-LTLCardinality-05: LTL/CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-12-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-12-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-12-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-12-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-12-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-12-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 46 LTL EXCL 20/399 16/2000 CO4-PT-12-LTLCardinality-15 2428285 m, 104926 m/sec, 10865985 t fired, .
[lola][.]
[lola][.] Time elapsed: 22 secs. Pages in use: 16
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] CO4-PT-12-LTLCardinality-02: INITIAL true preprocessing
[lola][.] CO4-PT-12-LTLCardinality-03: LTL false LTL model checker
[lola][.] CO4-PT-12-LTLCardinality-04: LTL/CTL false LTL model checker
[lola][.] CO4-PT-12-LTLCardinality-07: INITIAL false preprocessing
[lola][.] CO4-PT-12-LTLCardinality-09: LTL true LTL model checker
[lola][.] CO4-PT-12-LTLCardinality-13: LTL true LTL model checker
[lola][.] CO4-PT-12-LTLCardinality-14: INITIAL true preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] CO4-PT-12-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-12-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-12-LTLCardinality-05: LTL/CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-12-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-12-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-12-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-12-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-12-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-12-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 46 LTL EXCL 25/399 19/2000 CO4-PT-12-LTLCardinality-15 2879157 m, 90174 m/sec, 13395917 t fired, .
[lola][.]
[lola][.] Time elapsed: 27 secs. Pages in use: 19
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] CO4-PT-12-LTLCardinality-02: INITIAL true preprocessing
[lola][.] CO4-PT-12-LTLCardinality-03: LTL false LTL model checker
[lola][.] CO4-PT-12-LTLCardinality-04: LTL/CTL false LTL model checker
[lola][.] CO4-PT-12-LTLCardinality-07: INITIAL false preprocessing
[lola][.] CO4-PT-12-LTLCardinality-09: LTL true LTL model checker
[lola][.] CO4-PT-12-LTLCardinality-13: LTL true LTL model checker
[lola][.] CO4-PT-12-LTLCardinality-14: INITIAL true preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] CO4-PT-12-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-12-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-12-LTLCardinality-05: LTL/CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-12-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-12-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-12-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-12-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-12-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-12-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 46 LTL EXCL 30/399 22/2000 CO4-PT-12-LTLCardinality-15 3325740 m, 89316 m/sec, 15931405 t fired, .
[lola][.]
[lola][.] Time elapsed: 32 secs. Pages in use: 22
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[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] CO4-PT-12-LTLCardinality-02: INITIAL true preprocessing
[lola][.] CO4-PT-12-LTLCardinality-03: LTL false LTL model checker
[lola][.] CO4-PT-12-LTLCardinality-04: LTL/CTL false LTL model checker
[lola][.] CO4-PT-12-LTLCardinality-07: INITIAL false preprocessing
[lola][.] CO4-PT-12-LTLCardinality-09: LTL true LTL model checker
[lola][.] CO4-PT-12-LTLCardinality-13: LTL true LTL model checker
[lola][.] CO4-PT-12-LTLCardinality-14: INITIAL true preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] CO4-PT-12-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-12-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-12-LTLCardinality-05: LTL/CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-12-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-12-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-12-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-12-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-12-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-12-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 46 LTL EXCL 35/399 24/2000 CO4-PT-12-LTLCardinality-15 3764195 m, 87691 m/sec, 18420483 t fired, .
[lola][.]
[lola][.] Time elapsed: 37 secs. Pages in use: 24
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[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] CO4-PT-12-LTLCardinality-02: INITIAL true preprocessing
[lola][.] CO4-PT-12-LTLCardinality-03: LTL false LTL model checker
[lola][.] CO4-PT-12-LTLCardinality-04: LTL/CTL false LTL model checker
[lola][.] CO4-PT-12-LTLCardinality-07: INITIAL false preprocessing
[lola][.] CO4-PT-12-LTLCardinality-09: LTL true LTL model checker
[lola][.] CO4-PT-12-LTLCardinality-13: LTL true LTL model checker
[lola][.] CO4-PT-12-LTLCardinality-14: INITIAL true preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] CO4-PT-12-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-12-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-12-LTLCardinality-05: LTL/CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-12-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-12-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-12-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-12-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-12-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-12-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 46 LTL EXCL 40/399 28/2000 CO4-PT-12-LTLCardinality-15 4314083 m, 109977 m/sec, 20963044 t fired, .
[lola][.]
[lola][.] Time elapsed: 42 secs. Pages in use: 28
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[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] CO4-PT-12-LTLCardinality-02: INITIAL true preprocessing
[lola][.] CO4-PT-12-LTLCardinality-03: LTL false LTL model checker
[lola][.] CO4-PT-12-LTLCardinality-04: LTL/CTL false LTL model checker
[lola][.] CO4-PT-12-LTLCardinality-07: INITIAL false preprocessing
[lola][.] CO4-PT-12-LTLCardinality-09: LTL true LTL model checker
[lola][.] CO4-PT-12-LTLCardinality-13: LTL true LTL model checker
[lola][.] CO4-PT-12-LTLCardinality-14: INITIAL true preprocessing
[lola][.]
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[lola][.] 46 LTL EXCL 45/399 32/2000 CO4-PT-12-LTLCardinality-15 4889400 m, 115063 m/sec, 23593253 t fired, .
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[lola][.] 46 LTL EXCL 105/399 63/2000 CO4-PT-12-LTLCardinality-15 9926291 m, 84819 m/sec, 53465782 t fired, .
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[lola][.] 46 LTL EXCL 110/399 66/2000 CO4-PT-12-LTLCardinality-15 10318364 m, 78414 m/sec, 56025706 t fired, .
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[lola][.] 46 LTL EXCL 115/399 68/2000 CO4-PT-12-LTLCardinality-15 10678495 m, 72026 m/sec, 58425624 t fired, .
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[lola][.] 46 LTL EXCL 120/399 71/2000 CO4-PT-12-LTLCardinality-15 11122637 m, 88828 m/sec, 60958109 t fired, .
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[lola][.] 46 LTL EXCL 160/399 92/2000 CO4-PT-12-LTLCardinality-15 14438669 m, 87290 m/sec, 80857608 t fired, .
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[lola][.] CO4-PT-12-LTLCardinality-00: LTL true LTL model checker
[lola][.] CO4-PT-12-LTLCardinality-01: LTL true LTL model checker
[lola][.] CO4-PT-12-LTLCardinality-02: INITIAL true preprocessing
[lola][.] CO4-PT-12-LTLCardinality-03: LTL false LTL model checker
[lola][.] CO4-PT-12-LTLCardinality-04: LTL/CTL false LTL model checker
[lola][.] CO4-PT-12-LTLCardinality-05: LTL/CTL true LTL model checker
[lola][.] CO4-PT-12-LTLCardinality-06: LTL false LTL model checker
[lola][.] CO4-PT-12-LTLCardinality-07: INITIAL false preprocessing
[lola][.] CO4-PT-12-LTLCardinality-08: LTL true LTL model checker
[lola][.] CO4-PT-12-LTLCardinality-09: LTL true LTL model checker
[lola][.] CO4-PT-12-LTLCardinality-10: LTL true LTL model checker
[lola][.] CO4-PT-12-LTLCardinality-11: LTL false LTL model checker
[lola][.] CO4-PT-12-LTLCardinality-12: LTL false LTL model checker
[lola][.] CO4-PT-12-LTLCardinality-13: LTL true LTL model checker
[lola][.] CO4-PT-12-LTLCardinality-14: INITIAL true preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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[lola][.] CO4-PT-12-LTLCardinality-02: INITIAL true preprocessing
[lola][.] CO4-PT-12-LTLCardinality-03: LTL false LTL model checker
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[lola][.] CO4-PT-12-LTLCardinality-07: INITIAL false preprocessing
[lola][.] CO4-PT-12-LTLCardinality-08: LTL true LTL model checker
[lola][.] CO4-PT-12-LTLCardinality-09: LTL true LTL model checker
[lola][.] CO4-PT-12-LTLCardinality-10: LTL true LTL model checker
[lola][.] CO4-PT-12-LTLCardinality-11: LTL false LTL model checker
[lola][.] CO4-PT-12-LTLCardinality-12: LTL false LTL model checker
[lola][.] CO4-PT-12-LTLCardinality-13: LTL true LTL model checker
[lola][.] CO4-PT-12-LTLCardinality-14: INITIAL true preprocessing
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[lola][.] CO4-PT-12-LTLCardinality-02: INITIAL true preprocessing
[lola][.] CO4-PT-12-LTLCardinality-03: LTL false LTL model checker
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[lola][.] CO4-PT-12-LTLCardinality-05: LTL/CTL true LTL model checker
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[lola][.] CO4-PT-12-LTLCardinality-09: LTL true LTL model checker
[lola][.] CO4-PT-12-LTLCardinality-10: LTL true LTL model checker
[lola][.] CO4-PT-12-LTLCardinality-11: LTL false LTL model checker
[lola][.] CO4-PT-12-LTLCardinality-12: LTL false LTL model checker
[lola][.] CO4-PT-12-LTLCardinality-13: LTL true LTL model checker
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[lola][.] CO4-PT-12-LTLCardinality-05: LTL/CTL true LTL model checker
[lola][.] CO4-PT-12-LTLCardinality-06: LTL false LTL model checker
[lola][.] CO4-PT-12-LTLCardinality-07: INITIAL false preprocessing
[lola][.] CO4-PT-12-LTLCardinality-08: LTL true LTL model checker
[lola][.] CO4-PT-12-LTLCardinality-09: LTL true LTL model checker
[lola][.] CO4-PT-12-LTLCardinality-10: LTL true LTL model checker
[lola][.] CO4-PT-12-LTLCardinality-11: LTL false LTL model checker
[lola][.] CO4-PT-12-LTLCardinality-12: LTL false LTL model checker
[lola][.] CO4-PT-12-LTLCardinality-13: LTL true LTL model checker
[lola][.] CO4-PT-12-LTLCardinality-14: INITIAL true preprocessing
[lola][.]

========== file over 1MB has been truncated ======
retrieve it from the run archives if needed

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="CO4-PT-12"
export BK_EXAMINATION="LTLCardinality"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is CO4-PT-12, examination is LTLCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r551-tall-171734899300091"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/CO4-PT-12.tgz
mv CO4-PT-12 execution
cd execution
if [ "LTLCardinality" = "ReachabilityDeadlock" ] || [ "LTLCardinality" = "UpperBounds" ] || [ "LTLCardinality" = "QuasiLiveness" ] || [ "LTLCardinality" = "StableMarking" ] || [ "LTLCardinality" = "Liveness" ] || [ "LTLCardinality" = "OneSafe" ] || [ "LTLCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "LTLCardinality" = "ReachabilityDeadlock" ] || [ "LTLCardinality" = "QuasiLiveness" ] || [ "LTLCardinality" = "StableMarking" ] || [ "LTLCardinality" = "Liveness" ] || [ "LTLCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;