Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r551-tall-171734899300082.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is CO4-PT-11, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r551-tall-171734899300082
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 584K
-rw-r--r-- 1 mcc users 6.3K Jun 2 17:16 CTLCardinality.txt
-rw-r--r-- 1 mcc users 68K Jun 2 17:16 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.1K Jun 2 17:16 CTLFireability.txt
-rw-r--r-- 1 mcc users 60K Jun 2 17:16 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.3K Jun 2 17:12 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Jun 2 17:12 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Jun 2 17:12 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Jun 2 17:12 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 Jun 2 16:33 NewModel
-rw-r--r-- 1 mcc users 11K Jun 2 17:16 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 117K Jun 2 17:16 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.0K Jun 2 17:16 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 82K Jun 2 17:16 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.5K Jun 2 17:12 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.5K Jun 2 17:12 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Jun 2 16:33 equiv_col
-rw-r--r-- 1 mcc users 3 Jun 2 16:33 instance
-rw-r--r-- 1 mcc users 6 Jun 2 16:33 iscolored
-rw-r--r-- 1 mcc users 132K Jun 2 16:33 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME CO4-PT-11-CTLFireability-2024-00
FORMULA_NAME CO4-PT-11-CTLFireability-2024-01
FORMULA_NAME CO4-PT-11-CTLFireability-2024-02
FORMULA_NAME CO4-PT-11-CTLFireability-2024-03
FORMULA_NAME CO4-PT-11-CTLFireability-2024-04
FORMULA_NAME CO4-PT-11-CTLFireability-2024-05
FORMULA_NAME CO4-PT-11-CTLFireability-2024-06
FORMULA_NAME CO4-PT-11-CTLFireability-2024-07
FORMULA_NAME CO4-PT-11-CTLFireability-2024-08
FORMULA_NAME CO4-PT-11-CTLFireability-2024-09
FORMULA_NAME CO4-PT-11-CTLFireability-2024-10
FORMULA_NAME CO4-PT-11-CTLFireability-2024-11
FORMULA_NAME CO4-PT-11-CTLFireability-2024-12
FORMULA_NAME CO4-PT-11-CTLFireability-2024-13
FORMULA_NAME CO4-PT-11-CTLFireability-2024-14
FORMULA_NAME CO4-PT-11-CTLFireability-2024-15

=== Now, execution of the tool begins

BK_START 1717398482213

FORMULA CO4-PT-11-CTLFireability-2024-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-11-CTLFireability-2024-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-11-CTLFireability-2024-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-11-CTLFireability-2024-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-11-CTLFireability-2024-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-11-CTLFireability-2024-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-11-CTLFireability-2024-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-11-CTLFireability-2024-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-11-CTLFireability-2024-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-11-CTLFireability-2024-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-11-CTLFireability-2024-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-11-CTLFireability-2024-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-11-CTLFireability-2024-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-11-CTLFireability-2024-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-11-CTLFireability-2024-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-11-CTLFireability-2024-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[lola] FINAL RESULTS
[lola]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola] CO4-PT-11-CTLFireability-2024-00: INITIAL false preprocessing
[lola] CO4-PT-11-CTLFireability-2024-01: CTL false CTL model checker
[lola] CO4-PT-11-CTLFireability-2024-02: CTL false CTL model checker
[lola] CO4-PT-11-CTLFireability-2024-03: CTL false CTL model checker
[lola] CO4-PT-11-CTLFireability-2024-04: DISJ true CTL model checker
[lola] CO4-PT-11-CTLFireability-2024-05: CTL false CTL model checker
[lola] CO4-PT-11-CTLFireability-2024-06: CTL false CTL model checker
[lola] CO4-PT-11-CTLFireability-2024-07: CTL true CTL model checker
[lola] CO4-PT-11-CTLFireability-2024-08: INITIAL false preprocessing
[lola] CO4-PT-11-CTLFireability-2024-09: CTL true CTL model checker
[lola] CO4-PT-11-CTLFireability-2024-10: AGEF true tscc_search
[lola] CO4-PT-11-CTLFireability-2024-11: CTL true CTL model checker
[lola] CO4-PT-11-CTLFireability-2024-12: INITIAL false preprocessing
[lola] CO4-PT-11-CTLFireability-2024-13: CTL true CTL model checker
[lola] CO4-PT-11-CTLFireability-2024-14: CTL true CTL model checker
[lola] CO4-PT-11-CTLFireability-2024-15: INITIAL false preprocessing
[lola]
[lola] Time elapsed: 19 secs. Pages in use: 11

BK_STOP 1717398501400

--------------------
content from stderr:

[lola][I] LoLA will run for 3600 seconds at most (--timelimit)
[lola][W] unknown unit in memory specification: using default
[lola][I] MEM LIMIT 5
[lola][I] NET
[lola][I] reading net from model.pnml
[lola][I] input: PNML file (--pnmlnet)
[lola][I] reading pnml
[lola][I] PNML file contains place/transition net
[lola][I] closed net file model.pnml
[lola][I] finished parsing
[lola][I] Reading formula.
[lola][I] Using XML format (--xmlformula)
[lola][I] reading XML formula
[lola][I] reading formula from CTLFireability.xml
[lola][I] Rule S: 177 transitions removed,157 places removed
[lola][I] LAUNCH task # 1 (type CNST) for 0 CO4-PT-11-CTLFireability-2024-00
[lola][I] time limit : 0 sec
[lola][I] memory limit: 0 pages
[lola][I] FINISHED task # 1 (type CNST) for CO4-PT-11-CTLFireability-2024-00
[lola][I] result : false
[lola][I] LAUNCH task # 41 (type CNST) for 40 CO4-PT-11-CTLFireability-2024-12
[lola][I] time limit : 0 sec
[lola][I] memory limit: 0 pages
[lola][I] FINISHED task # 41 (type CNST) for CO4-PT-11-CTLFireability-2024-12
[lola][I] result : false
[lola][I] LAUNCH task # 53 (type EXCL) for 12 CO4-PT-11-CTLFireability-2024-04
[lola][I] time limit : 179 sec
[lola][I] memory limit: 2000 pages
[lola][I] LAUNCH task # 56 (type EQUN) for 12 CO4-PT-11-CTLFireability-2024-04
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 58 (type EQUN) for 12 CO4-PT-11-CTLFireability-2024-04
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 50 (type CNST) for 49 CO4-PT-11-CTLFireability-2024-15
[lola][I] time limit : 0 sec
[lola][I] memory limit: 0 pages
[lola][I] FINISHED task # 50 (type CNST) for CO4-PT-11-CTLFireability-2024-15
[lola][I] result : false
[lola][I] FINISHED task # 56 (type EQUN) for CO4-PT-11-CTLFireability-2024-04
[lola][I] result : true
[lola][I] LAUNCH task # 29 (type CNST) for 28 CO4-PT-11-CTLFireability-2024-08
[lola][I] time limit : 0 sec
[lola][I] memory limit: 0 pages
[lola][I] FINISHED task # 29 (type CNST) for CO4-PT-11-CTLFireability-2024-08
[lola][I] result : false
[lola][I] FINISHED task # 58 (type EQUN) for CO4-PT-11-CTLFireability-2024-04
[lola][I] result : unknown
[lola][I] LAUNCH task # 62 (type EQUN) for 34 CO4-PT-11-CTLFireability-2024-10
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 64 (type EQUN) for 34 CO4-PT-11-CTLFireability-2024-10
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 53 (type EXCL) for CO4-PT-11-CTLFireability-2024-04
[lola][I] result : true
[lola][I] markings : 59158
[lola][I] fired transitions : 303444
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 47 (type EXCL) for 46 CO4-PT-11-CTLFireability-2024-14
[lola][I] time limit : 299 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 47 (type EXCL) for CO4-PT-11-CTLFireability-2024-14
[lola][I] result : true
[lola][I] markings : 53
[lola][I] fired transitions : 123
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 44 (type EXCL) for 43 CO4-PT-11-CTLFireability-2024-13
[lola][I] time limit : 327 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 44 (type EXCL) for CO4-PT-11-CTLFireability-2024-13
[lola][I] result : true
[lola][I] markings : 26
[lola][I] fired transitions : 51
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 38 (type EXCL) for 37 CO4-PT-11-CTLFireability-2024-11
[lola][I] time limit : 359 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 62 (type EQUN) for CO4-PT-11-CTLFireability-2024-10
[lola][I] result : unknown
[lola][I] FINISHED task # 38 (type EXCL) for CO4-PT-11-CTLFireability-2024-11
[lola][I] result : true
[lola][I] markings : 4979
[lola][I] fired transitions : 11074
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 32 (type EXCL) for 31 CO4-PT-11-CTLFireability-2024-09
[lola][I] time limit : 399 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 32 (type EXCL) for CO4-PT-11-CTLFireability-2024-09
[lola][I] result : true
[lola][I] markings : 25
[lola][I] fired transitions : 50
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 26 (type EXCL) for 25 CO4-PT-11-CTLFireability-2024-07
[lola][I] time limit : 449 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 64 (type EQUN) for CO4-PT-11-CTLFireability-2024-10
[lola][I] result : unknown
[lola][I] FINISHED task # 26 (type EXCL) for CO4-PT-11-CTLFireability-2024-07
[lola][I] result : true
[lola][I] markings : 342
[lola][I] fired transitions : 731
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 23 (type EXCL) for 22 CO4-PT-11-CTLFireability-2024-06
[lola][I] time limit : 514 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 23 (type EXCL) for CO4-PT-11-CTLFireability-2024-06
[lola][I] result : false
[lola][I] markings : 342
[lola][I] fired transitions : 731
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 20 (type EXCL) for 19 CO4-PT-11-CTLFireability-2024-05
[lola][I] time limit : 599 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 20 (type EXCL) for CO4-PT-11-CTLFireability-2024-05
[lola][I] result : false
[lola][I] markings : 342
[lola][I] fired transitions : 731
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 17 (type EXCL) for 12 CO4-PT-11-CTLFireability-2024-04
[lola][I] time limit : 719 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 17 (type EXCL) for CO4-PT-11-CTLFireability-2024-04
[lola][I] result : true
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 10 (type EXCL) for 9 CO4-PT-11-CTLFireability-2024-03
[lola][I] time limit : 899 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 10 (type EXCL) for CO4-PT-11-CTLFireability-2024-03
[lola][I] result : false
[lola][I] markings : 25
[lola][I] fired transitions : 72
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 7 (type EXCL) for 6 CO4-PT-11-CTLFireability-2024-02
[lola][I] time limit : 1199 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 7 (type EXCL) for CO4-PT-11-CTLFireability-2024-02
[lola][I] result : false
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 4 (type EXCL) for 3 CO4-PT-11-CTLFireability-2024-01
[lola][I] time limit : 1799 sec
[lola][I] memory limit: 2000 pages
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] CO4-PT-11-CTLFireability-2024-00: INITIAL false preprocessing
[lola][.] CO4-PT-11-CTLFireability-2024-02: CTL false CTL model checker
[lola][.] CO4-PT-11-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] CO4-PT-11-CTLFireability-2024-04: DISJ true CTL model checker
[lola][.] CO4-PT-11-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] CO4-PT-11-CTLFireability-2024-06: CTL false CTL model checker
[lola][.] CO4-PT-11-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] CO4-PT-11-CTLFireability-2024-08: INITIAL false preprocessing
[lola][.] CO4-PT-11-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] CO4-PT-11-CTLFireability-2024-11: CTL true CTL model checker
[lola][.] CO4-PT-11-CTLFireability-2024-12: INITIAL false preprocessing
[lola][.] CO4-PT-11-CTLFireability-2024-13: CTL true CTL model checker
[lola][.] CO4-PT-11-CTLFireability-2024-14: CTL true CTL model checker
[lola][.] CO4-PT-11-CTLFireability-2024-15: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] CO4-PT-11-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[lola][.] CO4-PT-11-CTLFireability-2024-10: AGEF 0 1 0 0 3 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 4 CTL EXCL 5/1799 4/2000 CO4-PT-11-CTLFireability-2024-01 810242 m, 162048 m/sec, 2385982 t fired, .
[lola][.]
[lola][.] Time elapsed: 6 secs. Pages in use: 4
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] CO4-PT-11-CTLFireability-2024-00: INITIAL false preprocessing
[lola][.] CO4-PT-11-CTLFireability-2024-02: CTL false CTL model checker
[lola][.] CO4-PT-11-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] CO4-PT-11-CTLFireability-2024-04: DISJ true CTL model checker
[lola][.] CO4-PT-11-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] CO4-PT-11-CTLFireability-2024-06: CTL false CTL model checker
[lola][.] CO4-PT-11-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] CO4-PT-11-CTLFireability-2024-08: INITIAL false preprocessing
[lola][.] CO4-PT-11-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] CO4-PT-11-CTLFireability-2024-11: CTL true CTL model checker
[lola][.] CO4-PT-11-CTLFireability-2024-12: INITIAL false preprocessing
[lola][.] CO4-PT-11-CTLFireability-2024-13: CTL true CTL model checker
[lola][.] CO4-PT-11-CTLFireability-2024-14: CTL true CTL model checker
[lola][.] CO4-PT-11-CTLFireability-2024-15: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] CO4-PT-11-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[lola][.] CO4-PT-11-CTLFireability-2024-10: AGEF 0 1 0 0 3 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 4 CTL EXCL 10/1799 7/2000 CO4-PT-11-CTLFireability-2024-01 1440195 m, 125990 m/sec, 4977206 t fired, .
[lola][.]
[lola][.] Time elapsed: 11 secs. Pages in use: 7
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] CO4-PT-11-CTLFireability-2024-00: INITIAL false preprocessing
[lola][.] CO4-PT-11-CTLFireability-2024-02: CTL false CTL model checker
[lola][.] CO4-PT-11-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] CO4-PT-11-CTLFireability-2024-04: DISJ true CTL model checker
[lola][.] CO4-PT-11-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] CO4-PT-11-CTLFireability-2024-06: CTL false CTL model checker
[lola][.] CO4-PT-11-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] CO4-PT-11-CTLFireability-2024-08: INITIAL false preprocessing
[lola][.] CO4-PT-11-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] CO4-PT-11-CTLFireability-2024-11: CTL true CTL model checker
[lola][.] CO4-PT-11-CTLFireability-2024-12: INITIAL false preprocessing
[lola][.] CO4-PT-11-CTLFireability-2024-13: CTL true CTL model checker
[lola][.] CO4-PT-11-CTLFireability-2024-14: CTL true CTL model checker
[lola][.] CO4-PT-11-CTLFireability-2024-15: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] CO4-PT-11-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[lola][.] CO4-PT-11-CTLFireability-2024-10: AGEF 0 1 0 0 3 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 4 CTL EXCL 15/1799 9/2000 CO4-PT-11-CTLFireability-2024-01 2083707 m, 128702 m/sec, 7542608 t fired, .
[lola][.]
[lola][.] Time elapsed: 16 secs. Pages in use: 9
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I] FINISHED task # 4 (type EXCL) for CO4-PT-11-CTLFireability-2024-01
[lola][I] result : false
[lola][I] markings : 2434394
[lola][I] fired transitions : 8823862
[lola][I] time used : 18
[lola][I] memory pages used : 11
[lola][I] LAUNCH task # 59 (type EXCL) for 34 CO4-PT-11-CTLFireability-2024-10
[lola][I] time limit : 3581 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 59 (type EXCL) for CO4-PT-11-CTLFireability-2024-10
[lola][I] result : true
[lola][I] markings : 69937
[lola][I] fired transitions : 352851
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] Portfolio finished: no open formulas

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="CO4-PT-11"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is CO4-PT-11, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r551-tall-171734899300082"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/CO4-PT-11.tgz
mv CO4-PT-11 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;