About the Execution of LoLA for CO4-PT-10
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 1069.672 | 138416.00 | 140530.00 | 503.10 | TFFTFTTTFTFTFFTF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r551-tall-171734899300074.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is CO4-PT-10, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r551-tall-171734899300074
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 556K
-rw-r--r-- 1 mcc users 6.3K Jun 2 17:16 CTLCardinality.txt
-rw-r--r-- 1 mcc users 67K Jun 2 17:16 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.6K Jun 2 17:16 CTLFireability.txt
-rw-r--r-- 1 mcc users 68K Jun 2 17:16 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.6K Jun 2 17:12 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Jun 2 17:12 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.0K Jun 2 17:12 LTLFireability.txt
-rw-r--r-- 1 mcc users 15K Jun 2 17:12 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 Jun 2 16:33 NewModel
-rw-r--r-- 1 mcc users 9.8K Jun 2 17:16 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 105K Jun 2 17:16 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.8K Jun 2 17:16 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 67K Jun 2 17:16 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.5K Jun 2 17:12 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.5K Jun 2 17:12 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Jun 2 16:33 equiv_col
-rw-r--r-- 1 mcc users 3 Jun 2 16:33 instance
-rw-r--r-- 1 mcc users 6 Jun 2 16:33 iscolored
-rw-r--r-- 1 mcc users 132K Jun 2 16:33 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME CO4-PT-10-CTLFireability-2024-00
FORMULA_NAME CO4-PT-10-CTLFireability-2024-01
FORMULA_NAME CO4-PT-10-CTLFireability-2024-02
FORMULA_NAME CO4-PT-10-CTLFireability-2024-03
FORMULA_NAME CO4-PT-10-CTLFireability-2024-04
FORMULA_NAME CO4-PT-10-CTLFireability-2024-05
FORMULA_NAME CO4-PT-10-CTLFireability-2024-06
FORMULA_NAME CO4-PT-10-CTLFireability-2024-07
FORMULA_NAME CO4-PT-10-CTLFireability-2024-08
FORMULA_NAME CO4-PT-10-CTLFireability-2024-09
FORMULA_NAME CO4-PT-10-CTLFireability-2024-10
FORMULA_NAME CO4-PT-10-CTLFireability-2024-11
FORMULA_NAME CO4-PT-10-CTLFireability-2024-12
FORMULA_NAME CO4-PT-10-CTLFireability-2024-13
FORMULA_NAME CO4-PT-10-CTLFireability-2024-14
FORMULA_NAME CO4-PT-10-CTLFireability-2024-15
=== Now, execution of the tool begins
BK_START 1717398157276
FORMULA CO4-PT-10-CTLFireability-2024-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-10-CTLFireability-2024-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-10-CTLFireability-2024-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-10-CTLFireability-2024-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-10-CTLFireability-2024-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-10-CTLFireability-2024-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-10-CTLFireability-2024-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-10-CTLFireability-2024-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-10-CTLFireability-2024-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-10-CTLFireability-2024-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-10-CTLFireability-2024-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-10-CTLFireability-2024-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-10-CTLFireability-2024-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-10-CTLFireability-2024-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-10-CTLFireability-2024-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-10-CTLFireability-2024-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[[35mlola[0m] [1mFINAL RESULTS[0m
[[35mlola[0m] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m] [1m[32mCO4-PT-10-CTLFireability-2024-00: EF true state space[0m
[[35mlola[0m] [1m[31mCO4-PT-10-CTLFireability-2024-01: AGAF false state space /EFEG[0m
[[35mlola[0m] [1m[31mCO4-PT-10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mCO4-PT-10-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m] [1m[31mCO4-PT-10-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mCO4-PT-10-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mCO4-PT-10-CTLFireability-2024-06: CONJ true CONJ[0m
[[35mlola[0m] [1m[32mCO4-PT-10-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mCO4-PT-10-CTLFireability-2024-08: INITIAL false preprocessing[0m
[[35mlola[0m] [1m[32mCO4-PT-10-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mCO4-PT-10-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mCO4-PT-10-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mCO4-PT-10-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mCO4-PT-10-CTLFireability-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m] [1m[32mCO4-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mCO4-PT-10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m]
[[35mlola[0m] Time elapsed: 138 secs. Pages in use: 13
BK_STOP 1717398295692
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 177 transitions removed,157 places removed
[[35mlola[0m][I] LAUNCH task # 10 (type CNST) for 9 CO4-PT-10-CTLFireability-2024-03
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 10 (type CNST) for CO4-PT-10-CTLFireability-2024-03
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 48 (type CNST) for 47 CO4-PT-10-CTLFireability-2024-13
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 48 (type CNST) for CO4-PT-10-CTLFireability-2024-13
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 33 (type CNST) for 32 CO4-PT-10-CTLFireability-2024-08
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] LAUNCH task # 58 (type EXCL) for 0 CO4-PT-10-CTLFireability-2024-00
[[35mlola[0m][I] time limit : 156 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 56 (type FNDP) for 0 CO4-PT-10-CTLFireability-2024-00
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 57 (type EQUN) for 0 CO4-PT-10-CTLFireability-2024-00
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 33 (type CNST) for CO4-PT-10-CTLFireability-2024-08
[[35mlola[0m][I] result : false
[[35mlola[0m][I] FINISHED task # 58 (type EXCL) for CO4-PT-10-CTLFireability-2024-00
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 6
[[35mlola[0m][I] fired transitions : 5
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 56 (type FNDP) for CO4-PT-10-CTLFireability-2024-00 (obsolete)
[[35mlola[0m][W] CANCELED task # 57 (type EQUN) for CO4-PT-10-CTLFireability-2024-00 (obsolete)
[[35mlola[0m][I] FINISHED task # 56 (type FNDP) for CO4-PT-10-CTLFireability-2024-00
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] FINISHED task # 57 (type EQUN) for CO4-PT-10-CTLFireability-2024-00
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 45 (type EXCL) for 44 CO4-PT-10-CTLFireability-2024-12
[[35mlola[0m][I] time limit : 171 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 65 (type EQUN) for 18 CO4-PT-10-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 67 (type EQUN) for 3 CO4-PT-10-CTLFireability-2024-01
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 70 (type EQUN) for 3 CO4-PT-10-CTLFireability-2024-01
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 67 (type EQUN) for CO4-PT-10-CTLFireability-2024-01
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 73 (type EQUN) for 18 CO4-PT-10-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 70 (type EQUN) for CO4-PT-10-CTLFireability-2024-01
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] FINISHED task # 65 (type EQUN) for CO4-PT-10-CTLFireability-2024-06
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] FINISHED task # 73 (type EQUN) for CO4-PT-10-CTLFireability-2024-06
[[35mlola[0m][I] result : true
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-00: EF true state space[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-01: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-06: CONJ 0 3 0 0 5 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 5/257 3/2000 CO4-PT-10-CTLFireability-2024-12 468649 m, 93729 m/sec, 2805215 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-00: EF true state space[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-01: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-06: CONJ 0 3 0 0 5 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 10/257 4/2000 CO4-PT-10-CTLFireability-2024-12 866186 m, 79507 m/sec, 5493450 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-00: EF true state space[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-01: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-06: CONJ 0 3 0 0 5 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 15/257 6/2000 CO4-PT-10-CTLFireability-2024-12 1297915 m, 86345 m/sec, 8242302 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 15 secs. Pages in use: 6
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-00: EF true state space[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-01: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-06: CONJ 0 3 0 0 5 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 20/257 7/2000 CO4-PT-10-CTLFireability-2024-12 1639861 m, 68389 m/sec, 10962615 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 20 secs. Pages in use: 7
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-00: EF true state space[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-01: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-06: CONJ 0 3 0 0 5 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 25/257 9/2000 CO4-PT-10-CTLFireability-2024-12 2009876 m, 74003 m/sec, 13759496 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 25 secs. Pages in use: 9
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-00: EF true state space[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-01: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-06: CONJ 0 3 0 0 5 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 30/257 10/2000 CO4-PT-10-CTLFireability-2024-12 2357036 m, 69432 m/sec, 16453220 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 30 secs. Pages in use: 10
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-00: EF true state space[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-01: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-06: CONJ 0 3 0 0 5 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 35/257 12/2000 CO4-PT-10-CTLFireability-2024-12 2701724 m, 68937 m/sec, 19153058 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 35 secs. Pages in use: 12
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 45 (type EXCL) for CO4-PT-10-CTLFireability-2024-12
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 2891185
[[35mlola[0m][I] fired transitions : 20478299
[[35mlola[0m][I] time used : 38
[[35mlola[0m][I] memory pages used : 13
[[35mlola[0m][I] LAUNCH task # 61 (type EXCL) for 18 CO4-PT-10-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 274 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 61 (type EXCL) for CO4-PT-10-CTLFireability-2024-06
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 23
[[35mlola[0m][I] fired transitions : 23
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 54 (type EXCL) for 53 CO4-PT-10-CTLFireability-2024-15
[[35mlola[0m][I] time limit : 323 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-00: EF true state space[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-01: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-06: CONJ 0 1 0 0 6 0 0 1
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 2/323 2/2000 CO4-PT-10-CTLFireability-2024-15 308090 m, 61618 m/sec, 1445067 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 40 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-00: EF true state space[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-01: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-06: CONJ 0 1 0 0 6 0 0 1
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 7/323 4/2000 CO4-PT-10-CTLFireability-2024-15 740756 m, 86533 m/sec, 3990410 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 45 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-00: EF true state space[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-01: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-06: CONJ 0 1 0 0 6 0 0 1
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 12/323 6/2000 CO4-PT-10-CTLFireability-2024-15 1221553 m, 96159 m/sec, 6480221 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 50 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-00: EF true state space[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-01: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-06: CONJ 0 1 0 0 6 0 0 1
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 17/323 7/2000 CO4-PT-10-CTLFireability-2024-15 1591600 m, 74009 m/sec, 9000921 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 55 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-00: EF true state space[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-01: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-06: CONJ 0 1 0 0 6 0 0 1
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 22/323 9/2000 CO4-PT-10-CTLFireability-2024-15 1977887 m, 77257 m/sec, 11583267 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 60 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-00: EF true state space[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-01: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-06: CONJ 0 1 0 0 6 0 0 1
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 27/323 10/2000 CO4-PT-10-CTLFireability-2024-15 2333241 m, 71070 m/sec, 14000195 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 65 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-00: EF true state space[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-01: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-06: CONJ 0 1 0 0 6 0 0 1
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 32/323 12/2000 CO4-PT-10-CTLFireability-2024-15 2694654 m, 72282 m/sec, 16469498 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 70 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 54 (type EXCL) for CO4-PT-10-CTLFireability-2024-15
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 2891185
[[35mlola[0m][I] fired transitions : 17663537
[[35mlola[0m][I] time used : 35
[[35mlola[0m][I] memory pages used : 13
[[35mlola[0m][I] LAUNCH task # 51 (type EXCL) for 50 CO4-PT-10-CTLFireability-2024-14
[[35mlola[0m][I] time limit : 352 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 51 (type EXCL) for CO4-PT-10-CTLFireability-2024-14
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 26
[[35mlola[0m][I] fired transitions : 27
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 42 (type EXCL) for 41 CO4-PT-10-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 391 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 42 (type EXCL) for CO4-PT-10-CTLFireability-2024-11
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 342
[[35mlola[0m][I] fired transitions : 733
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 39 (type EXCL) for 38 CO4-PT-10-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 440 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-00: EF true state space[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-01: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-06: CONJ 0 1 0 0 6 0 0 1
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 2/440 2/2000 CO4-PT-10-CTLFireability-2024-10 310815 m, 62163 m/sec, 1451200 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 75 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-00: EF true state space[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-01: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-06: CONJ 0 1 0 0 6 0 0 1
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 7/440 4/2000 CO4-PT-10-CTLFireability-2024-10 746698 m, 87176 m/sec, 4006574 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 80 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-00: EF true state space[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-01: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-06: CONJ 0 1 0 0 6 0 0 1
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 12/440 6/2000 CO4-PT-10-CTLFireability-2024-10 1226324 m, 95925 m/sec, 6476138 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 85 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-00: EF true state space[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-01: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-06: CONJ 0 1 0 0 6 0 0 1
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 17/440 7/2000 CO4-PT-10-CTLFireability-2024-10 1596876 m, 74110 m/sec, 8998707 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 90 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-00: EF true state space[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-01: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-06: CONJ 0 1 0 0 6 0 0 1
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 22/440 9/2000 CO4-PT-10-CTLFireability-2024-10 1981219 m, 76868 m/sec, 11553937 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 95 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-00: EF true state space[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-01: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-06: CONJ 0 1 0 0 6 0 0 1
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 27/440 10/2000 CO4-PT-10-CTLFireability-2024-10 2327156 m, 69187 m/sec, 13899786 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 100 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-00: EF true state space[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-01: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-06: CONJ 0 1 0 0 6 0 0 1
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 32/440 12/2000 CO4-PT-10-CTLFireability-2024-10 2683871 m, 71343 m/sec, 16321920 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 105 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 39 (type EXCL) for CO4-PT-10-CTLFireability-2024-10
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 2891185
[[35mlola[0m][I] fired transitions : 17587114
[[35mlola[0m][I] time used : 35
[[35mlola[0m][I] memory pages used : 13
[[35mlola[0m][I] LAUNCH task # 36 (type EXCL) for 35 CO4-PT-10-CTLFireability-2024-09
[[35mlola[0m][I] time limit : 498 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-00: EF true state space[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-01: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-06: CONJ 0 1 0 0 6 0 0 1
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 2/498 2/2000 CO4-PT-10-CTLFireability-2024-09 347363 m, 69472 m/sec, 1299997 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 110 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-00: EF true state space[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-01: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-06: CONJ 0 1 0 0 6 0 0 1
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 7/498 4/2000 CO4-PT-10-CTLFireability-2024-09 866110 m, 103749 m/sec, 3757837 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 115 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-00: EF true state space[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-01: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-06: CONJ 0 1 0 0 6 0 0 1
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 12/498 6/2000 CO4-PT-10-CTLFireability-2024-09 1391971 m, 105172 m/sec, 6176391 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 120 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-00: EF true state space[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-01: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-06: CONJ 0 1 0 0 6 0 0 1
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 17/498 8/2000 CO4-PT-10-CTLFireability-2024-09 1802655 m, 82136 m/sec, 8550417 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 125 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-00: EF true state space[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-01: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-06: CONJ 0 1 0 0 6 0 0 1
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 22/498 10/2000 CO4-PT-10-CTLFireability-2024-09 2198003 m, 79069 m/sec, 10875704 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 130 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-00: EF true state space[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mCO4-PT-10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mCO4-PT-10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-01: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-06: CONJ 0 1 0 0 6 0 0 1
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-10-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 27/498 11/2000 CO4-PT-10-CTLFireability-2024-09 2628294 m, 86058 m/sec, 13284810 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 135 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 36 (type EXCL) for CO4-PT-10-CTLFireability-2024-09
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 2891185
[[35mlola[0m][I] fired transitions : 14686285
[[35mlola[0m][I] time used : 30
[[35mlola[0m][I] memory pages used : 13
[[35mlola[0m][I] LAUNCH task # 16 (type EXCL) for 15 CO4-PT-10-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 577 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 16 (type EXCL) for CO4-PT-10-CTLFireability-2024-05
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 509
[[35mlola[0m][I] fired transitions : 2376
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 13 (type EXCL) for 12 CO4-PT-10-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 692 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 13 (type EXCL) for CO4-PT-10-CTLFireability-2024-04
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 4261
[[35mlola[0m][I] fired transitions : 8527
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 7 (type EXCL) for 6 CO4-PT-10-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 865 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 7 (type EXCL) for CO4-PT-10-CTLFireability-2024-02
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1511
[[35mlola[0m][I] fired transitions : 3673
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 60 (type EXCL) for 3 CO4-PT-10-CTLFireability-2024-01
[[35mlola[0m][I] time limit : 1154 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 60 (type EXCL) for CO4-PT-10-CTLFireability-2024-01
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 8
[[35mlola[0m][I] fired transitions : 8
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 68 (type EXCL) for 18 CO4-PT-10-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 1731 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 68 (type EXCL) for CO4-PT-10-CTLFireability-2024-06
[[35mlola[0m][I] result : true
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 30 (type EXCL) for 29 CO4-PT-10-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 3462 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 30 (type EXCL) for CO4-PT-10-CTLFireability-2024-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 481
[[35mlola[0m][I] fired transitions : 1633
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] Portfolio finished: no open formulas
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="CO4-PT-10"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is CO4-PT-10, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r551-tall-171734899300074"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/CO4-PT-10.tgz
mv CO4-PT-10 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;