About the Execution of LoLA for CO4-PT-07
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 386.924 | 38525.00 | 39074.00 | 210.00 | FFTFFFFTFTTTFTFT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r551-tall-171734899200050.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
..........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is CO4-PT-07, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r551-tall-171734899200050
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 540K
-rw-r--r-- 1 mcc users 5.7K Jun 2 17:16 CTLCardinality.txt
-rw-r--r-- 1 mcc users 61K Jun 2 17:16 CTLCardinality.xml
-rw-r--r-- 1 mcc users 7.1K Jun 2 17:16 CTLFireability.txt
-rw-r--r-- 1 mcc users 73K Jun 2 17:16 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.5K Jun 2 17:12 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Jun 2 17:12 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Jun 2 17:12 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Jun 2 17:12 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 Jun 2 16:33 NewModel
-rw-r--r-- 1 mcc users 12K Jun 2 17:16 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 129K Jun 2 17:16 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 6.7K Jun 2 17:16 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 56K Jun 2 17:16 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.5K Jun 2 17:12 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.5K Jun 2 17:12 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Jun 2 16:33 equiv_col
-rw-r--r-- 1 mcc users 3 Jun 2 16:33 instance
-rw-r--r-- 1 mcc users 6 Jun 2 16:33 iscolored
-rw-r--r-- 1 mcc users 98K Jun 2 16:33 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME CO4-PT-07-CTLFireability-2024-00
FORMULA_NAME CO4-PT-07-CTLFireability-2024-01
FORMULA_NAME CO4-PT-07-CTLFireability-2024-02
FORMULA_NAME CO4-PT-07-CTLFireability-2024-03
FORMULA_NAME CO4-PT-07-CTLFireability-2024-04
FORMULA_NAME CO4-PT-07-CTLFireability-2024-05
FORMULA_NAME CO4-PT-07-CTLFireability-2024-06
FORMULA_NAME CO4-PT-07-CTLFireability-2024-07
FORMULA_NAME CO4-PT-07-CTLFireability-2024-08
FORMULA_NAME CO4-PT-07-CTLFireability-2024-09
FORMULA_NAME CO4-PT-07-CTLFireability-2024-10
FORMULA_NAME CO4-PT-07-CTLFireability-2024-11
FORMULA_NAME CO4-PT-07-CTLFireability-2024-12
FORMULA_NAME CO4-PT-07-CTLFireability-2024-13
FORMULA_NAME CO4-PT-07-CTLFireability-2024-14
FORMULA_NAME CO4-PT-07-CTLFireability-2024-15
=== Now, execution of the tool begins
BK_START 1717397320178
FORMULA CO4-PT-07-CTLFireability-2024-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-07-CTLFireability-2024-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-07-CTLFireability-2024-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-07-CTLFireability-2024-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-07-CTLFireability-2024-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-07-CTLFireability-2024-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-07-CTLFireability-2024-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-07-CTLFireability-2024-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-07-CTLFireability-2024-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-07-CTLFireability-2024-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-07-CTLFireability-2024-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-07-CTLFireability-2024-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-07-CTLFireability-2024-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-07-CTLFireability-2024-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-07-CTLFireability-2024-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-07-CTLFireability-2024-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[[35mlola[0m] [1mFINAL RESULTS[0m
[[35mlola[0m] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m] [1m[31mCO4-PT-07-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mCO4-PT-07-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mCO4-PT-07-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mCO4-PT-07-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mCO4-PT-07-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mCO4-PT-07-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mCO4-PT-07-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mCO4-PT-07-CTLFireability-2024-07: EFEG true state space /EFEG[0m
[[35mlola[0m] [1m[31mCO4-PT-07-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mCO4-PT-07-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mCO4-PT-07-CTLFireability-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m] [1m[32mCO4-PT-07-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mCO4-PT-07-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mCO4-PT-07-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m] [1m[31mCO4-PT-07-CTLFireability-2024-14: DISJ false DISJ[0m
[[35mlola[0m] [1m[32mCO4-PT-07-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m]
[[35mlola[0m] Time elapsed: 38 secs. Pages in use: 6
BK_STOP 1717397358703
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 120 transitions removed,100 places removed
[[35mlola[0m][I] LAUNCH task # 1 (type EXCL) for 0 CO4-PT-07-CTLFireability-2024-00
[[35mlola[0m][I] time limit : 156 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 1 (type EXCL) for CO4-PT-07-CTLFireability-2024-00
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 124
[[35mlola[0m][I] fired transitions : 156
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 40 (type CNST) for 39 CO4-PT-07-CTLFireability-2024-13
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 40 (type CNST) for CO4-PT-07-CTLFireability-2024-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 31 (type CNST) for 30 CO4-PT-07-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 31 (type CNST) for CO4-PT-07-CTLFireability-2024-10
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 34 (type EXCL) for 33 CO4-PT-07-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 240 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 34 (type EXCL) for CO4-PT-07-CTLFireability-2024-11
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 51
[[35mlola[0m][I] fired transitions : 55
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 19 (type EXCL) for 18 CO4-PT-07-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 257 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 19 (type EXCL) for CO4-PT-07-CTLFireability-2024-06
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 30
[[35mlola[0m][I] fired transitions : 56
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 16 (type EXCL) for 15 CO4-PT-07-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 276 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 55 (type EQUN) for 21 CO4-PT-07-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 57 (type EQUN) for 21 CO4-PT-07-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 55 (type EQUN) for CO4-PT-07-CTLFireability-2024-07
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] LAUNCH task # 59 (type FNDP) for 42 CO4-PT-07-CTLFireability-2024-14
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 60 (type EQUN) for 42 CO4-PT-07-CTLFireability-2024-14
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 57 (type EQUN) for CO4-PT-07-CTLFireability-2024-07
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] FINISHED task # 60 (type EQUN) for CO4-PT-07-CTLFireability-2024-14
[[35mlola[0m][I] result : true
[[35mlola[0m][W] CANCELED task # 59 (type FNDP) for CO4-PT-07-CTLFireability-2024-14 (obsolete)
[[35mlola[0m][I] FINISHED task # 59 (type FNDP) for CO4-PT-07-CTLFireability-2024-14
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCO4-PT-07-CTLFireability-2024-00: CTL false CTL model checker[0m
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[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-07-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-07-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-07-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-07-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-07-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-07-CTLFireability-2024-07: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] CO4-PT-07-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-07-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-07-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-07-CTLFireability-2024-14: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] CO4-PT-07-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 5/327 4/2000 CO4-PT-07-CTLFireability-2024-05 837363 m, 167472 m/sec, 3288143 t fired, .
[[35mlola[0m][.]
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[[35mlola[0m][.] CO4-PT-07-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-07-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-07-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] CO4-PT-07-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-07-CTLFireability-2024-07: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] CO4-PT-07-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-07-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-07-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-07-CTLFireability-2024-14: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] CO4-PT-07-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 10/327 5/2000 CO4-PT-07-CTLFireability-2024-05 1020264 m, 36580 m/sec, 6812098 t fired, .
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[[35mlola[0m][.] CO4-PT-07-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-07-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-07-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-07-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-07-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-07-CTLFireability-2024-07: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] CO4-PT-07-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-07-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-07-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-07-CTLFireability-2024-14: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] CO4-PT-07-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 15/327 5/2000 CO4-PT-07-CTLFireability-2024-05 1106779 m, 17303 m/sec, 10166896 t fired, .
[[35mlola[0m][.]
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[[35mlola[0m][.] 16 CTL EXCL 20/327 6/2000 CO4-PT-07-CTLFireability-2024-05 1187421 m, 16128 m/sec, 13635203 t fired, .
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[[35mlola[0m][.] 16 CTL EXCL 25/327 6/2000 CO4-PT-07-CTLFireability-2024-05 1295123 m, 21540 m/sec, 17094427 t fired, .
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[[35mlola[0m][I] LAUNCH task # 50 (type EXCL) for 49 CO4-PT-07-CTLFireability-2024-15
[[35mlola[0m][I] time limit : 357 sec
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[[35mlola[0m][I] FINISHED task # 50 (type EXCL) for CO4-PT-07-CTLFireability-2024-15
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[[35mlola[0m][I] LAUNCH task # 45 (type EXCL) for 42 CO4-PT-07-CTLFireability-2024-14
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[[35mlola[0m][I] LAUNCH task # 13 (type EXCL) for 12 CO4-PT-07-CTLFireability-2024-04
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[[35mlola[0m][I] LAUNCH task # 10 (type EXCL) for 9 CO4-PT-07-CTLFireability-2024-03
[[35mlola[0m][I] time limit : 712 sec
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[[35mlola[0m][I] FINISHED task # 10 (type EXCL) for CO4-PT-07-CTLFireability-2024-03
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[[35mlola[0m][I] FINISHED task # 7 (type EXCL) for CO4-PT-07-CTLFireability-2024-02
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[[35mlola[0m][I] LAUNCH task # 4 (type EXCL) for 3 CO4-PT-07-CTLFireability-2024-01
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[[35mlola[0m][I] LAUNCH task # 52 (type EXCL) for 21 CO4-PT-07-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 1781 sec
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[[35mlola[0m][I] FINISHED task # 52 (type EXCL) for CO4-PT-07-CTLFireability-2024-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 8
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[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 25 (type EXCL) for 24 CO4-PT-07-CTLFireability-2024-08
[[35mlola[0m][I] time limit : 3562 sec
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[[35mlola[0m][I] FINISHED task # 25 (type EXCL) for CO4-PT-07-CTLFireability-2024-08
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 8
[[35mlola[0m][I] fired transitions : 22
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[[35mlola[0m][I] Portfolio finished: no open formulas
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="CO4-PT-07"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is CO4-PT-07, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r551-tall-171734899200050"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/CO4-PT-07.tgz
mv CO4-PT-07 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;