Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r551-tall-171734899200042.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.....................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is CO4-PT-06, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r551-tall-171734899200042
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 492K
-rw-r--r-- 1 mcc users 5.9K Jun 2 17:16 CTLCardinality.txt
-rw-r--r-- 1 mcc users 64K Jun 2 17:16 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.1K Jun 2 17:16 CTLFireability.txt
-rw-r--r-- 1 mcc users 48K Jun 2 17:16 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.2K Jun 2 17:12 LTLCardinality.txt
-rw-r--r-- 1 mcc users 22K Jun 2 17:12 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Jun 2 17:12 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Jun 2 17:12 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 Jun 2 16:33 NewModel
-rw-r--r-- 1 mcc users 7.5K Jun 2 17:16 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 76K Jun 2 17:16 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.8K Jun 2 17:16 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 89K Jun 2 17:16 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.5K Jun 2 17:12 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.5K Jun 2 17:12 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Jun 2 16:33 equiv_col
-rw-r--r-- 1 mcc users 3 Jun 2 16:33 instance
-rw-r--r-- 1 mcc users 6 Jun 2 16:33 iscolored
-rw-r--r-- 1 mcc users 97K Jun 2 16:33 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME CO4-PT-06-CTLFireability-2024-00
FORMULA_NAME CO4-PT-06-CTLFireability-2024-01
FORMULA_NAME CO4-PT-06-CTLFireability-2024-02
FORMULA_NAME CO4-PT-06-CTLFireability-2024-03
FORMULA_NAME CO4-PT-06-CTLFireability-2024-04
FORMULA_NAME CO4-PT-06-CTLFireability-2024-05
FORMULA_NAME CO4-PT-06-CTLFireability-2024-06
FORMULA_NAME CO4-PT-06-CTLFireability-2024-07
FORMULA_NAME CO4-PT-06-CTLFireability-2024-08
FORMULA_NAME CO4-PT-06-CTLFireability-2024-09
FORMULA_NAME CO4-PT-06-CTLFireability-2024-10
FORMULA_NAME CO4-PT-06-CTLFireability-2024-11
FORMULA_NAME CO4-PT-06-CTLFireability-2024-12
FORMULA_NAME CO4-PT-06-CTLFireability-2024-13
FORMULA_NAME CO4-PT-06-CTLFireability-2024-14
FORMULA_NAME CO4-PT-06-CTLFireability-2024-15

=== Now, execution of the tool begins

BK_START 1717397293227

FORMULA CO4-PT-06-CTLFireability-2024-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-06-CTLFireability-2024-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-06-CTLFireability-2024-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-06-CTLFireability-2024-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-06-CTLFireability-2024-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-06-CTLFireability-2024-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-06-CTLFireability-2024-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-06-CTLFireability-2024-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-06-CTLFireability-2024-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-06-CTLFireability-2024-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-06-CTLFireability-2024-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-06-CTLFireability-2024-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-06-CTLFireability-2024-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-06-CTLFireability-2024-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-06-CTLFireability-2024-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-06-CTLFireability-2024-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[lola] FINAL RESULTS
[lola]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola] CO4-PT-06-CTLFireability-2024-00: CTL false CTL model checker
[lola] CO4-PT-06-CTLFireability-2024-01: CTL false CTL model checker
[lola] CO4-PT-06-CTLFireability-2024-02: CTL false CTL model checker
[lola] CO4-PT-06-CTLFireability-2024-03: INITIAL false preprocessing
[lola] CO4-PT-06-CTLFireability-2024-04: EF true state equation
[lola] CO4-PT-06-CTLFireability-2024-05: CTL false CTL model checker
[lola] CO4-PT-06-CTLFireability-2024-06: CTL true CTL model checker
[lola] CO4-PT-06-CTLFireability-2024-07: CTL false CTL model checker
[lola] CO4-PT-06-CTLFireability-2024-08: INITIAL true preprocessing
[lola] CO4-PT-06-CTLFireability-2024-09: CTL false CTL model checker
[lola] CO4-PT-06-CTLFireability-2024-10: CTL false CTL model checker
[lola] CO4-PT-06-CTLFireability-2024-11: CTL true CTL model checker
[lola] CO4-PT-06-CTLFireability-2024-12: INITIAL true preprocessing
[lola] CO4-PT-06-CTLFireability-2024-13: CTL false CTL model checker
[lola] CO4-PT-06-CTLFireability-2024-14: CTL false CTL model checker
[lola] CO4-PT-06-CTLFireability-2024-15: CTL true CTL model checker
[lola]
[lola] Time elapsed: 33 secs. Pages in use: 5

BK_STOP 1717397326925

--------------------
content from stderr:

[lola][I] LoLA will run for 3600 seconds at most (--timelimit)
[lola][W] unknown unit in memory specification: using default
[lola][I] MEM LIMIT 5
[lola][I] NET
[lola][I] reading net from model.pnml
[lola][I] input: PNML file (--pnmlnet)
[lola][I] reading pnml
[lola][I] PNML file contains place/transition net
[lola][I] closed net file model.pnml
[lola][I] finished parsing
[lola][I] Reading formula.
[lola][I] Using XML format (--xmlformula)
[lola][I] reading XML formula
[lola][I] reading formula from CTLFireability.xml
[lola][I] Rule S: 120 transitions removed,100 places removed
[lola][I] LAUNCH task # 37 (type CNST) for 36 CO4-PT-06-CTLFireability-2024-12
[lola][I] time limit : 0 sec
[lola][I] memory limit: 0 pages
[lola][I] FINISHED task # 37 (type CNST) for CO4-PT-06-CTLFireability-2024-12
[lola][I] result : true
[lola][I] LAUNCH task # 16 (type EXCL) for 15 CO4-PT-06-CTLFireability-2024-05
[lola][I] time limit : 189 sec
[lola][I] memory limit: 2000 pages
[lola][I] LAUNCH task # 48 (type FNDP) for 12 CO4-PT-06-CTLFireability-2024-04
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 49 (type EQUN) for 12 CO4-PT-06-CTLFireability-2024-04
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 49 (type EQUN) for CO4-PT-06-CTLFireability-2024-04
[lola][I] result : true
[lola][W] CANCELED task # 48 (type FNDP) for CO4-PT-06-CTLFireability-2024-04 (obsolete)
[lola][I] FINISHED task # 48 (type FNDP) for CO4-PT-06-CTLFireability-2024-04
[lola][I] result : true
[lola][I] tried executions : 1
[lola][I] time used : 0
[lola][I] memory pages used : 0
[lola][I] LAUNCH task # 25 (type CNST) for 24 CO4-PT-06-CTLFireability-2024-08
[lola][I] time limit : 0 sec
[lola][I] memory limit: 0 pages
[lola][I] FINISHED task # 25 (type CNST) for CO4-PT-06-CTLFireability-2024-08
[lola][I] result : true
[lola][I] LAUNCH task # 10 (type CNST) for 9 CO4-PT-06-CTLFireability-2024-03
[lola][I] time limit : 0 sec
[lola][I] memory limit: 0 pages
[lola][I] FINISHED task # 10 (type CNST) for CO4-PT-06-CTLFireability-2024-03
[lola][I] result : false
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] CO4-PT-06-CTLFireability-2024-03: INITIAL false preprocessing
[lola][.] CO4-PT-06-CTLFireability-2024-04: EF true state equation
[lola][.] CO4-PT-06-CTLFireability-2024-08: INITIAL true preprocessing
[lola][.] CO4-PT-06-CTLFireability-2024-12: INITIAL true preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] CO4-PT-06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-06-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-06-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] CO4-PT-06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-06-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-06-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 5/299 2/2000 CO4-PT-06-CTLFireability-2024-05 313271 m, 62654 m/sec, 3650535 t fired, .
[lola][.]
[lola][.] Time elapsed: 6 secs. Pages in use: 2
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] CO4-PT-06-CTLFireability-2024-03: INITIAL false preprocessing
[lola][.] CO4-PT-06-CTLFireability-2024-04: EF true state equation
[lola][.] CO4-PT-06-CTLFireability-2024-08: INITIAL true preprocessing
[lola][.] CO4-PT-06-CTLFireability-2024-12: INITIAL true preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] CO4-PT-06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-06-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-06-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] CO4-PT-06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-06-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-06-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 10/299 3/2000 CO4-PT-06-CTLFireability-2024-05 610115 m, 59368 m/sec, 7259978 t fired, .
[lola][.]
[lola][.] Time elapsed: 11 secs. Pages in use: 3
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] CO4-PT-06-CTLFireability-2024-03: INITIAL false preprocessing
[lola][.] CO4-PT-06-CTLFireability-2024-04: EF true state equation
[lola][.] CO4-PT-06-CTLFireability-2024-08: INITIAL true preprocessing
[lola][.] CO4-PT-06-CTLFireability-2024-12: INITIAL true preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] CO4-PT-06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-06-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-06-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] CO4-PT-06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-06-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-06-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 15/299 4/2000 CO4-PT-06-CTLFireability-2024-05 853758 m, 48728 m/sec, 10924169 t fired, .
[lola][.]
[lola][.] Time elapsed: 16 secs. Pages in use: 4
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] CO4-PT-06-CTLFireability-2024-03: INITIAL false preprocessing
[lola][.] CO4-PT-06-CTLFireability-2024-04: EF true state equation
[lola][.] CO4-PT-06-CTLFireability-2024-08: INITIAL true preprocessing
[lola][.] CO4-PT-06-CTLFireability-2024-12: INITIAL true preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] CO4-PT-06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-06-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-06-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] CO4-PT-06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-06-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-06-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 20/299 5/2000 CO4-PT-06-CTLFireability-2024-05 1105304 m, 50309 m/sec, 14556696 t fired, .
[lola][.]
[lola][.] Time elapsed: 21 secs. Pages in use: 5
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I] FINISHED task # 16 (type EXCL) for CO4-PT-06-CTLFireability-2024-05
[lola][I] result : false
[lola][I] markings : 1108499
[lola][I] fired transitions : 14597486
[lola][I] time used : 20
[lola][I] memory pages used : 5
[lola][I] LAUNCH task # 46 (type EXCL) for 45 CO4-PT-06-CTLFireability-2024-15
[lola][I] time limit : 325 sec
[lola][I] memory limit: 2000 pages
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] CO4-PT-06-CTLFireability-2024-03: INITIAL false preprocessing
[lola][.] CO4-PT-06-CTLFireability-2024-04: EF true state equation
[lola][.] CO4-PT-06-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] CO4-PT-06-CTLFireability-2024-08: INITIAL true preprocessing
[lola][.] CO4-PT-06-CTLFireability-2024-12: INITIAL true preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] CO4-PT-06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-06-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-06-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-06-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 46 CTL EXCL 5/325 3/2000 CO4-PT-06-CTLFireability-2024-15 651711 m, 130342 m/sec, 3663571 t fired, .
[lola][.]
[lola][.] Time elapsed: 26 secs. Pages in use: 5
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I] FINISHED task # 46 (type EXCL) for CO4-PT-06-CTLFireability-2024-15
[lola][I] result : true
[lola][I] markings : 1108498
[lola][I] fired transitions : 6716854
[lola][I] time used : 9
[lola][I] memory pages used : 5
[lola][I] LAUNCH task # 43 (type EXCL) for 42 CO4-PT-06-CTLFireability-2024-14
[lola][I] time limit : 357 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 43 (type EXCL) for CO4-PT-06-CTLFireability-2024-14
[lola][I] result : false
[lola][I] markings : 22
[lola][I] fired transitions : 21
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 40 (type EXCL) for 39 CO4-PT-06-CTLFireability-2024-13
[lola][I] time limit : 396 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 40 (type EXCL) for CO4-PT-06-CTLFireability-2024-13
[lola][I] result : false
[lola][I] markings : 1
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 34 (type EXCL) for 33 CO4-PT-06-CTLFireability-2024-11
[lola][I] time limit : 446 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 34 (type EXCL) for CO4-PT-06-CTLFireability-2024-11
[lola][I] result : true
[lola][I] markings : 291
[lola][I] fired transitions : 484
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 28 (type EXCL) for 27 CO4-PT-06-CTLFireability-2024-09
[lola][I] time limit : 510 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 28 (type EXCL) for CO4-PT-06-CTLFireability-2024-09
[lola][I] result : false
[lola][I] markings : 51
[lola][I] fired transitions : 179
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 22 (type EXCL) for 21 CO4-PT-06-CTLFireability-2024-07
[lola][I] time limit : 595 sec
[lola][I] memory limit: 2000 pages
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] CO4-PT-06-CTLFireability-2024-03: INITIAL false preprocessing
[lola][.] CO4-PT-06-CTLFireability-2024-04: EF true state equation
[lola][.] CO4-PT-06-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] CO4-PT-06-CTLFireability-2024-08: INITIAL true preprocessing
[lola][.] CO4-PT-06-CTLFireability-2024-09: CTL false CTL model checker
[lola][.] CO4-PT-06-CTLFireability-2024-11: CTL true CTL model checker
[lola][.] CO4-PT-06-CTLFireability-2024-12: INITIAL true preprocessing
[lola][.] CO4-PT-06-CTLFireability-2024-13: CTL false CTL model checker
[lola][.] CO4-PT-06-CTLFireability-2024-14: CTL false CTL model checker
[lola][.] CO4-PT-06-CTLFireability-2024-15: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] CO4-PT-06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-06-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-06-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[lola][.] CO4-PT-06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 22 CTL EXCL 1/595 1/2000 CO4-PT-06-CTLFireability-2024-07 216871 m, 43374 m/sec, 561319 t fired, .
[lola][.]
[lola][.] Time elapsed: 31 secs. Pages in use: 5
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I] FINISHED task # 22 (type EXCL) for CO4-PT-06-CTLFireability-2024-07
[lola][I] result : false
[lola][I] markings : 746030
[lola][I] fired transitions : 2341406
[lola][I] time used : 3
[lola][I] memory pages used : 4
[lola][I] LAUNCH task # 19 (type EXCL) for 18 CO4-PT-06-CTLFireability-2024-06
[lola][I] time limit : 713 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 19 (type EXCL) for CO4-PT-06-CTLFireability-2024-06
[lola][I] result : true
[lola][I] markings : 24
[lola][I] fired transitions : 71
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 7 (type EXCL) for 6 CO4-PT-06-CTLFireability-2024-02
[lola][I] time limit : 891 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 7 (type EXCL) for CO4-PT-06-CTLFireability-2024-02
[lola][I] result : false
[lola][I] markings : 24
[lola][I] fired transitions : 50
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 4 (type EXCL) for 3 CO4-PT-06-CTLFireability-2024-01
[lola][I] time limit : 1189 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 4 (type EXCL) for CO4-PT-06-CTLFireability-2024-01
[lola][I] result : false
[lola][I] markings : 39
[lola][I] fired transitions : 101
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 1 (type EXCL) for 0 CO4-PT-06-CTLFireability-2024-00
[lola][I] time limit : 1783 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 1 (type EXCL) for CO4-PT-06-CTLFireability-2024-00
[lola][I] result : false
[lola][I] markings : 48
[lola][I] fired transitions : 71
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 31 (type EXCL) for 30 CO4-PT-06-CTLFireability-2024-10
[lola][I] time limit : 3567 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 31 (type EXCL) for CO4-PT-06-CTLFireability-2024-10
[lola][I] result : false
[lola][I] markings : 14109
[lola][I] fired transitions : 69280
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] Portfolio finished: no open formulas

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="CO4-PT-06"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is CO4-PT-06, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r551-tall-171734899200042"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/CO4-PT-06.tgz
mv CO4-PT-06 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;