Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r551-tall-171734899200026.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
..............................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is CO4-PT-04, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r551-tall-171734899200026
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 584K
-rw-r--r-- 1 mcc users 8.0K Jun 2 17:16 CTLCardinality.txt
-rw-r--r-- 1 mcc users 96K Jun 2 17:16 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.7K Jun 2 17:16 CTLFireability.txt
-rw-r--r-- 1 mcc users 44K Jun 2 17:16 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.8K Jun 2 17:12 LTLCardinality.txt
-rw-r--r-- 1 mcc users 29K Jun 2 17:12 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.0K Jun 2 17:12 LTLFireability.txt
-rw-r--r-- 1 mcc users 15K Jun 2 17:12 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 Jun 2 16:33 NewModel
-rw-r--r-- 1 mcc users 16K Jun 2 17:16 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 186K Jun 2 17:16 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.4K Jun 2 17:16 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 74K Jun 2 17:16 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.5K Jun 2 17:12 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.5K Jun 2 17:12 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Jun 2 16:33 equiv_col
-rw-r--r-- 1 mcc users 3 Jun 2 16:33 instance
-rw-r--r-- 1 mcc users 6 Jun 2 16:33 iscolored
-rw-r--r-- 1 mcc users 53K Jun 2 16:33 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME CO4-PT-04-CTLFireability-2024-00
FORMULA_NAME CO4-PT-04-CTLFireability-2024-01
FORMULA_NAME CO4-PT-04-CTLFireability-2024-02
FORMULA_NAME CO4-PT-04-CTLFireability-2024-03
FORMULA_NAME CO4-PT-04-CTLFireability-2024-04
FORMULA_NAME CO4-PT-04-CTLFireability-2024-05
FORMULA_NAME CO4-PT-04-CTLFireability-2024-06
FORMULA_NAME CO4-PT-04-CTLFireability-2024-07
FORMULA_NAME CO4-PT-04-CTLFireability-2024-08
FORMULA_NAME CO4-PT-04-CTLFireability-2024-09
FORMULA_NAME CO4-PT-04-CTLFireability-2024-10
FORMULA_NAME CO4-PT-04-CTLFireability-2024-11
FORMULA_NAME CO4-PT-04-CTLFireability-2024-12
FORMULA_NAME CO4-PT-04-CTLFireability-2024-13
FORMULA_NAME CO4-PT-04-CTLFireability-2024-14
FORMULA_NAME CO4-PT-04-CTLFireability-2024-15

=== Now, execution of the tool begins

BK_START 1717397214152

FORMULA CO4-PT-04-CTLFireability-2024-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-04-CTLFireability-2024-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-04-CTLFireability-2024-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-04-CTLFireability-2024-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-04-CTLFireability-2024-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-04-CTLFireability-2024-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-04-CTLFireability-2024-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-04-CTLFireability-2024-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-04-CTLFireability-2024-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-04-CTLFireability-2024-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-04-CTLFireability-2024-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-04-CTLFireability-2024-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-04-CTLFireability-2024-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-04-CTLFireability-2024-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-04-CTLFireability-2024-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-04-CTLFireability-2024-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[lola] FINAL RESULTS
[lola]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola] CO4-PT-04-CTLFireability-2024-00: CTL false CTL model checker
[lola] CO4-PT-04-CTLFireability-2024-01: CTL true CTL model checker
[lola] CO4-PT-04-CTLFireability-2024-02: CTL false CTL model checker
[lola] CO4-PT-04-CTLFireability-2024-03: CTL true CTL model checker
[lola] CO4-PT-04-CTLFireability-2024-04: CTL false CTL model checker
[lola] CO4-PT-04-CTLFireability-2024-05: CTL false CTL model checker
[lola] CO4-PT-04-CTLFireability-2024-06: DISJ false DISJ
[lola] CO4-PT-04-CTLFireability-2024-07: CTL true CTL model checker
[lola] CO4-PT-04-CTLFireability-2024-08: CTL true CTL model checker
[lola] CO4-PT-04-CTLFireability-2024-09: CTL false CTL model checker
[lola] CO4-PT-04-CTLFireability-2024-10: CTL true CTL model checker
[lola] CO4-PT-04-CTLFireability-2024-11: CTL false CTL model checker
[lola] CO4-PT-04-CTLFireability-2024-12: CONJ false state space /EXEG
[lola] CO4-PT-04-CTLFireability-2024-13: SP ECTL true LTL model checker
[lola] CO4-PT-04-CTLFireability-2024-14: DISJ true state space /EU
[lola] CO4-PT-04-CTLFireability-2024-15: F false state space / EG
[lola]
[lola] Time elapsed: 28 secs. Pages in use: 5

BK_STOP 1717397242429

--------------------
content from stderr:

[lola][I] LoLA will run for 3600 seconds at most (--timelimit)
[lola][W] unknown unit in memory specification: using default
[lola][I] MEM LIMIT 5
[lola][I] NET
[lola][I] reading net from model.pnml
[lola][I] input: PNML file (--pnmlnet)
[lola][I] reading pnml
[lola][I] PNML file contains place/transition net
[lola][I] closed net file model.pnml
[lola][I] finished parsing
[lola][I] Reading formula.
[lola][I] Using XML format (--xmlformula)
[lola][I] reading XML formula
[lola][I] reading formula from CTLFireability.xml
[lola][I] Rule S: 0 transitions removed,0 places removed
[lola][I] LAUNCH task # 26 (type EXCL) for 25 CO4-PT-04-CTLFireability-2024-07
[lola][I] time limit : 171 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 26 (type EXCL) for CO4-PT-04-CTLFireability-2024-07
[lola][I] result : true
[lola][I] markings : 383
[lola][I] fired transitions : 1251
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 10 (type EXCL) for 9 CO4-PT-04-CTLFireability-2024-03
[lola][I] time limit : 180 sec
[lola][I] memory limit: 2000 pages
[lola][I] LAUNCH task # 76 (type EQUN) for 40 CO4-PT-04-CTLFireability-2024-12
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 78 (type EQUN) for 54 CO4-PT-04-CTLFireability-2024-14
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 83 (type EQUN) for 65 CO4-PT-04-CTLFireability-2024-15
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 78 (type EQUN) for CO4-PT-04-CTLFireability-2024-14
[lola][I] result : true
[lola][I] FINISHED task # 76 (type EQUN) for CO4-PT-04-CTLFireability-2024-12
[lola][I] result : true
[lola][I] FINISHED task # 83 (type EQUN) for CO4-PT-04-CTLFireability-2024-15
[lola][I] result : unknown
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] CO4-PT-04-CTLFireability-2024-07: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] CO4-PT-04-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-04-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-04-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[lola][.] CO4-PT-04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-04-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-04-CTLFireability-2024-06: DISJ 0 2 0 0 2 0 0 0
[lola][.] CO4-PT-04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-04-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-04-CTLFireability-2024-12: CONJ 0 3 0 0 4 0 0 0
[lola][.] CO4-PT-04-CTLFireability-2024-13: SP ECTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-04-CTLFireability-2024-14: DISJ 0 3 0 0 4 0 0 0
[lola][.] CO4-PT-04-CTLFireability-2024-15: F 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 10 CTL EXCL 5/180 4/2000 CO4-PT-04-CTLFireability-2024-03 903696 m, 180739 m/sec, 6992493 t fired, .
[lola][.]
[lola][.] Time elapsed: 5 secs. Pages in use: 4
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I] FINISHED task # 10 (type EXCL) for CO4-PT-04-CTLFireability-2024-03
[lola][I] result : true
[lola][I] markings : 1103234
[lola][I] fired transitions : 8711915
[lola][I] time used : 6
[lola][I] memory pages used : 5
[lola][I] LAUNCH task # 72 (type EXCL) for 40 CO4-PT-04-CTLFireability-2024-12
[lola][I] time limit : 189 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 72 (type EXCL) for CO4-PT-04-CTLFireability-2024-12
[lola][I] result : true
[lola][I] markings : 12
[lola][I] fired transitions : 12
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 63 (type EXCL) for 54 CO4-PT-04-CTLFireability-2024-14
[lola][I] time limit : 224 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 63 (type EXCL) for CO4-PT-04-CTLFireability-2024-14
[lola][I] result : false
[lola][I] markings : 1
[lola][I] fired transitions : 1
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 38 (type EXCL) for 37 CO4-PT-04-CTLFireability-2024-11
[lola][I] time limit : 256 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 38 (type EXCL) for CO4-PT-04-CTLFireability-2024-11
[lola][I] result : false
[lola][I] markings : 3008
[lola][I] fired transitions : 7637
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 32 (type EXCL) for 31 CO4-PT-04-CTLFireability-2024-09
[lola][I] time limit : 276 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 32 (type EXCL) for CO4-PT-04-CTLFireability-2024-09
[lola][I] result : false
[lola][I] markings : 190
[lola][I] fired transitions : 951
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 29 (type EXCL) for 28 CO4-PT-04-CTLFireability-2024-08
[lola][I] time limit : 299 sec
[lola][I] memory limit: 2000 pages
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] CO4-PT-04-CTLFireability-2024-03: CTL true CTL model checker
[lola][.] CO4-PT-04-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] CO4-PT-04-CTLFireability-2024-09: CTL false CTL model checker
[lola][.] CO4-PT-04-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] CO4-PT-04-CTLFireability-2024-12: CONJ false state space /EXEG
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] CO4-PT-04-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-04-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-04-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-04-CTLFireability-2024-06: DISJ 0 2 0 0 2 0 0 0
[lola][.] CO4-PT-04-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] CO4-PT-04-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-04-CTLFireability-2024-13: SP ECTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-04-CTLFireability-2024-14: DISJ 0 1 0 0 5 0 0 1
[lola][.] CO4-PT-04-CTLFireability-2024-15: F 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 29 CTL EXCL 4/299 3/2000 CO4-PT-04-CTLFireability-2024-08 700727 m, 140145 m/sec, 5305154 t fired, .
[lola][.]
[lola][.] Time elapsed: 10 secs. Pages in use: 5
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I] FINISHED task # 29 (type EXCL) for CO4-PT-04-CTLFireability-2024-08
[lola][I] result : true
[lola][I] markings : 1103234
[lola][I] fired transitions : 8704790
[lola][I] time used : 6
[lola][I] memory pages used : 5
[lola][I] LAUNCH task # 23 (type EXCL) for 18 CO4-PT-04-CTLFireability-2024-06
[lola][I] time limit : 326 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 23 (type EXCL) for CO4-PT-04-CTLFireability-2024-06
[lola][I] result : false
[lola][I] markings : 1
[lola][I] fired transitions : 1
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 16 (type EXCL) for 15 CO4-PT-04-CTLFireability-2024-05
[lola][I] time limit : 358 sec
[lola][I] memory limit: 2000 pages
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] CO4-PT-04-CTLFireability-2024-03: CTL true CTL model checker
[lola][.] CO4-PT-04-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] CO4-PT-04-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] CO4-PT-04-CTLFireability-2024-09: CTL false CTL model checker
[lola][.] CO4-PT-04-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] CO4-PT-04-CTLFireability-2024-12: CONJ false state space /EXEG
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] CO4-PT-04-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-04-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-04-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] CO4-PT-04-CTLFireability-2024-06: DISJ 0 1 0 0 3 0 0 0
[lola][.] CO4-PT-04-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-04-CTLFireability-2024-13: SP ECTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-04-CTLFireability-2024-14: DISJ 0 1 0 0 5 0 0 1
[lola][.] CO4-PT-04-CTLFireability-2024-15: F 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 3/358 2/2000 CO4-PT-04-CTLFireability-2024-05 464861 m, 92972 m/sec, 3749011 t fired, .
[lola][.]
[lola][.] Time elapsed: 15 secs. Pages in use: 5
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I] FINISHED task # 16 (type EXCL) for CO4-PT-04-CTLFireability-2024-05
[lola][I] result : false
[lola][I] markings : 1070786
[lola][I] fired transitions : 9485049
[lola][I] time used : 7
[lola][I] memory pages used : 5
[lola][I] LAUNCH task # 13 (type EXCL) for 12 CO4-PT-04-CTLFireability-2024-04
[lola][I] time limit : 397 sec
[lola][I] memory limit: 2000 pages
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] CO4-PT-04-CTLFireability-2024-03: CTL true CTL model checker
[lola][.] CO4-PT-04-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] CO4-PT-04-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] CO4-PT-04-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] CO4-PT-04-CTLFireability-2024-09: CTL false CTL model checker
[lola][.] CO4-PT-04-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] CO4-PT-04-CTLFireability-2024-12: CONJ false state space /EXEG
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] CO4-PT-04-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-04-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-04-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[lola][.] CO4-PT-04-CTLFireability-2024-06: DISJ 0 1 0 0 3 0 0 0
[lola][.] CO4-PT-04-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-04-CTLFireability-2024-13: SP ECTL 0 1 0 0 1 0 0 0
[lola][.] CO4-PT-04-CTLFireability-2024-14: DISJ 0 1 0 0 5 0 0 1
[lola][.] CO4-PT-04-CTLFireability-2024-15: F 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 13 CTL EXCL 1/397 2/2000 CO4-PT-04-CTLFireability-2024-04 243054 m, 48610 m/sec, 1439488 t fired, .
[lola][.]
[lola][.] Time elapsed: 20 secs. Pages in use: 5
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I] FINISHED task # 13 (type EXCL) for CO4-PT-04-CTLFireability-2024-04
[lola][I] result : false
[lola][I] markings : 1103234
[lola][I] fired transitions : 7558723
[lola][I] time used : 6
[lola][I] memory pages used : 5
[lola][I] LAUNCH task # 4 (type EXCL) for 3 CO4-PT-04-CTLFireability-2024-01
[lola][I] time limit : 446 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 4 (type EXCL) for CO4-PT-04-CTLFireability-2024-01
[lola][I] result : true
[lola][I] markings : 1
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 1 (type EXCL) for 0 CO4-PT-04-CTLFireability-2024-00
[lola][I] time limit : 510 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 1 (type EXCL) for CO4-PT-04-CTLFireability-2024-00
[lola][I] result : false
[lola][I] markings : 1332
[lola][I] fired transitions : 4785
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 80 (type EXCL) for 65 CO4-PT-04-CTLFireability-2024-15
[lola][I] time limit : 595 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 80 (type EXCL) for CO4-PT-04-CTLFireability-2024-15
[lola][I] result : true
[lola][I] markings : 7
[lola][I] fired transitions : 7
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 73 (type EXCL) for 54 CO4-PT-04-CTLFireability-2024-14
[lola][I] time limit : 715 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 73 (type EXCL) for CO4-PT-04-CTLFireability-2024-14
[lola][I] result : false
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 71 (type EXCL) for 51 CO4-PT-04-CTLFireability-2024-13
[lola][I] time limit : 893 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 71 (type EXCL) for CO4-PT-04-CTLFireability-2024-13
[lola][I] result : false
[lola][I] markings : 14
[lola][I] fired transitions : 14
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 35 (type EXCL) for 34 CO4-PT-04-CTLFireability-2024-10
[lola][I] time limit : 1191 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 35 (type EXCL) for CO4-PT-04-CTLFireability-2024-10
[lola][I] result : true
[lola][I] markings : 7
[lola][I] fired transitions : 14
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 21 (type EXCL) for 18 CO4-PT-04-CTLFireability-2024-06
[lola][I] time limit : 1787 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 21 (type EXCL) for CO4-PT-04-CTLFireability-2024-06
[lola][I] result : false
[lola][I] markings : 12
[lola][I] fired transitions : 42
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 7 (type EXCL) for 6 CO4-PT-04-CTLFireability-2024-02
[lola][I] time limit : 3575 sec
[lola][I] memory limit: 2000 pages
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] CO4-PT-04-CTLFireability-2024-00: CTL false CTL model checker
[lola][.] CO4-PT-04-CTLFireability-2024-01: CTL true CTL model checker
[lola][.] CO4-PT-04-CTLFireability-2024-03: CTL true CTL model checker
[lola][.] CO4-PT-04-CTLFireability-2024-04: CTL false CTL model checker
[lola][.] CO4-PT-04-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] CO4-PT-04-CTLFireability-2024-06: DISJ false DISJ
[lola][.] CO4-PT-04-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] CO4-PT-04-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] CO4-PT-04-CTLFireability-2024-09: CTL false CTL model checker
[lola][.] CO4-PT-04-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] CO4-PT-04-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] CO4-PT-04-CTLFireability-2024-12: CONJ false state space /EXEG
[lola][.] CO4-PT-04-CTLFireability-2024-13: SP ECTL true LTL model checker
[lola][.] CO4-PT-04-CTLFireability-2024-14: DISJ true state space /EU
[lola][.] CO4-PT-04-CTLFireability-2024-15: F false state space / EG
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] CO4-PT-04-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 7 CTL EXCL 0/3575 1/2000 CO4-PT-04-CTLFireability-2024-02 21534 m, 4306 m/sec, 125732 t fired, .
[lola][.]
[lola][.] Time elapsed: 25 secs. Pages in use: 5
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I] FINISHED task # 7 (type EXCL) for CO4-PT-04-CTLFireability-2024-02
[lola][I] result : false
[lola][I] markings : 592418
[lola][I] fired transitions : 4764237
[lola][I] time used : 3
[lola][I] memory pages used : 3
[lola][I] Portfolio finished: no open formulas

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="CO4-PT-04"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is CO4-PT-04, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r551-tall-171734899200026"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/CO4-PT-04.tgz
mv CO4-PT-04 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;