About the Execution of LoLA for CO4-PT-02
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
884.027 | 33039.00 | 113915.00 | 65.70 | TFFTTTFFTFFFTFTT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r551-tall-171734899100015.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is CO4-PT-02, examination is ReachabilityFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r551-tall-171734899100015
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 548K
-rw-r--r-- 1 mcc users 6.7K Jun 2 17:16 CTLCardinality.txt
-rw-r--r-- 1 mcc users 76K Jun 2 17:16 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.3K Jun 2 17:16 CTLFireability.txt
-rw-r--r-- 1 mcc users 63K Jun 2 17:16 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.3K Jun 2 17:12 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Jun 2 17:12 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Jun 2 17:12 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Jun 2 17:12 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 Jun 2 16:33 NewModel
-rw-r--r-- 1 mcc users 11K Jun 2 17:16 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 116K Jun 2 17:16 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Jun 2 17:16 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 102K Jun 2 17:16 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.5K Jun 2 17:12 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.5K Jun 2 17:12 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Jun 2 16:33 equiv_col
-rw-r--r-- 1 mcc users 3 Jun 2 16:33 instance
-rw-r--r-- 1 mcc users 6 Jun 2 16:33 iscolored
-rw-r--r-- 1 mcc users 74K Jun 2 16:33 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME CO4-PT-02-ReachabilityFireability-2024-00
FORMULA_NAME CO4-PT-02-ReachabilityFireability-2024-01
FORMULA_NAME CO4-PT-02-ReachabilityFireability-2024-02
FORMULA_NAME CO4-PT-02-ReachabilityFireability-2024-03
FORMULA_NAME CO4-PT-02-ReachabilityFireability-2024-04
FORMULA_NAME CO4-PT-02-ReachabilityFireability-2024-05
FORMULA_NAME CO4-PT-02-ReachabilityFireability-2024-06
FORMULA_NAME CO4-PT-02-ReachabilityFireability-2024-07
FORMULA_NAME CO4-PT-02-ReachabilityFireability-2024-08
FORMULA_NAME CO4-PT-02-ReachabilityFireability-2024-09
FORMULA_NAME CO4-PT-02-ReachabilityFireability-2024-10
FORMULA_NAME CO4-PT-02-ReachabilityFireability-2024-11
FORMULA_NAME CO4-PT-02-ReachabilityFireability-2024-12
FORMULA_NAME CO4-PT-02-ReachabilityFireability-2024-13
FORMULA_NAME CO4-PT-02-ReachabilityFireability-2024-14
FORMULA_NAME CO4-PT-02-ReachabilityFireability-2024-15
=== Now, execution of the tool begins
BK_START 1717397159189
FORMULA CO4-PT-02-ReachabilityFireability-2024-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-02-ReachabilityFireability-2024-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-02-ReachabilityFireability-2024-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-02-ReachabilityFireability-2024-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-02-ReachabilityFireability-2024-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-02-ReachabilityFireability-2024-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-02-ReachabilityFireability-2024-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-02-ReachabilityFireability-2024-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-02-ReachabilityFireability-2024-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-02-ReachabilityFireability-2024-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-02-ReachabilityFireability-2024-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-02-ReachabilityFireability-2024-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-02-ReachabilityFireability-2024-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-02-ReachabilityFireability-2024-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-02-ReachabilityFireability-2024-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CO4-PT-02-ReachabilityFireability-2024-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[[35mlola[0m] [1mFINAL RESULTS[0m
[[35mlola[0m] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m] [1m[32mCO4-PT-02-ReachabilityFireability-2024-00: EF true state space[0m
[[35mlola[0m] [1m[31mCO4-PT-02-ReachabilityFireability-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m] [1m[31mCO4-PT-02-ReachabilityFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m] [1m[32mCO4-PT-02-ReachabilityFireability-2024-03: EF true state space[0m
[[35mlola[0m] [1m[32mCO4-PT-02-ReachabilityFireability-2024-04: EF true state space[0m
[[35mlola[0m] [1m[32mCO4-PT-02-ReachabilityFireability-2024-05: AG true state space[0m
[[35mlola[0m] [1m[31mCO4-PT-02-ReachabilityFireability-2024-06: EF false state equation[0m
[[35mlola[0m] [1m[31mCO4-PT-02-ReachabilityFireability-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m] [1m[32mCO4-PT-02-ReachabilityFireability-2024-08: EF true state space[0m
[[35mlola[0m] [1m[31mCO4-PT-02-ReachabilityFireability-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m] [1m[31mCO4-PT-02-ReachabilityFireability-2024-10: EF false state space[0m
[[35mlola[0m] [1m[31mCO4-PT-02-ReachabilityFireability-2024-11: EF false state space[0m
[[35mlola[0m] [1m[32mCO4-PT-02-ReachabilityFireability-2024-12: AG true state space[0m
[[35mlola[0m] [1m[31mCO4-PT-02-ReachabilityFireability-2024-13: AG false state space[0m
[[35mlola[0m] [1m[32mCO4-PT-02-ReachabilityFireability-2024-14: EF true state space[0m
[[35mlola[0m] [1m[32mCO4-PT-02-ReachabilityFireability-2024-15: EF true state space[0m
[[35mlola[0m]
[[35mlola[0m] Time elapsed: 33 secs. Pages in use: 6
BK_STOP 1717397192228
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mReachabilityFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 50 (type EXCL) for 0 CO4-PT-02-ReachabilityFireability-2024-00
[[35mlola[0m][I] time limit : 138 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 48 (type FNDP) for 0 CO4-PT-02-ReachabilityFireability-2024-00
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 49 (type EQUN) for 0 CO4-PT-02-ReachabilityFireability-2024-00
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 50 (type EXCL) for CO4-PT-02-ReachabilityFireability-2024-00
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 7
[[35mlola[0m][I] fired transitions : 6
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 48 (type FNDP) for CO4-PT-02-ReachabilityFireability-2024-00 (obsolete)
[[35mlola[0m][W] CANCELED task # 49 (type EQUN) for CO4-PT-02-ReachabilityFireability-2024-00 (obsolete)
[[35mlola[0m][I] LAUNCH task # 4 (type CNST) for 3 CO4-PT-02-ReachabilityFireability-2024-01
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 4 (type CNST) for CO4-PT-02-ReachabilityFireability-2024-01
[[35mlola[0m][I] result : false
[[35mlola[0m][I] FINISHED task # 48 (type FNDP) for CO4-PT-02-ReachabilityFireability-2024-00
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] LAUNCH task # 28 (type CNST) for 27 CO4-PT-02-ReachabilityFireability-2024-09
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 28 (type CNST) for CO4-PT-02-ReachabilityFireability-2024-09
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 53 (type EXCL) for 12 CO4-PT-02-ReachabilityFireability-2024-04
[[35mlola[0m][I] time limit : 257 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 51 (type FNDP) for 12 CO4-PT-02-ReachabilityFireability-2024-04
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 52 (type EQUN) for 12 CO4-PT-02-ReachabilityFireability-2024-04
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 22 (type CNST) for 21 CO4-PT-02-ReachabilityFireability-2024-07
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 22 (type CNST) for CO4-PT-02-ReachabilityFireability-2024-07
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 56 (type FNDP) for 30 CO4-PT-02-ReachabilityFireability-2024-10
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 53 (type EXCL) for CO4-PT-02-ReachabilityFireability-2024-04
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 9
[[35mlola[0m][I] fired transitions : 8
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 51 (type FNDP) for CO4-PT-02-ReachabilityFireability-2024-04 (obsolete)
[[35mlola[0m][W] CANCELED task # 52 (type EQUN) for CO4-PT-02-ReachabilityFireability-2024-04 (obsolete)
[[35mlola[0m][I] LAUNCH task # 74 (type EXCL) for 45 CO4-PT-02-ReachabilityFireability-2024-15
[[35mlola[0m][I] time limit : 299 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 69 (type FNDP) for 18 CO4-PT-02-ReachabilityFireability-2024-06
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 70 (type EQUN) for 18 CO4-PT-02-ReachabilityFireability-2024-06
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 52 (type EQUN) for CO4-PT-02-ReachabilityFireability-2024-04
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 7 (type CNST) for 6 CO4-PT-02-ReachabilityFireability-2024-02
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 7 (type CNST) for CO4-PT-02-ReachabilityFireability-2024-02
[[35mlola[0m][I] result : false
[[35mlola[0m][I] FINISHED task # 74 (type EXCL) for CO4-PT-02-ReachabilityFireability-2024-15
[[35mlola[0m][I] result : true
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 64 (type EXCL) for 42 CO4-PT-02-ReachabilityFireability-2024-14
[[35mlola[0m][I] time limit : 399 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 51 (type FNDP) for CO4-PT-02-ReachabilityFireability-2024-04
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] FINISHED task # 64 (type EXCL) for CO4-PT-02-ReachabilityFireability-2024-14
[[35mlola[0m][I] result : true
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 82 (type EXCL) for 39 CO4-PT-02-ReachabilityFireability-2024-13
[[35mlola[0m][I] time limit : 449 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 82 (type EXCL) for CO4-PT-02-ReachabilityFireability-2024-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 81
[[35mlola[0m][I] fired transitions : 109
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 68 (type EXCL) for 33 CO4-PT-02-ReachabilityFireability-2024-11
[[35mlola[0m][I] time limit : 514 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 49 (type EQUN) for CO4-PT-02-ReachabilityFireability-2024-00
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] FINISHED task # 68 (type EXCL) for CO4-PT-02-ReachabilityFireability-2024-11
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 619313
[[35mlola[0m][I] fired transitions : 2971900
[[35mlola[0m][I] time used : 4
[[35mlola[0m][I] memory pages used : 3
[[35mlola[0m][I] LAUNCH task # 65 (type EXCL) for 9 CO4-PT-02-ReachabilityFireability-2024-03
[[35mlola[0m][I] time limit : 599 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 65 (type EXCL) for CO4-PT-02-ReachabilityFireability-2024-03
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 44
[[35mlola[0m][I] fired transitions : 48
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 59 (type EXCL) for 24 CO4-PT-02-ReachabilityFireability-2024-08
[[35mlola[0m][I] time limit : 719 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 59 (type EXCL) for CO4-PT-02-ReachabilityFireability-2024-08
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 6
[[35mlola[0m][I] fired transitions : 5
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 86 (type EXCL) for 36 CO4-PT-02-ReachabilityFireability-2024-12
[[35mlola[0m][I] time limit : 898 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mCO4-PT-02-ReachabilityFireability-2024-00: EF true state space[0m
[[35mlola[0m][.] [1m[31mCO4-PT-02-ReachabilityFireability-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mCO4-PT-02-ReachabilityFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mCO4-PT-02-ReachabilityFireability-2024-03: EF true state space[0m
[[35mlola[0m][.] [1m[32mCO4-PT-02-ReachabilityFireability-2024-04: EF true state space[0m
[[35mlola[0m][.] [1m[31mCO4-PT-02-ReachabilityFireability-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mCO4-PT-02-ReachabilityFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[31mCO4-PT-02-ReachabilityFireability-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mCO4-PT-02-ReachabilityFireability-2024-11: EF false state space[0m
[[35mlola[0m][.] [1m[31mCO4-PT-02-ReachabilityFireability-2024-13: AG false state space[0m
[[35mlola[0m][.] [1m[32mCO4-PT-02-ReachabilityFireability-2024-14: EF true state space[0m
[[35mlola[0m][.] [1m[32mCO4-PT-02-ReachabilityFireability-2024-15: EF true state space[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-02-ReachabilityFireability-2024-05: AG 0 3 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-02-ReachabilityFireability-2024-06: EF 0 1 2 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-02-ReachabilityFireability-2024-10: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-02-ReachabilityFireability-2024-12: AG 0 2 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 56 EF FNDP 5/1195 0/5 CO4-PT-02-ReachabilityFireability-2024-10 31 attempts, .
[[35mlola[0m][.] 69 EF FNDP 5/1195 0/5 CO4-PT-02-ReachabilityFireability-2024-06 23 attempts, .
[[35mlola[0m][.] 70 EF STEQ 5/1795 0/5 CO4-PT-02-ReachabilityFireability-2024-06 sara not yet started (preprocessing).
[[35mlola[0m][.] 86 EF EXCL 1/898 1/2000 CO4-PT-02-ReachabilityFireability-2024-12 225201 m, 45040 m/sec, 997552 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 6 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 4 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mCO4-PT-02-ReachabilityFireability-2024-00: EF true state space[0m
[[35mlola[0m][.] [1m[31mCO4-PT-02-ReachabilityFireability-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mCO4-PT-02-ReachabilityFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mCO4-PT-02-ReachabilityFireability-2024-03: EF true state space[0m
[[35mlola[0m][.] [1m[32mCO4-PT-02-ReachabilityFireability-2024-04: EF true state space[0m
[[35mlola[0m][.] [1m[31mCO4-PT-02-ReachabilityFireability-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mCO4-PT-02-ReachabilityFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[31mCO4-PT-02-ReachabilityFireability-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mCO4-PT-02-ReachabilityFireability-2024-11: EF false state space[0m
[[35mlola[0m][.] [1m[31mCO4-PT-02-ReachabilityFireability-2024-13: AG false state space[0m
[[35mlola[0m][.] [1m[32mCO4-PT-02-ReachabilityFireability-2024-14: EF true state space[0m
[[35mlola[0m][.] [1m[32mCO4-PT-02-ReachabilityFireability-2024-15: EF true state space[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-02-ReachabilityFireability-2024-05: AG 0 3 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-02-ReachabilityFireability-2024-06: EF 0 1 2 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-02-ReachabilityFireability-2024-10: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-02-ReachabilityFireability-2024-12: AG 0 2 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 56 EF FNDP 10/1194 0/5 CO4-PT-02-ReachabilityFireability-2024-10 56 attempts, .
[[35mlola[0m][.] 69 EF FNDP 10/1194 0/5 CO4-PT-02-ReachabilityFireability-2024-06 51 attempts, .
[[35mlola[0m][.] 70 EF STEQ 10/1794 0/5 CO4-PT-02-ReachabilityFireability-2024-06 sara not yet started (preprocessing).
[[35mlola[0m][.] 86 EF EXCL 6/898 4/2000 CO4-PT-02-ReachabilityFireability-2024-12 921035 m, 139166 m/sec, 5050521 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 11 secs. Pages in use: 4
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[[35mlola[0m][.] [1m[32mCO4-PT-02-ReachabilityFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[31mCO4-PT-02-ReachabilityFireability-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mCO4-PT-02-ReachabilityFireability-2024-11: EF false state space[0m
[[35mlola[0m][.] [1m[31mCO4-PT-02-ReachabilityFireability-2024-13: AG false state space[0m
[[35mlola[0m][.] [1m[32mCO4-PT-02-ReachabilityFireability-2024-14: EF true state space[0m
[[35mlola[0m][.] [1m[32mCO4-PT-02-ReachabilityFireability-2024-15: EF true state space[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-02-ReachabilityFireability-2024-05: AG 0 3 0 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-02-ReachabilityFireability-2024-06: EF 0 1 2 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-02-ReachabilityFireability-2024-10: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-02-ReachabilityFireability-2024-12: AG 0 2 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 56 EF FNDP 15/1189 0/5 CO4-PT-02-ReachabilityFireability-2024-10 59 attempts, .
[[35mlola[0m][.] 69 EF FNDP 15/1189 0/5 CO4-PT-02-ReachabilityFireability-2024-06 105 attempts, .
[[35mlola[0m][.] 70 EF STEQ 15/1789 0/5 CO4-PT-02-ReachabilityFireability-2024-06 sara not yet started (preprocessing).
[[35mlola[0m][.] 86 EF EXCL 11/898 6/2000 CO4-PT-02-ReachabilityFireability-2024-12 1625996 m, 140992 m/sec, 8899551 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 16 secs. Pages in use: 6
[[35mlola[0m][.] # running tasks: 4 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 86 (type EXCL) for CO4-PT-02-ReachabilityFireability-2024-12
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1677163
[[35mlola[0m][I] fired transitions : 9485827
[[35mlola[0m][I] time used : 12
[[35mlola[0m][I] memory pages used : 6
[[35mlola[0m][I] LAUNCH task # 61 (type EXCL) for 30 CO4-PT-02-ReachabilityFireability-2024-10
[[35mlola[0m][I] time limit : 1194 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 70 (type EQUN) for CO4-PT-02-ReachabilityFireability-2024-06
[[35mlola[0m][I] result : false
[[35mlola[0m][W] CANCELED task # 69 (type FNDP) for CO4-PT-02-ReachabilityFireability-2024-06 (obsolete)
[[35mlola[0m][I] LAUNCH task # 76 (type FNDP) for 15 CO4-PT-02-ReachabilityFireability-2024-05
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 77 (type EQUN) for 15 CO4-PT-02-ReachabilityFireability-2024-05
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 69 (type FNDP) for CO4-PT-02-ReachabilityFireability-2024-06
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] tried executions : 112
[[35mlola[0m][I] time used : 16
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mCO4-PT-02-ReachabilityFireability-2024-00: EF true state space[0m
[[35mlola[0m][.] [1m[31mCO4-PT-02-ReachabilityFireability-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mCO4-PT-02-ReachabilityFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mCO4-PT-02-ReachabilityFireability-2024-03: EF true state space[0m
[[35mlola[0m][.] [1m[32mCO4-PT-02-ReachabilityFireability-2024-04: EF true state space[0m
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[[35mlola[0m][.] [1m[31mCO4-PT-02-ReachabilityFireability-2024-13: AG false state space[0m
[[35mlola[0m][.] [1m[32mCO4-PT-02-ReachabilityFireability-2024-14: EF true state space[0m
[[35mlola[0m][.] [1m[32mCO4-PT-02-ReachabilityFireability-2024-15: EF true state space[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-02-ReachabilityFireability-2024-05: AG 0 1 2 0 1 0 0 0
[[35mlola[0m][.] CO4-PT-02-ReachabilityFireability-2024-10: EF 0 1 2 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 56 EF FNDP 20/3583 0/5 CO4-PT-02-ReachabilityFireability-2024-10 101 attempts, .
[[35mlola[0m][.] 61 EF EXCL 4/1791 3/2000 CO4-PT-02-ReachabilityFireability-2024-10 808189 m, 161637 m/sec, 3475458 t fired, .
[[35mlola[0m][.] 76 EF FNDP 4/3583 0/5 CO4-PT-02-ReachabilityFireability-2024-05 5 attempts, .
[[35mlola[0m][.] 77 EF STEQ 4/1791 0/5 CO4-PT-02-ReachabilityFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 21 secs. Pages in use: 6
[[35mlola[0m][.] # running tasks: 4 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 61 (type EXCL) for CO4-PT-02-ReachabilityFireability-2024-10
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 900650
[[35mlola[0m][I] fired transitions : 3920263
[[35mlola[0m][I] time used : 5
[[35mlola[0m][I] memory pages used : 4
[[35mlola[0m][W] CANCELED task # 56 (type FNDP) for CO4-PT-02-ReachabilityFireability-2024-10 (obsolete)
[[35mlola[0m][I] LAUNCH task # 78 (type EXCL) for 15 CO4-PT-02-ReachabilityFireability-2024-05
[[35mlola[0m][I] time limit : 3578 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 56 (type FNDP) for CO4-PT-02-ReachabilityFireability-2024-10
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] tried executions : 102
[[35mlola[0m][I] time used : 21
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mCO4-PT-02-ReachabilityFireability-2024-00: EF true state space[0m
[[35mlola[0m][.] [1m[31mCO4-PT-02-ReachabilityFireability-2024-01: INITIAL false preprocessing[0m
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[[35mlola[0m][.] [1m[31mCO4-PT-02-ReachabilityFireability-2024-06: EF false state equation[0m
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[[35mlola[0m][.] [1m[31mCO4-PT-02-ReachabilityFireability-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mCO4-PT-02-ReachabilityFireability-2024-10: EF false state space[0m
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[[35mlola[0m][.] [1m[31mCO4-PT-02-ReachabilityFireability-2024-13: AG false state space[0m
[[35mlola[0m][.] [1m[32mCO4-PT-02-ReachabilityFireability-2024-14: EF true state space[0m
[[35mlola[0m][.] [1m[32mCO4-PT-02-ReachabilityFireability-2024-15: EF true state space[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-02-ReachabilityFireability-2024-05: AG 0 0 3 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 76 EF FNDP 9/3583 0/5 CO4-PT-02-ReachabilityFireability-2024-05 9 attempts, .
[[35mlola[0m][.] 77 EF STEQ 9/3583 0/5 CO4-PT-02-ReachabilityFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.] 78 EF EXCL 4/3578 3/2000 CO4-PT-02-ReachabilityFireability-2024-05 639491 m, 127898 m/sec, 3420093 t fired, .
[[35mlola[0m][.]
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[[35mlola[0m][I] FINISHED task # 77 (type EQUN) for CO4-PT-02-ReachabilityFireability-2024-05
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mCO4-PT-02-ReachabilityFireability-2024-00: EF true state space[0m
[[35mlola[0m][.] [1m[31mCO4-PT-02-ReachabilityFireability-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mCO4-PT-02-ReachabilityFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mCO4-PT-02-ReachabilityFireability-2024-03: EF true state space[0m
[[35mlola[0m][.] [1m[32mCO4-PT-02-ReachabilityFireability-2024-04: EF true state space[0m
[[35mlola[0m][.] [1m[31mCO4-PT-02-ReachabilityFireability-2024-06: EF false state equation[0m
[[35mlola[0m][.] [1m[31mCO4-PT-02-ReachabilityFireability-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mCO4-PT-02-ReachabilityFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[31mCO4-PT-02-ReachabilityFireability-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mCO4-PT-02-ReachabilityFireability-2024-10: EF false state space[0m
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[[35mlola[0m][.] [1m[31mCO4-PT-02-ReachabilityFireability-2024-13: AG false state space[0m
[[35mlola[0m][.] [1m[32mCO4-PT-02-ReachabilityFireability-2024-14: EF true state space[0m
[[35mlola[0m][.] [1m[32mCO4-PT-02-ReachabilityFireability-2024-15: EF true state space[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CO4-PT-02-ReachabilityFireability-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 76 EF FNDP 14/3583 0/5 CO4-PT-02-ReachabilityFireability-2024-05 20 attempts, .
[[35mlola[0m][.] 78 EF EXCL 9/3578 5/2000 CO4-PT-02-ReachabilityFireability-2024-05 1323464 m, 136794 m/sec, 7281244 t fired, .
[[35mlola[0m][.]
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[[35mlola[0m][I] FINISHED task # 78 (type EXCL) for CO4-PT-02-ReachabilityFireability-2024-05
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1547281
[[35mlola[0m][I] fired transitions : 8535647
[[35mlola[0m][I] time used : 11
[[35mlola[0m][I] memory pages used : 6
[[35mlola[0m][W] CANCELED task # 76 (type FNDP) for CO4-PT-02-ReachabilityFireability-2024-05 (obsolete)
[[35mlola[0m][I] Portfolio finished: no open formulas
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="CO4-PT-02"
export BK_EXAMINATION="ReachabilityFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is CO4-PT-02, examination is ReachabilityFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r551-tall-171734899100015"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/CO4-PT-02.tgz
mv CO4-PT-02 execution
cd execution
if [ "ReachabilityFireability" = "ReachabilityDeadlock" ] || [ "ReachabilityFireability" = "UpperBounds" ] || [ "ReachabilityFireability" = "QuasiLiveness" ] || [ "ReachabilityFireability" = "StableMarking" ] || [ "ReachabilityFireability" = "Liveness" ] || [ "ReachabilityFireability" = "OneSafe" ] || [ "ReachabilityFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "ReachabilityFireability" = "ReachabilityDeadlock" ] || [ "ReachabilityFireability" = "QuasiLiveness" ] || [ "ReachabilityFireability" = "StableMarking" ] || [ "ReachabilityFireability" = "Liveness" ] || [ "ReachabilityFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME ReachabilityFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;