fond
Model Checking Contest 2024
14th edition, Geneva, Switzerland, June 25, 2024
Execution of r544-smll-171701111000194
Last Updated
July 7, 2024

About the Execution of LTSMin+red for UtilityControlRoom-PT-Z2T4N06

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
336.172 16115.00 33112.00 311.50 [undef] Cannot compute

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r544-smll-171701111000194.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool ltsminxred
Input is UtilityControlRoom-PT-Z2T4N06, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r544-smll-171701111000194
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.4M
-rw-r--r-- 1 mcc users 33K Apr 13 05:28 CTLCardinality.txt
-rw-r--r-- 1 mcc users 187K Apr 13 05:28 CTLCardinality.xml
-rw-r--r-- 1 mcc users 24K Apr 13 05:25 CTLFireability.txt
-rw-r--r-- 1 mcc users 120K Apr 13 05:25 CTLFireability.xml
-rw-r--r-- 1 mcc users 7.8K Apr 23 08:04 LTLCardinality.txt
-rw-r--r-- 1 mcc users 37K Apr 23 08:04 LTLCardinality.xml
-rw-r--r-- 1 mcc users 12K Apr 23 08:04 LTLFireability.txt
-rw-r--r-- 1 mcc users 42K Apr 23 08:04 LTLFireability.xml
-rw-r--r-- 1 mcc users 60K Apr 13 05:37 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 341K Apr 13 05:37 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 67K Apr 13 05:35 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 300K Apr 13 05:35 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.8K Apr 23 08:04 UpperBounds.txt
-rw-r--r-- 1 mcc users 5.9K Apr 23 08:04 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 8 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 70K May 18 16:43 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME UtilityControlRoom-PT-Z2T4N06-CTLFireability-2024-00
FORMULA_NAME UtilityControlRoom-PT-Z2T4N06-CTLFireability-2024-01
FORMULA_NAME UtilityControlRoom-PT-Z2T4N06-CTLFireability-2024-02
FORMULA_NAME UtilityControlRoom-PT-Z2T4N06-CTLFireability-2024-03
FORMULA_NAME UtilityControlRoom-PT-Z2T4N06-CTLFireability-2024-04
FORMULA_NAME UtilityControlRoom-PT-Z2T4N06-CTLFireability-2024-05
FORMULA_NAME UtilityControlRoom-PT-Z2T4N06-CTLFireability-2024-06
FORMULA_NAME UtilityControlRoom-PT-Z2T4N06-CTLFireability-2024-07
FORMULA_NAME UtilityControlRoom-PT-Z2T4N06-CTLFireability-2024-08
FORMULA_NAME UtilityControlRoom-PT-Z2T4N06-CTLFireability-2024-09
FORMULA_NAME UtilityControlRoom-PT-Z2T4N06-CTLFireability-2024-10
FORMULA_NAME UtilityControlRoom-PT-Z2T4N06-CTLFireability-2024-11
FORMULA_NAME UtilityControlRoom-PT-Z2T4N06-CTLFireability-2024-12
FORMULA_NAME UtilityControlRoom-PT-Z2T4N06-CTLFireability-2024-13
FORMULA_NAME UtilityControlRoom-PT-Z2T4N06-CTLFireability-2024-14
FORMULA_NAME UtilityControlRoom-PT-Z2T4N06-CTLFireability-2024-15

=== Now, execution of the tool begins

BK_START 1717273575983

Invoking MCC driver with
BK_TOOL=ltsminxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=UtilityControlRoom-PT-Z2T4N06
BK_MEMORY_CONFINEMENT=16384
Applying reductions before tool ltsmin
Invoking reducer
Running Version 202405141337
[2024-06-01 20:26:18] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2024-06-01 20:26:18] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2024-06-01 20:26:18] [INFO ] Load time of PNML (sax parser for PT used): 128 ms
[2024-06-01 20:26:18] [INFO ] Transformed 106 places.
[2024-06-01 20:26:18] [INFO ] Transformed 162 transitions.
[2024-06-01 20:26:18] [INFO ] Parsed PT model containing 106 places and 162 transitions and 510 arcs in 320 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 34 ms.
[2024-06-01 20:26:18] [INFO ] Reduced 6 identical enabling conditions.
[2024-06-01 20:26:18] [INFO ] Reduced 6 identical enabling conditions.
[2024-06-01 20:26:18] [INFO ] Reduced 6 identical enabling conditions.
[2024-06-01 20:26:18] [INFO ] Reduced 6 identical enabling conditions.
[2024-06-01 20:26:18] [INFO ] Reduced 6 identical enabling conditions.
[2024-06-01 20:26:18] [INFO ] Reduced 6 identical enabling conditions.
[2024-06-01 20:26:18] [INFO ] Reduced 6 identical enabling conditions.
[2024-06-01 20:26:18] [INFO ] Reduced 6 identical enabling conditions.
[2024-06-01 20:26:18] [INFO ] Reduced 6 identical enabling conditions.
Ensure Unique test removed 24 transitions
Reduce redundant transitions removed 24 transitions.
Support contains 106 out of 106 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 106/106 places, 138/138 transitions.
Applied a total of 0 rules in 123 ms. Remains 106 /106 variables (removed 0) and now considering 138/138 (removed 0) transitions.
// Phase 1: matrix 138 rows 106 cols
[2024-06-01 20:26:18] [INFO ] Computed 15 invariants in 14 ms
[2024-06-01 20:26:19] [INFO ] Implicit Places using invariants in 349 ms returned []
[2024-06-01 20:26:19] [INFO ] Invariant cache hit.
[2024-06-01 20:26:19] [INFO ] Implicit Places using invariants and state equation in 189 ms returned []
Implicit Place search using SMT with State Equation took 590 ms to find 0 implicit places.
Running 132 sub problems to find dead transitions.
[2024-06-01 20:26:19] [INFO ] Invariant cache hit.
At refinement iteration 0 (INCLUDED_ONLY) 0/100 variables, 2/2 constraints. Problems are: Problem set: 0 solved, 132 unsolved
At refinement iteration 1 (INCLUDED_ONLY) 0/100 variables, 0/2 constraints. Problems are: Problem set: 0 solved, 132 unsolved
At refinement iteration 2 (OVERLAPS) 6/106 variables, 13/15 constraints. Problems are: Problem set: 0 solved, 132 unsolved
At refinement iteration 3 (INCLUDED_ONLY) 0/106 variables, 0/15 constraints. Problems are: Problem set: 0 solved, 132 unsolved
At refinement iteration 4 (OVERLAPS) 138/244 variables, 106/121 constraints. Problems are: Problem set: 0 solved, 132 unsolved
At refinement iteration 5 (INCLUDED_ONLY) 0/244 variables, 0/121 constraints. Problems are: Problem set: 0 solved, 132 unsolved
At refinement iteration 6 (OVERLAPS) 0/244 variables, 0/121 constraints. Problems are: Problem set: 0 solved, 132 unsolved
No progress, stopping.
After SMT solving in domain Real declared 244/244 variables, and 121 constraints, problems are : Problem set: 0 solved, 132 unsolved in 4346 ms.
Refiners :[Positive P Invariants (semi-flows): 15/15 constraints, State Equation: 106/106 constraints, PredecessorRefiner: 132/132 constraints, Known Traps: 0/0 constraints]
Escalating to Integer solving :Problem set: 0 solved, 132 unsolved
At refinement iteration 0 (INCLUDED_ONLY) 0/100 variables, 2/2 constraints. Problems are: Problem set: 0 solved, 132 unsolved
At refinement iteration 1 (INCLUDED_ONLY) 0/100 variables, 0/2 constraints. Problems are: Problem set: 0 solved, 132 unsolved
At refinement iteration 2 (OVERLAPS) 6/106 variables, 13/15 constraints. Problems are: Problem set: 0 solved, 132 unsolved
At refinement iteration 3 (INCLUDED_ONLY) 0/106 variables, 0/15 constraints. Problems are: Problem set: 0 solved, 132 unsolved
At refinement iteration 4 (OVERLAPS) 138/244 variables, 106/121 constraints. Problems are: Problem set: 0 solved, 132 unsolved
At refinement iteration 5 (INCLUDED_ONLY) 0/244 variables, 132/253 constraints. Problems are: Problem set: 0 solved, 132 unsolved
At refinement iteration 6 (INCLUDED_ONLY) 0/244 variables, 0/253 constraints. Problems are: Problem set: 0 solved, 132 unsolved
At refinement iteration 7 (OVERLAPS) 0/244 variables, 0/253 constraints. Problems are: Problem set: 0 solved, 132 unsolved
No progress, stopping.
After SMT solving in domain Int declared 244/244 variables, and 253 constraints, problems are : Problem set: 0 solved, 132 unsolved in 4599 ms.
Refiners :[Positive P Invariants (semi-flows): 15/15 constraints, State Equation: 106/106 constraints, PredecessorRefiner: 132/132 constraints, Known Traps: 0/0 constraints]
After SMT, in 9171ms problems are : Problem set: 0 solved, 132 unsolved
Search for dead transitions found 0 dead transitions in 9194ms
Finished structural reductions in LTL mode , in 1 iterations and 9943 ms. Remains : 106/106 places, 138/138 transitions.
Support contains 106 out of 106 places after structural reductions.
[2024-06-01 20:26:29] [INFO ] Flatten gal took : 59 ms
[2024-06-01 20:26:29] [INFO ] Flatten gal took : 51 ms
[2024-06-01 20:26:29] [INFO ] Input system was already deterministic with 138 transitions.
Reduction of identical properties reduced properties to check from 52 to 51
RANDOM walk for 40000 steps (8 resets) in 2063 ms. (19 steps per ms) remains 2/51 properties
BEST_FIRST walk for 40004 steps (8 resets) in 454 ms. (87 steps per ms) remains 2/2 properties
BEST_FIRST walk for 40003 steps (8 resets) in 434 ms. (91 steps per ms) remains 2/2 properties
[2024-06-01 20:26:30] [INFO ] Invariant cache hit.
At refinement iteration 0 (INCLUDED_ONLY) 0/6 variables, 0/0 constraints. Problems are: Problem set: 0 solved, 2 unsolved
Problem AtomicPropp32 is UNSAT
Problem AtomicPropp33 is UNSAT
After SMT solving in domain Real declared 84/244 variables, and 6 constraints, problems are : Problem set: 2 solved, 0 unsolved in 58 ms.
Refiners :[Positive P Invariants (semi-flows): 6/15 constraints, State Equation: 0/106 constraints, PredecessorRefiner: 2/2 constraints, Known Traps: 0/0 constraints]
After SMT, in 71ms problems are : Problem set: 2 solved, 0 unsolved
Skipping Parikh replay, no witness traces provided.
Successfully simplified 2 atomic propositions for a total of 16 simplifications.
[2024-06-01 20:26:30] [INFO ] Flatten gal took : 21 ms
[2024-06-01 20:26:30] [INFO ] Flatten gal took : 24 ms
[2024-06-01 20:26:30] [INFO ] Input system was already deterministic with 138 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 106/106 places, 138/138 transitions.
Discarding 12 places :
Symmetric choice reduction at 0 with 12 rule applications. Total rules 12 place count 94 transition count 126
Iterating global reduction 0 with 12 rules applied. Total rules applied 24 place count 94 transition count 126
Applied a total of 24 rules in 13 ms. Remains 94 /106 variables (removed 12) and now considering 126/138 (removed 12) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 13 ms. Remains : 94/106 places, 126/138 transitions.
[2024-06-01 20:26:30] [INFO ] Flatten gal took : 12 ms
[2024-06-01 20:26:30] [INFO ] Flatten gal took : 12 ms
[2024-06-01 20:26:30] [INFO ] Input system was already deterministic with 126 transitions.
Starting structural reductions in LTL mode, iteration 0 : 106/106 places, 138/138 transitions.
Discarding 12 places :
Symmetric choice reduction at 0 with 12 rule applications. Total rules 12 place count 94 transition count 126
Iterating global reduction 0 with 12 rules applied. Total rules applied 24 place count 94 transition count 126
Applied a total of 24 rules in 4 ms. Remains 94 /106 variables (removed 12) and now considering 126/138 (removed 12) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 94/106 places, 126/138 transitions.
[2024-06-01 20:26:30] [INFO ] Flatten gal took : 13 ms
[2024-06-01 20:26:30] [INFO ] Flatten gal took : 15 ms
[2024-06-01 20:26:30] [INFO ] Input system was already deterministic with 126 transitions.
Starting structural reductions in LTL mode, iteration 0 : 106/106 places, 138/138 transitions.
Discarding 12 places :
Symmetric choice reduction at 0 with 12 rule applications. Total rules 12 place count 94 transition count 126
Iterating global reduction 0 with 12 rules applied. Total rules applied 24 place count 94 transition count 126
Applied a total of 24 rules in 6 ms. Remains 94 /106 variables (removed 12) and now considering 126/138 (removed 12) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6 ms. Remains : 94/106 places, 126/138 transitions.
[2024-06-01 20:26:30] [INFO ] Flatten gal took : 10 ms
[2024-06-01 20:26:30] [INFO ] Flatten gal took : 10 ms
[2024-06-01 20:26:30] [INFO ] Input system was already deterministic with 126 transitions.
Starting structural reductions in LTL mode, iteration 0 : 106/106 places, 138/138 transitions.
Discarding 12 places :
Symmetric choice reduction at 0 with 12 rule applications. Total rules 12 place count 94 transition count 126
Iterating global reduction 0 with 12 rules applied. Total rules applied 24 place count 94 transition count 126
Applied a total of 24 rules in 7 ms. Remains 94 /106 variables (removed 12) and now considering 126/138 (removed 12) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 7 ms. Remains : 94/106 places, 126/138 transitions.
[2024-06-01 20:26:30] [INFO ] Flatten gal took : 10 ms
[2024-06-01 20:26:30] [INFO ] Flatten gal took : 10 ms
[2024-06-01 20:26:30] [INFO ] Input system was already deterministic with 126 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 106/106 places, 138/138 transitions.
Drop transitions (Trivial Post-Agglo cleanup.) removed 24 transitions
Trivial Post-agglo rules discarded 24 transitions
Performed 24 trivial Post agglomeration. Transition count delta: 24
Iterating post reduction 0 with 24 rules applied. Total rules applied 24 place count 106 transition count 114
Reduce places removed 24 places and 0 transitions.
Ensure Unique test removed 12 transitions
Reduce isomorphic transitions removed 12 transitions.
Iterating post reduction 1 with 36 rules applied. Total rules applied 60 place count 82 transition count 102
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 61 place count 81 transition count 90
Iterating global reduction 2 with 1 rules applied. Total rules applied 62 place count 81 transition count 90
Performed 6 Post agglomeration using F-continuation condition.Transition count delta: 6
Deduced a syphon composed of 6 places in 0 ms
Ensure Unique test removed 1 places
Reduce places removed 7 places and 0 transitions.
Iterating global reduction 2 with 13 rules applied. Total rules applied 75 place count 74 transition count 84
Applied a total of 75 rules in 34 ms. Remains 74 /106 variables (removed 32) and now considering 84/138 (removed 54) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 34 ms. Remains : 74/106 places, 84/138 transitions.
[2024-06-01 20:26:30] [INFO ] Flatten gal took : 6 ms
[2024-06-01 20:26:30] [INFO ] Flatten gal took : 10 ms
[2024-06-01 20:26:30] [INFO ] Input system was already deterministic with 84 transitions.
Starting structural reductions in LTL mode, iteration 0 : 106/106 places, 138/138 transitions.
Applied a total of 0 rules in 2 ms. Remains 106 /106 variables (removed 0) and now considering 138/138 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 106/106 places, 138/138 transitions.
[2024-06-01 20:26:30] [INFO ] Flatten gal took : 10 ms
[2024-06-01 20:26:30] [INFO ] Flatten gal took : 10 ms
[2024-06-01 20:26:30] [INFO ] Input system was already deterministic with 138 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 106/106 places, 138/138 transitions.
Applied a total of 0 rules in 6 ms. Remains 106 /106 variables (removed 0) and now considering 138/138 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 6 ms. Remains : 106/106 places, 138/138 transitions.
[2024-06-01 20:26:31] [INFO ] Flatten gal took : 9 ms
[2024-06-01 20:26:31] [INFO ] Flatten gal took : 9 ms
[2024-06-01 20:26:31] [INFO ] Input system was already deterministic with 138 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 106/106 places, 138/138 transitions.
Performed 24 Post agglomeration using F-continuation condition.Transition count delta: 24
Iterating post reduction 0 with 24 rules applied. Total rules applied 24 place count 106 transition count 114
Reduce places removed 24 places and 0 transitions.
Ensure Unique test removed 12 transitions
Reduce isomorphic transitions removed 12 transitions.
Iterating post reduction 1 with 36 rules applied. Total rules applied 60 place count 82 transition count 102
Applied a total of 60 rules in 9 ms. Remains 82 /106 variables (removed 24) and now considering 102/138 (removed 36) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 10 ms. Remains : 82/106 places, 102/138 transitions.
[2024-06-01 20:26:31] [INFO ] Flatten gal took : 6 ms
[2024-06-01 20:26:31] [INFO ] Flatten gal took : 7 ms
[2024-06-01 20:26:31] [INFO ] Input system was already deterministic with 102 transitions.
Starting structural reductions in LTL mode, iteration 0 : 106/106 places, 138/138 transitions.
Discarding 11 places :
Symmetric choice reduction at 0 with 11 rule applications. Total rules 11 place count 95 transition count 127
Iterating global reduction 0 with 11 rules applied. Total rules applied 22 place count 95 transition count 127
Applied a total of 22 rules in 7 ms. Remains 95 /106 variables (removed 11) and now considering 127/138 (removed 11) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 7 ms. Remains : 95/106 places, 127/138 transitions.
[2024-06-01 20:26:31] [INFO ] Flatten gal took : 8 ms
[2024-06-01 20:26:31] [INFO ] Flatten gal took : 8 ms
[2024-06-01 20:26:31] [INFO ] Input system was already deterministic with 127 transitions.
Starting structural reductions in LTL mode, iteration 0 : 106/106 places, 138/138 transitions.
Discarding 12 places :
Symmetric choice reduction at 0 with 12 rule applications. Total rules 12 place count 94 transition count 126
Iterating global reduction 0 with 12 rules applied. Total rules applied 24 place count 94 transition count 126
Applied a total of 24 rules in 8 ms. Remains 94 /106 variables (removed 12) and now considering 126/138 (removed 12) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 8 ms. Remains : 94/106 places, 126/138 transitions.
[2024-06-01 20:26:31] [INFO ] Flatten gal took : 8 ms
[2024-06-01 20:26:31] [INFO ] Flatten gal took : 8 ms
[2024-06-01 20:26:31] [INFO ] Input system was already deterministic with 126 transitions.
Starting structural reductions in LTL mode, iteration 0 : 106/106 places, 138/138 transitions.
Discarding 12 places :
Symmetric choice reduction at 0 with 12 rule applications. Total rules 12 place count 94 transition count 126
Iterating global reduction 0 with 12 rules applied. Total rules applied 24 place count 94 transition count 126
Applied a total of 24 rules in 7 ms. Remains 94 /106 variables (removed 12) and now considering 126/138 (removed 12) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 7 ms. Remains : 94/106 places, 126/138 transitions.
[2024-06-01 20:26:31] [INFO ] Flatten gal took : 7 ms
[2024-06-01 20:26:31] [INFO ] Flatten gal took : 6 ms
[2024-06-01 20:26:31] [INFO ] Input system was already deterministic with 126 transitions.
Starting structural reductions in LTL mode, iteration 0 : 106/106 places, 138/138 transitions.
Discarding 8 places :
Symmetric choice reduction at 0 with 8 rule applications. Total rules 8 place count 98 transition count 130
Iterating global reduction 0 with 8 rules applied. Total rules applied 16 place count 98 transition count 130
Applied a total of 16 rules in 5 ms. Remains 98 /106 variables (removed 8) and now considering 130/138 (removed 8) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 98/106 places, 130/138 transitions.
[2024-06-01 20:26:31] [INFO ] Flatten gal took : 7 ms
[2024-06-01 20:26:31] [INFO ] Flatten gal took : 7 ms
[2024-06-01 20:26:31] [INFO ] Input system was already deterministic with 130 transitions.
Starting structural reductions in LTL mode, iteration 0 : 106/106 places, 138/138 transitions.
Discarding 10 places :
Symmetric choice reduction at 0 with 10 rule applications. Total rules 10 place count 96 transition count 128
Iterating global reduction 0 with 10 rules applied. Total rules applied 20 place count 96 transition count 128
Applied a total of 20 rules in 3 ms. Remains 96 /106 variables (removed 10) and now considering 128/138 (removed 10) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 96/106 places, 128/138 transitions.
[2024-06-01 20:26:31] [INFO ] Flatten gal took : 6 ms
[2024-06-01 20:26:31] [INFO ] Flatten gal took : 7 ms
[2024-06-01 20:26:31] [INFO ] Input system was already deterministic with 128 transitions.
Starting structural reductions in LTL mode, iteration 0 : 106/106 places, 138/138 transitions.
Discarding 12 places :
Symmetric choice reduction at 0 with 12 rule applications. Total rules 12 place count 94 transition count 126
Iterating global reduction 0 with 12 rules applied. Total rules applied 24 place count 94 transition count 126
Applied a total of 24 rules in 4 ms. Remains 94 /106 variables (removed 12) and now considering 126/138 (removed 12) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 94/106 places, 126/138 transitions.
[2024-06-01 20:26:31] [INFO ] Flatten gal took : 6 ms
[2024-06-01 20:26:31] [INFO ] Flatten gal took : 6 ms
[2024-06-01 20:26:31] [INFO ] Input system was already deterministic with 126 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 106/106 places, 138/138 transitions.
Performed 21 Post agglomeration using F-continuation condition.Transition count delta: 21
Iterating post reduction 0 with 21 rules applied. Total rules applied 21 place count 106 transition count 117
Reduce places removed 21 places and 0 transitions.
Ensure Unique test removed 10 transitions
Reduce isomorphic transitions removed 10 transitions.
Iterating post reduction 1 with 31 rules applied. Total rules applied 52 place count 85 transition count 107
Performed 10 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 10 Pre rules applied. Total rules applied 52 place count 85 transition count 97
Deduced a syphon composed of 10 places in 0 ms
Reduce places removed 10 places and 0 transitions.
Iterating global reduction 2 with 20 rules applied. Total rules applied 72 place count 75 transition count 97
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 73 place count 74 transition count 96
Iterating global reduction 2 with 1 rules applied. Total rules applied 74 place count 74 transition count 96
Performed 6 Post agglomeration using F-continuation condition.Transition count delta: 6
Deduced a syphon composed of 6 places in 0 ms
Reduce places removed 6 places and 0 transitions.
Iterating global reduction 2 with 12 rules applied. Total rules applied 86 place count 68 transition count 90
Applied a total of 86 rules in 18 ms. Remains 68 /106 variables (removed 38) and now considering 90/138 (removed 48) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 18 ms. Remains : 68/106 places, 90/138 transitions.
[2024-06-01 20:26:31] [INFO ] Flatten gal took : 5 ms
[2024-06-01 20:26:31] [INFO ] Flatten gal took : 5 ms
[2024-06-01 20:26:31] [INFO ] Input system was already deterministic with 90 transitions.
Starting structural reductions in LTL mode, iteration 0 : 106/106 places, 138/138 transitions.
Discarding 10 places :
Symmetric choice reduction at 0 with 10 rule applications. Total rules 10 place count 96 transition count 128
Iterating global reduction 0 with 10 rules applied. Total rules applied 20 place count 96 transition count 128
Applied a total of 20 rules in 3 ms. Remains 96 /106 variables (removed 10) and now considering 128/138 (removed 10) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 96/106 places, 128/138 transitions.
[2024-06-01 20:26:31] [INFO ] Flatten gal took : 6 ms
[2024-06-01 20:26:31] [INFO ] Flatten gal took : 6 ms
[2024-06-01 20:26:31] [INFO ] Input system was already deterministic with 128 transitions.
[2024-06-01 20:26:31] [INFO ] Flatten gal took : 14 ms
[2024-06-01 20:26:31] [INFO ] Flatten gal took : 14 ms
[2024-06-01 20:26:31] [INFO ] Export to MCC of 16 properties in file /home/mcc/execution/CTLFireability.sr.xml took 20 ms.
[2024-06-01 20:26:31] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 106 places, 138 transitions and 414 arcs took 6 ms.
Total runtime 13407 ms.
There are residual formulas that ITS could not solve within timeout
Usage: pnml2lts-sym [-gvqh] [--order=]
[--mu-opt] [--saturation=]
[--sat-granularity=] [--save-sat-levels]
[--guidance=] [-d|--deadlock]
[--action=] [-i|--invariant=STRING] [-n|--no-exit]
[--trace=] [--type=]
[--mu=.mu] [--ctl-star=.ctl]
[--ctl=.ctl] [--ltl=.ltl] [--dot=STRING]
[--save-levels=STRING] [--pg-solve] [--attr=]
[--saturating-attractor] [--write-strategy=.spg]
[--check-strategy] [--interactive-play] [--player]
[--pg-write=.spg] [--no-matrix] [--noack=<1|2>]
[--edge-label=] [--labels] [-m|--matrix]
[--mucalc=.mcf|] [-c|--cache]
[--allow-undefined-edges] [--allow-undefined-values]
[-p|--por= (default: heur)]
[--weak=[valmari] (default: uses stronger left-commutativity)]
[--leap] [-r|--regroup=<(T,)+>] [--sloan-w1=] [--sloan-w2=]
[--cw-max-cols=] [--cw-max-rows=] [--col-ins=<(C.C',)+>]
[--mh-timeout=] [--row-perm=<(R,)+>] [--col-perm=<(C,)+>]
[--graph-metrics] [--regroup-exit] [--regroup-time]
[-g|--pins-guards] [--vset=] [--ldd32-step=]
[--ldd32-cache=] [--ldd-step=] [--ldd-cache=]
[--cache-ratio=] [--max-increase=]
[--min-free-nodes=] [--fdd-bits=]
[--fdd-reorder=]
[--vset-cache-diff=] [--no-soundness-check] [--precise]
[--next-union] [--peak-nodes] [--maxsum=]
[--block-size=] [--cluster-size=] [-v] [-q]
[--debug=] [--stats] [--where] [--when]
[--timeout=INT] [--version] [-h|--help] [--usage]
[OPTIONS] []
Could not compute solution for formula : UtilityControlRoom-PT-Z2T4N06-CTLFireability-2024-00
Could not compute solution for formula : UtilityControlRoom-PT-Z2T4N06-CTLFireability-2024-01
Could not compute solution for formula : UtilityControlRoom-PT-Z2T4N06-CTLFireability-2024-02
Could not compute solution for formula : UtilityControlRoom-PT-Z2T4N06-CTLFireability-2024-03
Could not compute solution for formula : UtilityControlRoom-PT-Z2T4N06-CTLFireability-2024-04
Could not compute solution for formula : UtilityControlRoom-PT-Z2T4N06-CTLFireability-2024-05
Could not compute solution for formula : UtilityControlRoom-PT-Z2T4N06-CTLFireability-2024-06
Could not compute solution for formula : UtilityControlRoom-PT-Z2T4N06-CTLFireability-2024-07
Could not compute solution for formula : UtilityControlRoom-PT-Z2T4N06-CTLFireability-2024-08
Could not compute solution for formula : UtilityControlRoom-PT-Z2T4N06-CTLFireability-2024-09
Could not compute solution for formula : UtilityControlRoom-PT-Z2T4N06-CTLFireability-2024-10
Could not compute solution for formula : UtilityControlRoom-PT-Z2T4N06-CTLFireability-2024-11
Could not compute solution for formula : UtilityControlRoom-PT-Z2T4N06-CTLFireability-2024-12
Could not compute solution for formula : UtilityControlRoom-PT-Z2T4N06-CTLFireability-2024-13
Could not compute solution for formula : UtilityControlRoom-PT-Z2T4N06-CTLFireability-2024-14
Could not compute solution for formula : UtilityControlRoom-PT-Z2T4N06-CTLFireability-2024-15

BK_STOP 1717273592098

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202405141337.jar
+ VERSION=202405141337
+ echo 'Running Version 202405141337'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
mcc2024
ctl formula name UtilityControlRoom-PT-Z2T4N06-CTLFireability-2024-00
ctl formula formula --ctl=/tmp/516/ctl_0_
ctl formula name UtilityControlRoom-PT-Z2T4N06-CTLFireability-2024-01
ctl formula formula --ctl=/tmp/516/ctl_1_
ctl formula name UtilityControlRoom-PT-Z2T4N06-CTLFireability-2024-02
ctl formula formula --ctl=/tmp/516/ctl_2_
ctl formula name UtilityControlRoom-PT-Z2T4N06-CTLFireability-2024-03
ctl formula formula --ctl=/tmp/516/ctl_3_
ctl formula name UtilityControlRoom-PT-Z2T4N06-CTLFireability-2024-04
ctl formula formula --ctl=/tmp/516/ctl_4_
ctl formula name UtilityControlRoom-PT-Z2T4N06-CTLFireability-2024-05
ctl formula formula --ctl=/tmp/516/ctl_5_
ctl formula name UtilityControlRoom-PT-Z2T4N06-CTLFireability-2024-06
ctl formula formula --ctl=/tmp/516/ctl_6_
ctl formula name UtilityControlRoom-PT-Z2T4N06-CTLFireability-2024-07
ctl formula formula --ctl=/tmp/516/ctl_7_
ctl formula name UtilityControlRoom-PT-Z2T4N06-CTLFireability-2024-08
ctl formula formula --ctl=/tmp/516/ctl_8_
ctl formula name UtilityControlRoom-PT-Z2T4N06-CTLFireability-2024-09
ctl formula formula --ctl=/tmp/516/ctl_9_
ctl formula name UtilityControlRoom-PT-Z2T4N06-CTLFireability-2024-10
ctl formula formula --ctl=/tmp/516/ctl_10_
ctl formula name UtilityControlRoom-PT-Z2T4N06-CTLFireability-2024-11
ctl formula formula --ctl=/tmp/516/ctl_11_
ctl formula name UtilityControlRoom-PT-Z2T4N06-CTLFireability-2024-12
ctl formula formula --ctl=/tmp/516/ctl_12_
ctl formula name UtilityControlRoom-PT-Z2T4N06-CTLFireability-2024-13
ctl formula formula --ctl=/tmp/516/ctl_13_
ctl formula name UtilityControlRoom-PT-Z2T4N06-CTLFireability-2024-14
ctl formula formula --ctl=/tmp/516/ctl_14_
ctl formula name UtilityControlRoom-PT-Z2T4N06-CTLFireability-2024-15
ctl formula formula --ctl=/tmp/516/ctl_15_
pnml2lts-sym, ** error **: unknown vector set implementation lddmc

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="UtilityControlRoom-PT-Z2T4N06"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="ltsminxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool ltsminxred"
echo " Input is UtilityControlRoom-PT-Z2T4N06, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r544-smll-171701111000194"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/UtilityControlRoom-PT-Z2T4N06.tgz
mv UtilityControlRoom-PT-Z2T4N06 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;