About the Execution of LTSMin+red for SmallOperatingSystem-PT-MT8192DC4096
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 381.415 | 136699.00 | 305527.00 | 402.40 | TT????????????FF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r532-smll-171683811300329.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool ltsminxred
Input is SmallOperatingSystem-PT-MT8192DC4096, examination is CTLCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r532-smll-171683811300329
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 492K
-rw-r--r-- 1 mcc users 11K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 95K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.0K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 46K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:43 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.7K May 18 16:43 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.5K Apr 23 07:57 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Apr 23 07:57 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.8K Apr 23 07:57 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Apr 23 07:57 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Apr 12 14:13 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 115K Apr 12 14:13 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.6K Apr 12 14:12 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 69K Apr 12 14:12 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.1K Apr 23 07:57 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.1K Apr 23 07:57 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 13 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 8.1K May 18 16:43 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-2024-00
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-2024-01
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-2024-02
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-2024-03
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-2024-04
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-2024-05
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-2024-06
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-2024-07
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-2024-08
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-2024-09
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-2024-10
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-2024-11
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-2023-12
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-2023-13
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-2023-14
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-2023-15
=== Now, execution of the tool begins
BK_START 1717256125182
Invoking MCC driver with
BK_TOOL=ltsminxred
BK_EXAMINATION=CTLCardinality
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=SmallOperatingSystem-PT-MT8192DC4096
BK_MEMORY_CONFINEMENT=16384
Applying reductions before tool ltsmin
Invoking reducer
Running Version 202405141337
[2024-06-01 15:35:27] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLCardinality, -timeout, 360, -rebuildPNML]
[2024-06-01 15:35:27] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2024-06-01 15:35:28] [INFO ] Load time of PNML (sax parser for PT used): 64 ms
[2024-06-01 15:35:28] [INFO ] Transformed 9 places.
[2024-06-01 15:35:28] [INFO ] Transformed 8 transitions.
[2024-06-01 15:35:28] [INFO ] Parsed PT model containing 9 places and 8 transitions and 27 arcs in 311 ms.
Parsed 16 properties from file /home/mcc/execution/CTLCardinality.xml in 58 ms.
Support contains 9 out of 9 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 22 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
// Phase 1: matrix 8 rows 9 cols
[2024-06-01 15:35:28] [INFO ] Computed 4 invariants in 11 ms
[2024-06-01 15:35:28] [INFO ] Implicit Places using invariants in 245 ms returned []
[2024-06-01 15:35:28] [INFO ] Invariant cache hit.
[2024-06-01 15:35:28] [INFO ] Implicit Places using invariants and state equation in 75 ms returned []
Implicit Place search using SMT with State Equation took 382 ms to find 0 implicit places.
Running 7 sub problems to find dead transitions.
[2024-06-01 15:35:28] [INFO ] Invariant cache hit.
At refinement iteration 0 (INCLUDED_ONLY) 0/8 variables, 3/3 constraints. Problems are: Problem set: 0 solved, 7 unsolved
At refinement iteration 1 (INCLUDED_ONLY) 0/8 variables, 0/3 constraints. Problems are: Problem set: 0 solved, 7 unsolved
At refinement iteration 2 (OVERLAPS) 1/9 variables, 1/4 constraints. Problems are: Problem set: 0 solved, 7 unsolved
At refinement iteration 3 (INCLUDED_ONLY) 0/9 variables, 0/4 constraints. Problems are: Problem set: 0 solved, 7 unsolved
At refinement iteration 4 (OVERLAPS) 8/17 variables, 9/13 constraints. Problems are: Problem set: 0 solved, 7 unsolved
At refinement iteration 5 (INCLUDED_ONLY) 0/17 variables, 0/13 constraints. Problems are: Problem set: 0 solved, 7 unsolved
At refinement iteration 6 (OVERLAPS) 0/17 variables, 0/13 constraints. Problems are: Problem set: 0 solved, 7 unsolved
No progress, stopping.
After SMT solving in domain Real declared 17/17 variables, and 13 constraints, problems are : Problem set: 0 solved, 7 unsolved in 234 ms.
Refiners :[Positive P Invariants (semi-flows): 4/4 constraints, State Equation: 9/9 constraints, PredecessorRefiner: 7/7 constraints, Known Traps: 0/0 constraints]
Escalating to Integer solving :Problem set: 0 solved, 7 unsolved
At refinement iteration 0 (INCLUDED_ONLY) 0/8 variables, 3/3 constraints. Problems are: Problem set: 0 solved, 7 unsolved
At refinement iteration 1 (INCLUDED_ONLY) 0/8 variables, 0/3 constraints. Problems are: Problem set: 0 solved, 7 unsolved
At refinement iteration 2 (OVERLAPS) 1/9 variables, 1/4 constraints. Problems are: Problem set: 0 solved, 7 unsolved
At refinement iteration 3 (INCLUDED_ONLY) 0/9 variables, 0/4 constraints. Problems are: Problem set: 0 solved, 7 unsolved
At refinement iteration 4 (OVERLAPS) 8/17 variables, 9/13 constraints. Problems are: Problem set: 0 solved, 7 unsolved
At refinement iteration 5 (INCLUDED_ONLY) 0/17 variables, 7/20 constraints. Problems are: Problem set: 0 solved, 7 unsolved
At refinement iteration 6 (INCLUDED_ONLY) 0/17 variables, 0/20 constraints. Problems are: Problem set: 0 solved, 7 unsolved
At refinement iteration 7 (OVERLAPS) 0/17 variables, 0/20 constraints. Problems are: Problem set: 0 solved, 7 unsolved
No progress, stopping.
After SMT solving in domain Int declared 17/17 variables, and 20 constraints, problems are : Problem set: 0 solved, 7 unsolved in 176 ms.
Refiners :[Positive P Invariants (semi-flows): 4/4 constraints, State Equation: 9/9 constraints, PredecessorRefiner: 7/7 constraints, Known Traps: 0/0 constraints]
After SMT, in 452ms problems are : Problem set: 0 solved, 7 unsolved
Search for dead transitions found 0 dead transitions in 469ms
Finished structural reductions in LTL mode , in 1 iterations and 936 ms. Remains : 9/9 places, 8/8 transitions.
Support contains 9 out of 9 places after structural reductions.
[2024-06-01 15:35:29] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
[2024-06-01 15:35:29] [INFO ] Flatten gal took : 29 ms
FORMULA SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-2024-01 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2024-06-01 15:35:29] [INFO ] Flatten gal took : 10 ms
[2024-06-01 15:35:29] [INFO ] Input system was already deterministic with 8 transitions.
RANDOM walk for 49172 steps (8 resets) in 236 ms. (207 steps per ms) remains 75/98 properties
BEST_FIRST walk for 4004 steps (8 resets) in 210 ms. (18 steps per ms) remains 71/75 properties
BEST_FIRST walk for 4003 steps (8 resets) in 255 ms. (15 steps per ms) remains 71/71 properties
BEST_FIRST walk for 4004 steps (8 resets) in 293 ms. (13 steps per ms) remains 71/71 properties
BEST_FIRST walk for 4004 steps (8 resets) in 132 ms. (30 steps per ms) remains 71/71 properties
BEST_FIRST walk for 4004 steps (8 resets) in 247 ms. (16 steps per ms) remains 71/71 properties
BEST_FIRST walk for 4004 steps (8 resets) in 149 ms. (26 steps per ms) remains 71/71 properties
BEST_FIRST walk for 4002 steps (8 resets) in 127 ms. (31 steps per ms) remains 70/71 properties
BEST_FIRST walk for 4004 steps (8 resets) in 140 ms. (28 steps per ms) remains 70/70 properties
BEST_FIRST walk for 4004 steps (8 resets) in 103 ms. (38 steps per ms) remains 70/70 properties
BEST_FIRST walk for 4004 steps (8 resets) in 109 ms. (36 steps per ms) remains 70/70 properties
BEST_FIRST walk for 4004 steps (8 resets) in 142 ms. (28 steps per ms) remains 70/70 properties
BEST_FIRST walk for 4004 steps (8 resets) in 136 ms. (29 steps per ms) remains 70/70 properties
BEST_FIRST walk for 4004 steps (8 resets) in 116 ms. (34 steps per ms) remains 70/70 properties
BEST_FIRST walk for 4004 steps (8 resets) in 64 ms. (61 steps per ms) remains 70/70 properties
BEST_FIRST walk for 4003 steps (8 resets) in 15 ms. (250 steps per ms) remains 70/70 properties
BEST_FIRST walk for 4004 steps (8 resets) in 21 ms. (182 steps per ms) remains 70/70 properties
BEST_FIRST walk for 4004 steps (8 resets) in 26 ms. (148 steps per ms) remains 70/70 properties
BEST_FIRST walk for 4004 steps (8 resets) in 18 ms. (210 steps per ms) remains 70/70 properties
BEST_FIRST walk for 4004 steps (8 resets) in 30 ms. (129 steps per ms) remains 70/70 properties
BEST_FIRST walk for 4004 steps (8 resets) in 38 ms. (102 steps per ms) remains 70/70 properties
BEST_FIRST walk for 4003 steps (8 resets) in 30 ms. (129 steps per ms) remains 70/70 properties
BEST_FIRST walk for 4004 steps (8 resets) in 29 ms. (133 steps per ms) remains 70/70 properties
BEST_FIRST walk for 4004 steps (8 resets) in 16 ms. (235 steps per ms) remains 70/70 properties
BEST_FIRST walk for 4003 steps (8 resets) in 17 ms. (222 steps per ms) remains 70/70 properties
BEST_FIRST walk for 4003 steps (8 resets) in 28 ms. (138 steps per ms) remains 70/70 properties
BEST_FIRST walk for 4004 steps (8 resets) in 18 ms. (210 steps per ms) remains 70/70 properties
BEST_FIRST walk for 4003 steps (8 resets) in 18 ms. (210 steps per ms) remains 70/70 properties
BEST_FIRST walk for 4002 steps (8 resets) in 33 ms. (117 steps per ms) remains 70/70 properties
BEST_FIRST walk for 4004 steps (8 resets) in 19 ms. (200 steps per ms) remains 70/70 properties
BEST_FIRST walk for 4003 steps (8 resets) in 30 ms. (129 steps per ms) remains 70/70 properties
BEST_FIRST walk for 4003 steps (8 resets) in 49 ms. (80 steps per ms) remains 70/70 properties
BEST_FIRST walk for 4002 steps (8 resets) in 24 ms. (160 steps per ms) remains 70/70 properties
BEST_FIRST walk for 4004 steps (8 resets) in 32 ms. (121 steps per ms) remains 70/70 properties
BEST_FIRST walk for 4003 steps (8 resets) in 24 ms. (160 steps per ms) remains 70/70 properties
BEST_FIRST walk for 4004 steps (8 resets) in 36 ms. (108 steps per ms) remains 70/70 properties
BEST_FIRST walk for 4004 steps (8 resets) in 25 ms. (154 steps per ms) remains 70/70 properties
BEST_FIRST walk for 4004 steps (8 resets) in 33 ms. (117 steps per ms) remains 70/70 properties
BEST_FIRST walk for 4002 steps (8 resets) in 41 ms. (95 steps per ms) remains 70/70 properties
BEST_FIRST walk for 4002 steps (8 resets) in 23 ms. (166 steps per ms) remains 70/70 properties
BEST_FIRST walk for 4004 steps (8 resets) in 36 ms. (108 steps per ms) remains 70/70 properties
BEST_FIRST walk for 4002 steps (8 resets) in 23 ms. (166 steps per ms) remains 70/70 properties
BEST_FIRST walk for 4004 steps (8 resets) in 24 ms. (160 steps per ms) remains 70/70 properties
BEST_FIRST walk for 4002 steps (8 resets) in 41 ms. (95 steps per ms) remains 70/70 properties
BEST_FIRST walk for 4004 steps (8 resets) in 51 ms. (77 steps per ms) remains 70/70 properties
BEST_FIRST walk for 4004 steps (8 resets) in 24 ms. (160 steps per ms) remains 70/70 properties
BEST_FIRST walk for 4004 steps (8 resets) in 28 ms. (138 steps per ms) remains 70/70 properties
BEST_FIRST walk for 4003 steps (8 resets) in 30 ms. (129 steps per ms) remains 70/70 properties
BEST_FIRST walk for 4004 steps (8 resets) in 17 ms. (222 steps per ms) remains 70/70 properties
BEST_FIRST walk for 4004 steps (8 resets) in 19 ms. (200 steps per ms) remains 70/70 properties
BEST_FIRST walk for 4004 steps (8 resets) in 19 ms. (200 steps per ms) remains 70/70 properties
BEST_FIRST walk for 4003 steps (8 resets) in 19 ms. (200 steps per ms) remains 70/70 properties
BEST_FIRST walk for 4002 steps (8 resets) in 21 ms. (181 steps per ms) remains 70/70 properties
BEST_FIRST walk for 4002 steps (8 resets) in 19 ms. (200 steps per ms) remains 70/70 properties
BEST_FIRST walk for 4003 steps (8 resets) in 16 ms. (235 steps per ms) remains 70/70 properties
BEST_FIRST walk for 4004 steps (8 resets) in 25 ms. (154 steps per ms) remains 70/70 properties
BEST_FIRST walk for 4004 steps (8 resets) in 22 ms. (174 steps per ms) remains 70/70 properties
[2024-06-01 15:35:31] [INFO ] Invariant cache hit.
Problem AtomicPropp3 is UNSAT
Problem AtomicPropp7 is UNSAT
Problem AtomicPropp10 is UNSAT
Problem AtomicPropp11 is UNSAT
Problem AtomicPropp21 is UNSAT
Problem AtomicPropp23 is UNSAT
Problem AtomicPropp25 is UNSAT
Problem AtomicPropp36 is UNSAT
Problem AtomicPropp52 is UNSAT
Problem AtomicPropp55 is UNSAT
Problem AtomicPropp57 is UNSAT
Problem AtomicPropp58 is UNSAT
Problem AtomicPropp62 is UNSAT
Problem AtomicPropp65 is UNSAT
Problem AtomicPropp66 is UNSAT
Problem AtomicPropp72 is UNSAT
Problem AtomicPropp88 is UNSAT
Problem AtomicPropp91 is UNSAT
Problem AtomicPropp92 is UNSAT
At refinement iteration 0 (INCLUDED_ONLY) 0/9 variables, 4/4 constraints. Problems are: Problem set: 19 solved, 51 unsolved
At refinement iteration 1 (INCLUDED_ONLY) 0/9 variables, 0/4 constraints. Problems are: Problem set: 19 solved, 51 unsolved
At refinement iteration 2 (OVERLAPS) 8/17 variables, 9/13 constraints. Problems are: Problem set: 19 solved, 51 unsolved
At refinement iteration 3 (INCLUDED_ONLY) 0/17 variables, 0/13 constraints. Problems are: Problem set: 19 solved, 51 unsolved
At refinement iteration 4 (OVERLAPS) 0/17 variables, 0/13 constraints. Problems are: Problem set: 19 solved, 51 unsolved
No progress, stopping.
After SMT solving in domain Real declared 17/17 variables, and 13 constraints, problems are : Problem set: 19 solved, 51 unsolved in 700 ms.
Refiners :[Positive P Invariants (semi-flows): 4/4 constraints, State Equation: 9/9 constraints, PredecessorRefiner: 70/70 constraints, Known Traps: 0/0 constraints]
Escalating to Integer solving :Problem set: 19 solved, 51 unsolved
At refinement iteration 0 (INCLUDED_ONLY) 0/9 variables, 4/4 constraints. Problems are: Problem set: 19 solved, 51 unsolved
At refinement iteration 1 (INCLUDED_ONLY) 0/9 variables, 0/4 constraints. Problems are: Problem set: 19 solved, 51 unsolved
At refinement iteration 2 (OVERLAPS) 8/17 variables, 9/13 constraints. Problems are: Problem set: 19 solved, 51 unsolved
At refinement iteration 3 (INCLUDED_ONLY) 0/17 variables, 51/64 constraints. Problems are: Problem set: 19 solved, 51 unsolved
At refinement iteration 4 (INCLUDED_ONLY) 0/17 variables, 0/64 constraints. Problems are: Problem set: 19 solved, 51 unsolved
At refinement iteration 5 (OVERLAPS) 0/17 variables, 0/64 constraints. Problems are: Problem set: 19 solved, 51 unsolved
No progress, stopping.
After SMT solving in domain Int declared 17/17 variables, and 64 constraints, problems are : Problem set: 19 solved, 51 unsolved in 1138 ms.
Refiners :[Positive P Invariants (semi-flows): 4/4 constraints, State Equation: 9/9 constraints, PredecessorRefiner: 51/70 constraints, Known Traps: 0/0 constraints]
After SMT, in 1884ms problems are : Problem set: 19 solved, 51 unsolved
Parikh walk visited 35 properties in 32138 ms.
Support contains 9 out of 9 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 5 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 5 ms. Remains : 9/9 places, 8/8 transitions.
RANDOM walk for 49172 steps (8 resets) in 81 ms. (599 steps per ms) remains 16/16 properties
BEST_FIRST walk for 4004 steps (8 resets) in 16 ms. (235 steps per ms) remains 16/16 properties
BEST_FIRST walk for 4003 steps (8 resets) in 13 ms. (285 steps per ms) remains 16/16 properties
BEST_FIRST walk for 4003 steps (8 resets) in 14 ms. (266 steps per ms) remains 16/16 properties
BEST_FIRST walk for 4001 steps (8 resets) in 18 ms. (210 steps per ms) remains 16/16 properties
BEST_FIRST walk for 4003 steps (8 resets) in 9 ms. (400 steps per ms) remains 16/16 properties
BEST_FIRST walk for 4004 steps (8 resets) in 12 ms. (308 steps per ms) remains 16/16 properties
BEST_FIRST walk for 4004 steps (8 resets) in 9 ms. (400 steps per ms) remains 16/16 properties
BEST_FIRST walk for 4003 steps (8 resets) in 13 ms. (285 steps per ms) remains 16/16 properties
BEST_FIRST walk for 4003 steps (8 resets) in 9 ms. (400 steps per ms) remains 16/16 properties
BEST_FIRST walk for 4004 steps (8 resets) in 10 ms. (364 steps per ms) remains 16/16 properties
BEST_FIRST walk for 4004 steps (8 resets) in 15 ms. (250 steps per ms) remains 16/16 properties
BEST_FIRST walk for 4003 steps (8 resets) in 9 ms. (400 steps per ms) remains 16/16 properties
BEST_FIRST walk for 4003 steps (8 resets) in 14 ms. (266 steps per ms) remains 16/16 properties
BEST_FIRST walk for 4002 steps (8 resets) in 9 ms. (400 steps per ms) remains 16/16 properties
BEST_FIRST walk for 4004 steps (8 resets) in 16 ms. (235 steps per ms) remains 16/16 properties
BEST_FIRST walk for 4003 steps (8 resets) in 14 ms. (266 steps per ms) remains 16/16 properties
Interrupted probabilistic random walk after 236457 steps, run timeout after 3001 ms. (steps per millisecond=78 ) properties seen :0 out of 16
Probabilistic random walk after 236457 steps, saw 129338 distinct states, run finished after 3021 ms. (steps per millisecond=78 ) properties seen :0
[2024-06-01 15:36:08] [INFO ] Invariant cache hit.
At refinement iteration 0 (INCLUDED_ONLY) 0/9 variables, 4/4 constraints. Problems are: Problem set: 0 solved, 16 unsolved
At refinement iteration 1 (INCLUDED_ONLY) 0/9 variables, 0/4 constraints. Problems are: Problem set: 0 solved, 16 unsolved
At refinement iteration 2 (OVERLAPS) 8/17 variables, 9/13 constraints. Problems are: Problem set: 0 solved, 16 unsolved
At refinement iteration 3 (INCLUDED_ONLY) 0/17 variables, 0/13 constraints. Problems are: Problem set: 0 solved, 16 unsolved
At refinement iteration 4 (OVERLAPS) 0/17 variables, 0/13 constraints. Problems are: Problem set: 0 solved, 16 unsolved
No progress, stopping.
After SMT solving in domain Real declared 17/17 variables, and 13 constraints, problems are : Problem set: 0 solved, 16 unsolved in 174 ms.
Refiners :[Positive P Invariants (semi-flows): 4/4 constraints, State Equation: 9/9 constraints, PredecessorRefiner: 16/16 constraints, Known Traps: 0/0 constraints]
Escalating to Integer solving :Problem set: 0 solved, 16 unsolved
At refinement iteration 0 (INCLUDED_ONLY) 0/9 variables, 4/4 constraints. Problems are: Problem set: 0 solved, 16 unsolved
At refinement iteration 1 (INCLUDED_ONLY) 0/9 variables, 0/4 constraints. Problems are: Problem set: 0 solved, 16 unsolved
At refinement iteration 2 (OVERLAPS) 8/17 variables, 9/13 constraints. Problems are: Problem set: 0 solved, 16 unsolved
At refinement iteration 3 (INCLUDED_ONLY) 0/17 variables, 16/29 constraints. Problems are: Problem set: 0 solved, 16 unsolved
At refinement iteration 4 (INCLUDED_ONLY) 0/17 variables, 0/29 constraints. Problems are: Problem set: 0 solved, 16 unsolved
At refinement iteration 5 (OVERLAPS) 0/17 variables, 0/29 constraints. Problems are: Problem set: 0 solved, 16 unsolved
No progress, stopping.
After SMT solving in domain Int declared 17/17 variables, and 29 constraints, problems are : Problem set: 0 solved, 16 unsolved in 214 ms.
Refiners :[Positive P Invariants (semi-flows): 4/4 constraints, State Equation: 9/9 constraints, PredecessorRefiner: 16/16 constraints, Known Traps: 0/0 constraints]
After SMT, in 407ms problems are : Problem set: 0 solved, 16 unsolved
Parikh walk visited 9 properties in 33993 ms.
Support contains 7 out of 9 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 6 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 6 ms. Remains : 9/9 places, 8/8 transitions.
RANDOM walk for 49172 steps (8 resets) in 23 ms. (2048 steps per ms) remains 7/7 properties
BEST_FIRST walk for 40001 steps (8 resets) in 68 ms. (579 steps per ms) remains 7/7 properties
BEST_FIRST walk for 40004 steps (8 resets) in 46 ms. (851 steps per ms) remains 7/7 properties
BEST_FIRST walk for 40004 steps (8 resets) in 65 ms. (606 steps per ms) remains 7/7 properties
BEST_FIRST walk for 40003 steps (8 resets) in 51 ms. (769 steps per ms) remains 7/7 properties
BEST_FIRST walk for 40004 steps (8 resets) in 65 ms. (606 steps per ms) remains 7/7 properties
BEST_FIRST walk for 40003 steps (8 resets) in 42 ms. (930 steps per ms) remains 7/7 properties
BEST_FIRST walk for 40003 steps (8 resets) in 53 ms. (740 steps per ms) remains 7/7 properties
Interrupted probabilistic random walk after 335222 steps, run timeout after 3001 ms. (steps per millisecond=111 ) properties seen :0 out of 7
Probabilistic random walk after 335222 steps, saw 183661 distinct states, run finished after 3001 ms. (steps per millisecond=111 ) properties seen :0
[2024-06-01 15:36:45] [INFO ] Invariant cache hit.
At refinement iteration 0 (INCLUDED_ONLY) 0/7 variables, 1/1 constraints. Problems are: Problem set: 0 solved, 7 unsolved
At refinement iteration 1 (INCLUDED_ONLY) 0/7 variables, 0/1 constraints. Problems are: Problem set: 0 solved, 7 unsolved
At refinement iteration 2 (OVERLAPS) 2/9 variables, 3/4 constraints. Problems are: Problem set: 0 solved, 7 unsolved
At refinement iteration 3 (INCLUDED_ONLY) 0/9 variables, 0/4 constraints. Problems are: Problem set: 0 solved, 7 unsolved
At refinement iteration 4 (OVERLAPS) 8/17 variables, 9/13 constraints. Problems are: Problem set: 0 solved, 7 unsolved
At refinement iteration 5 (INCLUDED_ONLY) 0/17 variables, 0/13 constraints. Problems are: Problem set: 0 solved, 7 unsolved
At refinement iteration 6 (OVERLAPS) 0/17 variables, 0/13 constraints. Problems are: Problem set: 0 solved, 7 unsolved
No progress, stopping.
After SMT solving in domain Real declared 17/17 variables, and 13 constraints, problems are : Problem set: 0 solved, 7 unsolved in 138 ms.
Refiners :[Positive P Invariants (semi-flows): 4/4 constraints, State Equation: 9/9 constraints, PredecessorRefiner: 7/7 constraints, Known Traps: 0/0 constraints]
Escalating to Integer solving :Problem set: 0 solved, 7 unsolved
At refinement iteration 0 (INCLUDED_ONLY) 0/7 variables, 1/1 constraints. Problems are: Problem set: 0 solved, 7 unsolved
At refinement iteration 1 (INCLUDED_ONLY) 0/7 variables, 0/1 constraints. Problems are: Problem set: 0 solved, 7 unsolved
At refinement iteration 2 (OVERLAPS) 2/9 variables, 3/4 constraints. Problems are: Problem set: 0 solved, 7 unsolved
At refinement iteration 3 (INCLUDED_ONLY) 0/9 variables, 0/4 constraints. Problems are: Problem set: 0 solved, 7 unsolved
At refinement iteration 4 (OVERLAPS) 8/17 variables, 9/13 constraints. Problems are: Problem set: 0 solved, 7 unsolved
At refinement iteration 5 (INCLUDED_ONLY) 0/17 variables, 7/20 constraints. Problems are: Problem set: 0 solved, 7 unsolved
At refinement iteration 6 (INCLUDED_ONLY) 0/17 variables, 0/20 constraints. Problems are: Problem set: 0 solved, 7 unsolved
At refinement iteration 7 (OVERLAPS) 0/17 variables, 0/20 constraints. Problems are: Problem set: 0 solved, 7 unsolved
No progress, stopping.
After SMT solving in domain Int declared 17/17 variables, and 20 constraints, problems are : Problem set: 0 solved, 7 unsolved in 138 ms.
Refiners :[Positive P Invariants (semi-flows): 4/4 constraints, State Equation: 9/9 constraints, PredecessorRefiner: 7/7 constraints, Known Traps: 0/0 constraints]
After SMT, in 294ms problems are : Problem set: 0 solved, 7 unsolved
Parikh walk visited 3 properties in 55011 ms.
Support contains 7 out of 9 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 14 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 14 ms. Remains : 9/9 places, 8/8 transitions.
Successfully simplified 19 atomic propositions for a total of 15 simplifications.
[2024-06-01 15:37:41] [INFO ] Initial state reduction rules for CTL removed 2 formulas.
[2024-06-01 15:37:41] [INFO ] Flatten gal took : 5 ms
[2024-06-01 15:37:41] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
FORMULA SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-2023-15 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-2023-14 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-2024-00 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2024-06-01 15:37:41] [INFO ] Flatten gal took : 3 ms
[2024-06-01 15:37:41] [INFO ] Input system was already deterministic with 8 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 8
Applied a total of 1 rules in 10 ms. Remains 8 /9 variables (removed 1) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 10 ms. Remains : 8/9 places, 8/8 transitions.
[2024-06-01 15:37:41] [INFO ] Flatten gal took : 2 ms
[2024-06-01 15:37:41] [INFO ] Flatten gal took : 2 ms
[2024-06-01 15:37:41] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 8 transition count 7
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 8 transition count 7
Applied a total of 2 rules in 6 ms. Remains 8 /9 variables (removed 1) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 6 ms. Remains : 8/9 places, 7/8 transitions.
[2024-06-01 15:37:41] [INFO ] Flatten gal took : 2 ms
[2024-06-01 15:37:41] [INFO ] Flatten gal took : 2 ms
[2024-06-01 15:37:41] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 8 transition count 7
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 8 transition count 7
Applied a total of 2 rules in 1 ms. Remains 8 /9 variables (removed 1) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1 ms. Remains : 8/9 places, 7/8 transitions.
[2024-06-01 15:37:41] [INFO ] Flatten gal took : 1 ms
[2024-06-01 15:37:41] [INFO ] Flatten gal took : 1 ms
[2024-06-01 15:37:41] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 8
Discarding 1 places :
Symmetric choice reduction at 1 with 1 rule applications. Total rules 2 place count 7 transition count 7
Iterating global reduction 1 with 1 rules applied. Total rules applied 3 place count 7 transition count 7
Applied a total of 3 rules in 0 ms. Remains 7 /9 variables (removed 2) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 7/9 places, 7/8 transitions.
[2024-06-01 15:37:41] [INFO ] Flatten gal took : 1 ms
[2024-06-01 15:37:41] [INFO ] Flatten gal took : 1 ms
[2024-06-01 15:37:41] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 0 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 9/9 places, 8/8 transitions.
[2024-06-01 15:37:41] [INFO ] Flatten gal took : 1 ms
[2024-06-01 15:37:41] [INFO ] Flatten gal took : 2 ms
[2024-06-01 15:37:41] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 0 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 9/9 places, 8/8 transitions.
[2024-06-01 15:37:41] [INFO ] Flatten gal took : 1 ms
[2024-06-01 15:37:41] [INFO ] Flatten gal took : 1 ms
[2024-06-01 15:37:41] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 0 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 9/9 places, 8/8 transitions.
[2024-06-01 15:37:41] [INFO ] Flatten gal took : 1 ms
[2024-06-01 15:37:41] [INFO ] Flatten gal took : 1 ms
[2024-06-01 15:37:41] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 8
Discarding 1 places :
Symmetric choice reduction at 1 with 1 rule applications. Total rules 2 place count 7 transition count 7
Iterating global reduction 1 with 1 rules applied. Total rules applied 3 place count 7 transition count 7
Applied a total of 3 rules in 1 ms. Remains 7 /9 variables (removed 2) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 7/9 places, 7/8 transitions.
[2024-06-01 15:37:41] [INFO ] Flatten gal took : 1 ms
[2024-06-01 15:37:41] [INFO ] Flatten gal took : 1 ms
[2024-06-01 15:37:41] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Applied a total of 0 rules in 1 ms. Remains 8 /9 variables (removed 1) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1 ms. Remains : 8/9 places, 8/8 transitions.
[2024-06-01 15:37:41] [INFO ] Flatten gal took : 1 ms
[2024-06-01 15:37:41] [INFO ] Flatten gal took : 1 ms
[2024-06-01 15:37:41] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 8
Applied a total of 1 rules in 0 ms. Remains 8 /9 variables (removed 1) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/9 places, 8/8 transitions.
[2024-06-01 15:37:41] [INFO ] Flatten gal took : 1 ms
[2024-06-01 15:37:41] [INFO ] Flatten gal took : 1 ms
[2024-06-01 15:37:41] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 8 transition count 7
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 8 transition count 7
Applied a total of 2 rules in 1 ms. Remains 8 /9 variables (removed 1) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/9 places, 7/8 transitions.
[2024-06-01 15:37:41] [INFO ] Flatten gal took : 1 ms
[2024-06-01 15:37:41] [INFO ] Flatten gal took : 1 ms
[2024-06-01 15:37:41] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 1 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1 ms. Remains : 9/9 places, 8/8 transitions.
[2024-06-01 15:37:41] [INFO ] Flatten gal took : 2 ms
[2024-06-01 15:37:41] [INFO ] Flatten gal took : 1 ms
[2024-06-01 15:37:41] [INFO ] Input system was already deterministic with 8 transitions.
[2024-06-01 15:37:41] [INFO ] Flatten gal took : 2 ms
[2024-06-01 15:37:41] [INFO ] Flatten gal took : 2 ms
[2024-06-01 15:37:41] [INFO ] Export to MCC of 12 properties in file /home/mcc/execution/CTLCardinality.sr.xml took 4 ms.
[2024-06-01 15:37:41] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 9 places, 8 transitions and 27 arcs took 6 ms.
Total runtime 133743 ms.
There are residual formulas that ITS could not solve within timeout
Usage: pnml2lts-sym [-gvqh] [--order=
[--mu-opt] [--saturation=
[--sat-granularity=
[--guidance=
[--action=
[--trace=
[--mu=
[--ctl=
[--save-levels=STRING] [--pg-solve] [--attr=
[--saturating-attractor] [--write-strategy=
[--check-strategy] [--interactive-play] [--player]
[--pg-write=
[--edge-label=
[--mucalc=
[--allow-undefined-edges] [--allow-undefined-values]
[-p|--por=
[--weak=[valmari] (default: uses stronger left-commutativity)]
[--leap] [-r|--regroup=<(T,)+>] [--sloan-w1=
[--cw-max-cols=
[--mh-timeout=
[--graph-metrics] [--regroup-exit] [--regroup-time]
[-g|--pins-guards] [--vset=
[--ldd32-cache=
[--cache-ratio=
[--min-free-nodes=
[--fdd-reorder=
[--vset-cache-diff=
[--next-union] [--peak-nodes] [--maxsum=
[--block-size=
[--debug=
[--timeout=INT] [--version] [-h|--help] [--usage]
[OPTIONS]
Could not compute solution for formula : SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-2024-02
Could not compute solution for formula : SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-2024-03
Could not compute solution for formula : SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-2024-04
Could not compute solution for formula : SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-2024-05
Could not compute solution for formula : SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-2024-06
Could not compute solution for formula : SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-2024-07
Could not compute solution for formula : SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-2024-08
Could not compute solution for formula : SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-2024-09
Could not compute solution for formula : SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-2024-10
Could not compute solution for formula : SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-2024-11
Could not compute solution for formula : SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-2023-12
Could not compute solution for formula : SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-2023-13
BK_STOP 1717256261881
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202405141337.jar
+ VERSION=202405141337
+ echo 'Running Version 202405141337'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLCardinality -timeout 360 -rebuildPNML
mcc2024
ctl formula name SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-2024-02
ctl formula formula --ctl=/tmp/531/ctl_0_
ctl formula name SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-2024-03
ctl formula formula --ctl=/tmp/531/ctl_1_
ctl formula name SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-2024-04
ctl formula formula --ctl=/tmp/531/ctl_2_
ctl formula name SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-2024-05
ctl formula formula --ctl=/tmp/531/ctl_3_
ctl formula name SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-2024-06
ctl formula formula --ctl=/tmp/531/ctl_4_
ctl formula name SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-2024-07
ctl formula formula --ctl=/tmp/531/ctl_5_
ctl formula name SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-2024-08
ctl formula formula --ctl=/tmp/531/ctl_6_
ctl formula name SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-2024-09
ctl formula formula --ctl=/tmp/531/ctl_7_
ctl formula name SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-2024-10
ctl formula formula --ctl=/tmp/531/ctl_8_
ctl formula name SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-2024-11
ctl formula formula --ctl=/tmp/531/ctl_9_
ctl formula name SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-2023-12
ctl formula formula --ctl=/tmp/531/ctl_10_
ctl formula name SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-2023-13
ctl formula formula --ctl=/tmp/531/ctl_11_
pnml2lts-sym, ** error **: unknown vector set implementation lddmc
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="SmallOperatingSystem-PT-MT8192DC4096"
export BK_EXAMINATION="CTLCardinality"
export BK_TOOL="ltsminxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool ltsminxred"
echo " Input is SmallOperatingSystem-PT-MT8192DC4096, examination is CTLCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r532-smll-171683811300329"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/SmallOperatingSystem-PT-MT8192DC4096.tgz
mv SmallOperatingSystem-PT-MT8192DC4096 execution
cd execution
if [ "CTLCardinality" = "ReachabilityDeadlock" ] || [ "CTLCardinality" = "UpperBounds" ] || [ "CTLCardinality" = "QuasiLiveness" ] || [ "CTLCardinality" = "StableMarking" ] || [ "CTLCardinality" = "Liveness" ] || [ "CTLCardinality" = "OneSafe" ] || [ "CTLCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLCardinality" = "ReachabilityDeadlock" ] || [ "CTLCardinality" = "QuasiLiveness" ] || [ "CTLCardinality" = "StableMarking" ] || [ "CTLCardinality" = "Liveness" ] || [ "CTLCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;