Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r532-smll-171683811200322.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool ltsminxred
Input is SmallOperatingSystem-PT-MT8192DC2048, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r532-smll-171683811200322
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 496K
-rw-r--r-- 1 mcc users 7.7K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 69K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 7.0K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 57K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:43 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.7K May 18 16:43 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.7K Apr 23 07:57 LTLCardinality.txt
-rw-r--r-- 1 mcc users 29K Apr 23 07:57 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.7K Apr 23 07:57 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Apr 23 07:57 LTLFireability.xml
-rw-r--r-- 1 mcc users 15K Apr 12 14:02 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 127K Apr 12 14:02 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Apr 12 14:02 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 74K Apr 12 14:02 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.1K Apr 23 07:57 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.1K Apr 23 07:57 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 13 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 8.1K May 18 16:43 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15

=== Now, execution of the tool begins

BK_START 1717255978686

Invoking MCC driver with
BK_TOOL=ltsminxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=SmallOperatingSystem-PT-MT8192DC2048
BK_MEMORY_CONFINEMENT=16384
Applying reductions before tool ltsmin
Invoking reducer
Running Version 202405141337
[2024-06-01 15:33:00] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2024-06-01 15:33:00] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2024-06-01 15:33:00] [INFO ] Load time of PNML (sax parser for PT used): 60 ms
[2024-06-01 15:33:00] [INFO ] Transformed 9 places.
[2024-06-01 15:33:00] [INFO ] Transformed 8 transitions.
[2024-06-01 15:33:00] [INFO ] Parsed PT model containing 9 places and 8 transitions and 27 arcs in 232 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 37 ms.
Initial state reduction rules removed 1 formulas.
FORMULA SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 9 out of 9 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 17 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
// Phase 1: matrix 8 rows 9 cols
[2024-06-01 15:33:01] [INFO ] Computed 4 invariants in 5 ms
[2024-06-01 15:33:01] [INFO ] Implicit Places using invariants in 212 ms returned []
[2024-06-01 15:33:01] [INFO ] Invariant cache hit.
[2024-06-01 15:33:01] [INFO ] Implicit Places using invariants and state equation in 65 ms returned []
Implicit Place search using SMT with State Equation took 337 ms to find 0 implicit places.
Running 7 sub problems to find dead transitions.
[2024-06-01 15:33:01] [INFO ] Invariant cache hit.
At refinement iteration 0 (INCLUDED_ONLY) 0/8 variables, 3/3 constraints. Problems are: Problem set: 0 solved, 7 unsolved
At refinement iteration 1 (INCLUDED_ONLY) 0/8 variables, 0/3 constraints. Problems are: Problem set: 0 solved, 7 unsolved
At refinement iteration 2 (OVERLAPS) 1/9 variables, 1/4 constraints. Problems are: Problem set: 0 solved, 7 unsolved
At refinement iteration 3 (INCLUDED_ONLY) 0/9 variables, 0/4 constraints. Problems are: Problem set: 0 solved, 7 unsolved
At refinement iteration 4 (OVERLAPS) 8/17 variables, 9/13 constraints. Problems are: Problem set: 0 solved, 7 unsolved
At refinement iteration 5 (INCLUDED_ONLY) 0/17 variables, 0/13 constraints. Problems are: Problem set: 0 solved, 7 unsolved
At refinement iteration 6 (OVERLAPS) 0/17 variables, 0/13 constraints. Problems are: Problem set: 0 solved, 7 unsolved
No progress, stopping.
After SMT solving in domain Real declared 17/17 variables, and 13 constraints, problems are : Problem set: 0 solved, 7 unsolved in 172 ms.
Refiners :[Positive P Invariants (semi-flows): 4/4 constraints, State Equation: 9/9 constraints, PredecessorRefiner: 7/7 constraints, Known Traps: 0/0 constraints]
Escalating to Integer solving :Problem set: 0 solved, 7 unsolved
At refinement iteration 0 (INCLUDED_ONLY) 0/8 variables, 3/3 constraints. Problems are: Problem set: 0 solved, 7 unsolved
At refinement iteration 1 (INCLUDED_ONLY) 0/8 variables, 0/3 constraints. Problems are: Problem set: 0 solved, 7 unsolved
At refinement iteration 2 (OVERLAPS) 1/9 variables, 1/4 constraints. Problems are: Problem set: 0 solved, 7 unsolved
At refinement iteration 3 (INCLUDED_ONLY) 0/9 variables, 0/4 constraints. Problems are: Problem set: 0 solved, 7 unsolved
At refinement iteration 4 (OVERLAPS) 8/17 variables, 9/13 constraints. Problems are: Problem set: 0 solved, 7 unsolved
At refinement iteration 5 (INCLUDED_ONLY) 0/17 variables, 7/20 constraints. Problems are: Problem set: 0 solved, 7 unsolved
At refinement iteration 6 (INCLUDED_ONLY) 0/17 variables, 0/20 constraints. Problems are: Problem set: 0 solved, 7 unsolved
At refinement iteration 7 (OVERLAPS) 0/17 variables, 0/20 constraints. Problems are: Problem set: 0 solved, 7 unsolved
No progress, stopping.
After SMT solving in domain Int declared 17/17 variables, and 20 constraints, problems are : Problem set: 0 solved, 7 unsolved in 134 ms.
Refiners :[Positive P Invariants (semi-flows): 4/4 constraints, State Equation: 9/9 constraints, PredecessorRefiner: 7/7 constraints, Known Traps: 0/0 constraints]
After SMT, in 340ms problems are : Problem set: 0 solved, 7 unsolved
Search for dead transitions found 0 dead transitions in 355ms
Finished structural reductions in LTL mode , in 1 iterations and 756 ms. Remains : 9/9 places, 8/8 transitions.
Support contains 9 out of 9 places after structural reductions.
[2024-06-01 15:33:01] [INFO ] Flatten gal took : 20 ms
[2024-06-01 15:33:02] [INFO ] Flatten gal took : 7 ms
[2024-06-01 15:33:02] [INFO ] Input system was already deterministic with 8 transitions.
Reduction of identical properties reduced properties to check from 32 to 29
RANDOM walk for 40988 steps (8 resets) in 101 ms. (401 steps per ms) remains 17/29 properties
BEST_FIRST walk for 4004 steps (8 resets) in 66 ms. (59 steps per ms) remains 2/17 properties
BEST_FIRST walk for 4003 steps (8 resets) in 111 ms. (35 steps per ms) remains 2/2 properties
BEST_FIRST walk for 4002 steps (8 resets) in 46 ms. (85 steps per ms) remains 2/2 properties
[2024-06-01 15:33:02] [INFO ] Invariant cache hit.
Problem AtomicPropp13 is UNSAT
At refinement iteration 0 (INCLUDED_ONLY) 0/7 variables, 2/2 constraints. Problems are: Problem set: 1 solved, 1 unsolved
At refinement iteration 1 (INCLUDED_ONLY) 0/7 variables, 0/2 constraints. Problems are: Problem set: 1 solved, 1 unsolved
At refinement iteration 2 (OVERLAPS) 1/8 variables, 1/3 constraints. Problems are: Problem set: 1 solved, 1 unsolved
At refinement iteration 3 (INCLUDED_ONLY) 0/8 variables, 0/3 constraints. Problems are: Problem set: 1 solved, 1 unsolved
At refinement iteration 4 (OVERLAPS) 1/9 variables, 1/4 constraints. Problems are: Problem set: 1 solved, 1 unsolved
At refinement iteration 5 (INCLUDED_ONLY) 0/9 variables, 0/4 constraints. Problems are: Problem set: 1 solved, 1 unsolved
All remaining problems are real, not stopping.
At refinement iteration 6 (OVERLAPS) 8/17 variables, 9/13 constraints. Problems are: Problem set: 1 solved, 1 unsolved
At refinement iteration 7 (INCLUDED_ONLY) 0/17 variables, 0/13 constraints. Problems are: Problem set: 1 solved, 1 unsolved
At refinement iteration 8 (OVERLAPS) 0/17 variables, 0/13 constraints. Problems are: Problem set: 1 solved, 1 unsolved
No progress, stopping.
After SMT solving in domain Real declared 17/17 variables, and 13 constraints, problems are : Problem set: 1 solved, 1 unsolved in 43 ms.
Refiners :[Positive P Invariants (semi-flows): 4/4 constraints, State Equation: 9/9 constraints, PredecessorRefiner: 2/2 constraints, Known Traps: 0/0 constraints]
Escalating to Integer solving :Problem set: 1 solved, 1 unsolved
At refinement iteration 0 (INCLUDED_ONLY) 0/5 variables, 2/2 constraints. Problems are: Problem set: 1 solved, 1 unsolved
At refinement iteration 1 (INCLUDED_ONLY) 0/5 variables, 0/2 constraints. Problems are: Problem set: 1 solved, 1 unsolved
At refinement iteration 2 (OVERLAPS) 3/8 variables, 1/3 constraints. Problems are: Problem set: 1 solved, 1 unsolved
At refinement iteration 3 (INCLUDED_ONLY) 0/8 variables, 0/3 constraints. Problems are: Problem set: 1 solved, 1 unsolved
At refinement iteration 4 (OVERLAPS) 1/9 variables, 1/4 constraints. Problems are: Problem set: 1 solved, 1 unsolved
At refinement iteration 5 (INCLUDED_ONLY) 0/9 variables, 0/4 constraints. Problems are: Problem set: 1 solved, 1 unsolved
At refinement iteration 6 (OVERLAPS) 8/17 variables, 9/13 constraints. Problems are: Problem set: 1 solved, 1 unsolved
At refinement iteration 7 (INCLUDED_ONLY) 0/17 variables, 1/14 constraints. Problems are: Problem set: 1 solved, 1 unsolved
At refinement iteration 8 (INCLUDED_ONLY) 0/17 variables, 0/14 constraints. Problems are: Problem set: 1 solved, 1 unsolved
At refinement iteration 9 (OVERLAPS) 0/17 variables, 0/14 constraints. Problems are: Problem set: 1 solved, 1 unsolved
No progress, stopping.
After SMT solving in domain Int declared 17/17 variables, and 14 constraints, problems are : Problem set: 1 solved, 1 unsolved in 43 ms.
Refiners :[Positive P Invariants (semi-flows): 4/4 constraints, State Equation: 9/9 constraints, PredecessorRefiner: 1/2 constraints, Known Traps: 0/0 constraints]
After SMT, in 93ms problems are : Problem set: 1 solved, 1 unsolved
Finished Parikh walk after 32692 steps, including 0 resets, run visited all 1 properties in 183 ms. (steps per millisecond=178 )
Parikh walk visited 1 properties in 191 ms.
Successfully simplified 1 atomic propositions for a total of 15 simplifications.
[2024-06-01 15:33:02] [INFO ] Flatten gal took : 4 ms
[2024-06-01 15:33:02] [INFO ] Flatten gal took : 4 ms
[2024-06-01 15:33:02] [INFO ] Input system was already deterministic with 8 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 8
Applied a total of 1 rules in 10 ms. Remains 8 /9 variables (removed 1) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 10 ms. Remains : 8/9 places, 8/8 transitions.
[2024-06-01 15:33:02] [INFO ] Flatten gal took : 2 ms
[2024-06-01 15:33:02] [INFO ] Flatten gal took : 2 ms
[2024-06-01 15:33:02] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 1 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 9/9 places, 8/8 transitions.
[2024-06-01 15:33:02] [INFO ] Flatten gal took : 1 ms
[2024-06-01 15:33:02] [INFO ] Flatten gal took : 2 ms
[2024-06-01 15:33:02] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 1 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 9/9 places, 8/8 transitions.
[2024-06-01 15:33:02] [INFO ] Flatten gal took : 2 ms
[2024-06-01 15:33:02] [INFO ] Flatten gal took : 2 ms
[2024-06-01 15:33:02] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 5 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 5 ms. Remains : 9/9 places, 8/8 transitions.
[2024-06-01 15:33:02] [INFO ] Flatten gal took : 1 ms
[2024-06-01 15:33:02] [INFO ] Flatten gal took : 2 ms
[2024-06-01 15:33:02] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 1 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1 ms. Remains : 9/9 places, 8/8 transitions.
[2024-06-01 15:33:02] [INFO ] Flatten gal took : 2 ms
[2024-06-01 15:33:02] [INFO ] Flatten gal took : 2 ms
[2024-06-01 15:33:02] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 7 transition count 7
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 7 transition count 7
Applied a total of 2 rules in 6 ms. Remains 7 /9 variables (removed 2) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 6 ms. Remains : 7/9 places, 7/8 transitions.
[2024-06-01 15:33:02] [INFO ] Flatten gal took : 1 ms
[2024-06-01 15:33:02] [INFO ] Flatten gal took : 1 ms
[2024-06-01 15:33:02] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 0 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 9/9 places, 8/8 transitions.
[2024-06-01 15:33:02] [INFO ] Flatten gal took : 2 ms
[2024-06-01 15:33:02] [INFO ] Flatten gal took : 2 ms
[2024-06-01 15:33:02] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 1 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1 ms. Remains : 9/9 places, 8/8 transitions.
[2024-06-01 15:33:02] [INFO ] Flatten gal took : 2 ms
[2024-06-01 15:33:02] [INFO ] Flatten gal took : 2 ms
[2024-06-01 15:33:02] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 1 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 9/9 places, 8/8 transitions.
[2024-06-01 15:33:02] [INFO ] Flatten gal took : 1 ms
[2024-06-01 15:33:02] [INFO ] Flatten gal took : 1 ms
[2024-06-01 15:33:02] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 8
Applied a total of 1 rules in 1 ms. Remains 8 /9 variables (removed 1) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/9 places, 8/8 transitions.
[2024-06-01 15:33:02] [INFO ] Flatten gal took : 2 ms
[2024-06-01 15:33:02] [INFO ] Flatten gal took : 1 ms
[2024-06-01 15:33:02] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 8 transition count 7
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 8 transition count 7
Applied a total of 2 rules in 1 ms. Remains 8 /9 variables (removed 1) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/9 places, 7/8 transitions.
[2024-06-01 15:33:02] [INFO ] Flatten gal took : 1 ms
[2024-06-01 15:33:02] [INFO ] Flatten gal took : 2 ms
[2024-06-01 15:33:02] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 0 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 9/9 places, 8/8 transitions.
[2024-06-01 15:33:02] [INFO ] Flatten gal took : 1 ms
[2024-06-01 15:33:02] [INFO ] Flatten gal took : 1 ms
[2024-06-01 15:33:02] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 8
Discarding 1 places :
Symmetric choice reduction at 1 with 1 rule applications. Total rules 2 place count 7 transition count 7
Iterating global reduction 1 with 1 rules applied. Total rules applied 3 place count 7 transition count 7
Applied a total of 3 rules in 1 ms. Remains 7 /9 variables (removed 2) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 7/9 places, 7/8 transitions.
[2024-06-01 15:33:02] [INFO ] Flatten gal took : 1 ms
[2024-06-01 15:33:02] [INFO ] Flatten gal took : 2 ms
[2024-06-01 15:33:02] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 0 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 9/9 places, 8/8 transitions.
[2024-06-01 15:33:02] [INFO ] Flatten gal took : 2 ms
[2024-06-01 15:33:02] [INFO ] Flatten gal took : 1 ms
[2024-06-01 15:33:02] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Drop transitions (Trivial Post-Agglo cleanup.) removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 0 with 2 rules applied. Total rules applied 2 place count 8 transition count 6
Reduce places removed 3 places and 0 transitions.
Graph (trivial) has 3 edges and 5 vertex of which 2 / 5 are part of one of the 1 SCC in 2 ms
Free SCC test removed 1 places
Iterating post reduction 1 with 4 rules applied. Total rules applied 6 place count 4 transition count 6
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 7 place count 4 transition count 5
Applied a total of 7 rules in 20 ms. Remains 4 /9 variables (removed 5) and now considering 5/8 (removed 3) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 20 ms. Remains : 4/9 places, 5/8 transitions.
[2024-06-01 15:33:02] [INFO ] Flatten gal took : 1 ms
[2024-06-01 15:33:02] [INFO ] Flatten gal took : 1 ms
[2024-06-01 15:33:02] [INFO ] Input system was already deterministic with 5 transitions.
RANDOM walk for 4 steps (0 resets) in 6 ms. (0 steps per ms) remains 0/1 properties
FORMULA SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
[2024-06-01 15:33:02] [INFO ] Flatten gal took : 2 ms
[2024-06-01 15:33:02] [INFO ] Flatten gal took : 3 ms
[2024-06-01 15:33:02] [INFO ] Export to MCC of 14 properties in file /home/mcc/execution/CTLFireability.sr.xml took 4 ms.
[2024-06-01 15:33:02] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 9 places, 8 transitions and 27 arcs took 5 ms.
Total runtime 2363 ms.
There are residual formulas that ITS could not solve within timeout
Usage: pnml2lts-sym [-gvqh] [--order=]
[--mu-opt] [--saturation=]
[--sat-granularity=] [--save-sat-levels]
[--guidance=] [-d|--deadlock]
[--action=] [-i|--invariant=STRING] [-n|--no-exit]
[--trace=] [--type=]
[--mu=.mu] [--ctl-star=.ctl]
[--ctl=.ctl] [--ltl=.ltl] [--dot=STRING]
[--save-levels=STRING] [--pg-solve] [--attr=]
[--saturating-attractor] [--write-strategy=.spg]
[--check-strategy] [--interactive-play] [--player]
[--pg-write=.spg] [--no-matrix] [--noack=<1|2>]
[--edge-label=] [--labels] [-m|--matrix]
[--mucalc=.mcf|] [-c|--cache]
[--allow-undefined-edges] [--allow-undefined-values]
[-p|--por= (default: heur)]
[--weak=[valmari] (default: uses stronger left-commutativity)]
[--leap] [-r|--regroup=<(T,)+>] [--sloan-w1=] [--sloan-w2=]
[--cw-max-cols=] [--cw-max-rows=] [--col-ins=<(C.C',)+>]
[--mh-timeout=] [--row-perm=<(R,)+>] [--col-perm=<(C,)+>]
[--graph-metrics] [--regroup-exit] [--regroup-time]
[-g|--pins-guards] [--vset=] [--ldd32-step=]
[--ldd32-cache=] [--ldd-step=] [--ldd-cache=]
[--cache-ratio=] [--max-increase=]
[--min-free-nodes=] [--fdd-bits=]
[--fdd-reorder=]
[--vset-cache-diff=] [--no-soundness-check] [--precise]
[--next-union] [--peak-nodes] [--maxsum=]
[--block-size=] [--cluster-size=] [-v] [-q]
[--debug=] [--stats] [--where] [--when]
[--timeout=INT] [--version] [-h|--help] [--usage]
[OPTIONS] []
Could not compute solution for formula : SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00
Could not compute solution for formula : SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01
Could not compute solution for formula : SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02
Could not compute solution for formula : SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03
Could not compute solution for formula : SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04
Could not compute solution for formula : SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05
Could not compute solution for formula : SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06
Could not compute solution for formula : SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07
Could not compute solution for formula : SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08
Could not compute solution for formula : SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09
Could not compute solution for formula : SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10
Could not compute solution for formula : SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12
Could not compute solution for formula : SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13
Could not compute solution for formula : SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14

BK_STOP 1717255983307

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202405141337.jar
+ VERSION=202405141337
+ echo 'Running Version 202405141337'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
mcc2024
ctl formula name SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00
ctl formula formula --ctl=/tmp/508/ctl_0_
ctl formula name SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01
ctl formula formula --ctl=/tmp/508/ctl_1_
ctl formula name SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02
ctl formula formula --ctl=/tmp/508/ctl_2_
ctl formula name SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03
ctl formula formula --ctl=/tmp/508/ctl_3_
ctl formula name SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04
ctl formula formula --ctl=/tmp/508/ctl_4_
ctl formula name SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05
ctl formula formula --ctl=/tmp/508/ctl_5_
ctl formula name SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06
ctl formula formula --ctl=/tmp/508/ctl_6_
ctl formula name SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07
ctl formula formula --ctl=/tmp/508/ctl_7_
ctl formula name SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08
ctl formula formula --ctl=/tmp/508/ctl_8_
ctl formula name SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09
ctl formula formula --ctl=/tmp/508/ctl_9_
ctl formula name SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10
ctl formula formula --ctl=/tmp/508/ctl_10_
ctl formula name SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12
ctl formula formula --ctl=/tmp/508/ctl_11_
ctl formula name SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13
ctl formula formula --ctl=/tmp/508/ctl_12_
ctl formula name SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14
ctl formula formula --ctl=/tmp/508/ctl_13_
pnml2lts-sym, ** error **: unknown vector set implementation lddmc

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="SmallOperatingSystem-PT-MT8192DC2048"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="ltsminxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool ltsminxred"
echo " Input is SmallOperatingSystem-PT-MT8192DC2048, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r532-smll-171683811200322"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/SmallOperatingSystem-PT-MT8192DC2048.tgz
mv SmallOperatingSystem-PT-MT8192DC2048 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;