Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r528-tall-171683762200962.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool ltsminxred
Input is ShieldRVt-PT-010A, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r528-tall-171683762200962
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 516K
-rw-r--r-- 1 mcc users 5.8K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 60K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.6K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 40K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:43 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.6K May 18 16:43 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.6K Apr 23 07:55 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Apr 23 07:55 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Apr 23 07:55 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Apr 23 07:55 LTLFireability.xml
-rw-r--r-- 1 mcc users 17K Apr 11 22:56 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 197K Apr 11 22:56 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 6.5K Apr 11 22:50 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 53K Apr 11 22:50 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Apr 23 07:55 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Apr 23 07:55 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 5 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 27K May 18 16:43 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME ShieldRVt-PT-010A-CTLFireability-2024-00
FORMULA_NAME ShieldRVt-PT-010A-CTLFireability-2024-01
FORMULA_NAME ShieldRVt-PT-010A-CTLFireability-2024-02
FORMULA_NAME ShieldRVt-PT-010A-CTLFireability-2024-03
FORMULA_NAME ShieldRVt-PT-010A-CTLFireability-2024-04
FORMULA_NAME ShieldRVt-PT-010A-CTLFireability-2024-05
FORMULA_NAME ShieldRVt-PT-010A-CTLFireability-2024-06
FORMULA_NAME ShieldRVt-PT-010A-CTLFireability-2024-07
FORMULA_NAME ShieldRVt-PT-010A-CTLFireability-2024-08
FORMULA_NAME ShieldRVt-PT-010A-CTLFireability-2024-09
FORMULA_NAME ShieldRVt-PT-010A-CTLFireability-2024-10
FORMULA_NAME ShieldRVt-PT-010A-CTLFireability-2024-11
FORMULA_NAME ShieldRVt-PT-010A-CTLFireability-2023-12
FORMULA_NAME ShieldRVt-PT-010A-CTLFireability-2023-13
FORMULA_NAME ShieldRVt-PT-010A-CTLFireability-2023-14
FORMULA_NAME ShieldRVt-PT-010A-CTLFireability-2023-15

=== Now, execution of the tool begins

BK_START 1717275699147

Invoking MCC driver with
BK_TOOL=ltsminxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=ShieldRVt-PT-010A
BK_MEMORY_CONFINEMENT=16384
Applying reductions before tool ltsmin
Invoking reducer
Running Version 202405141337
[2024-06-01 21:01:40] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2024-06-01 21:01:40] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2024-06-01 21:01:40] [INFO ] Load time of PNML (sax parser for PT used): 53 ms
[2024-06-01 21:01:40] [INFO ] Transformed 83 places.
[2024-06-01 21:01:40] [INFO ] Transformed 83 transitions.
[2024-06-01 21:01:40] [INFO ] Found NUPN structural information;
[2024-06-01 21:01:40] [INFO ] Parsed PT model containing 83 places and 83 transitions and 346 arcs in 152 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 12 ms.
Initial state reduction rules removed 1 formulas.
Ensure Unique test removed 1 transitions
Reduce redundant transitions removed 1 transitions.
FORMULA ShieldRVt-PT-010A-CTLFireability-2023-14 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 72 out of 83 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 83/83 places, 82/82 transitions.
Applied a total of 0 rules in 9 ms. Remains 83 /83 variables (removed 0) and now considering 82/82 (removed 0) transitions.
// Phase 1: matrix 82 rows 83 cols
[2024-06-01 21:01:40] [INFO ] Computed 41 invariants in 5 ms
[2024-06-01 21:01:40] [INFO ] Implicit Places using invariants in 185 ms returned []
[2024-06-01 21:01:40] [INFO ] Invariant cache hit.
[2024-06-01 21:01:40] [INFO ] Implicit Places using invariants and state equation in 99 ms returned []
Implicit Place search using SMT with State Equation took 313 ms to find 0 implicit places.
Running 81 sub problems to find dead transitions.
[2024-06-01 21:01:40] [INFO ] Invariant cache hit.
At refinement iteration 0 (INCLUDED_ONLY) 0/82 variables, 82/82 constraints. Problems are: Problem set: 0 solved, 81 unsolved
At refinement iteration 1 (INCLUDED_ONLY) 0/82 variables, 0/82 constraints. Problems are: Problem set: 0 solved, 81 unsolved
At refinement iteration 2 (OVERLAPS) 1/83 variables, 41/123 constraints. Problems are: Problem set: 0 solved, 81 unsolved
At refinement iteration 3 (INCLUDED_ONLY) 0/83 variables, 1/124 constraints. Problems are: Problem set: 0 solved, 81 unsolved
At refinement iteration 4 (INCLUDED_ONLY) 0/83 variables, 0/124 constraints. Problems are: Problem set: 0 solved, 81 unsolved
At refinement iteration 5 (OVERLAPS) 82/165 variables, 83/207 constraints. Problems are: Problem set: 0 solved, 81 unsolved
At refinement iteration 6 (INCLUDED_ONLY) 0/165 variables, 0/207 constraints. Problems are: Problem set: 0 solved, 81 unsolved
At refinement iteration 7 (OVERLAPS) 0/165 variables, 0/207 constraints. Problems are: Problem set: 0 solved, 81 unsolved
No progress, stopping.
After SMT solving in domain Real declared 165/165 variables, and 207 constraints, problems are : Problem set: 0 solved, 81 unsolved in 1461 ms.
Refiners :[Domain max(s): 83/83 constraints, Positive P Invariants (semi-flows): 41/41 constraints, State Equation: 83/83 constraints, PredecessorRefiner: 81/81 constraints, Known Traps: 0/0 constraints]
Escalating to Integer solving :Problem set: 0 solved, 81 unsolved
At refinement iteration 0 (INCLUDED_ONLY) 0/82 variables, 82/82 constraints. Problems are: Problem set: 0 solved, 81 unsolved
At refinement iteration 1 (INCLUDED_ONLY) 0/82 variables, 0/82 constraints. Problems are: Problem set: 0 solved, 81 unsolved
At refinement iteration 2 (OVERLAPS) 1/83 variables, 41/123 constraints. Problems are: Problem set: 0 solved, 81 unsolved
At refinement iteration 3 (INCLUDED_ONLY) 0/83 variables, 1/124 constraints. Problems are: Problem set: 0 solved, 81 unsolved
At refinement iteration 4 (INCLUDED_ONLY) 0/83 variables, 0/124 constraints. Problems are: Problem set: 0 solved, 81 unsolved
At refinement iteration 5 (OVERLAPS) 82/165 variables, 83/207 constraints. Problems are: Problem set: 0 solved, 81 unsolved
At refinement iteration 6 (INCLUDED_ONLY) 0/165 variables, 81/288 constraints. Problems are: Problem set: 0 solved, 81 unsolved
At refinement iteration 7 (INCLUDED_ONLY) 0/165 variables, 0/288 constraints. Problems are: Problem set: 0 solved, 81 unsolved
At refinement iteration 8 (OVERLAPS) 0/165 variables, 0/288 constraints. Problems are: Problem set: 0 solved, 81 unsolved
No progress, stopping.
After SMT solving in domain Int declared 165/165 variables, and 288 constraints, problems are : Problem set: 0 solved, 81 unsolved in 1390 ms.
Refiners :[Domain max(s): 83/83 constraints, Positive P Invariants (semi-flows): 41/41 constraints, State Equation: 83/83 constraints, PredecessorRefiner: 81/81 constraints, Known Traps: 0/0 constraints]
After SMT, in 2901ms problems are : Problem set: 0 solved, 81 unsolved
Search for dead transitions found 0 dead transitions in 2918ms
Finished structural reductions in LTL mode , in 1 iterations and 3264 ms. Remains : 83/83 places, 82/82 transitions.
Support contains 72 out of 83 places after structural reductions.
[2024-06-01 21:01:43] [INFO ] Flatten gal took : 48 ms
[2024-06-01 21:01:43] [INFO ] Flatten gal took : 11 ms
[2024-06-01 21:01:44] [INFO ] Input system was already deterministic with 82 transitions.
Reduction of identical properties reduced properties to check from 57 to 52
RANDOM walk for 40000 steps (8 resets) in 1528 ms. (26 steps per ms) remains 3/52 properties
BEST_FIRST walk for 40003 steps (8 resets) in 193 ms. (206 steps per ms) remains 3/3 properties
BEST_FIRST walk for 40003 steps (8 resets) in 102 ms. (388 steps per ms) remains 3/3 properties
BEST_FIRST walk for 40004 steps (8 resets) in 134 ms. (296 steps per ms) remains 3/3 properties
[2024-06-01 21:01:44] [INFO ] Invariant cache hit.
At refinement iteration 0 (INCLUDED_ONLY) 0/16 variables, 16/16 constraints. Problems are: Problem set: 0 solved, 3 unsolved
Problem AtomicPropp32 is UNSAT
Problem AtomicPropp53 is UNSAT
At refinement iteration 1 (INCLUDED_ONLY) 0/16 variables, 2/18 constraints. Problems are: Problem set: 2 solved, 1 unsolved
At refinement iteration 2 (INCLUDED_ONLY) 0/16 variables, 0/18 constraints. Problems are: Problem set: 2 solved, 1 unsolved
At refinement iteration 3 (OVERLAPS) 67/83 variables, 39/57 constraints. Problems are: Problem set: 2 solved, 1 unsolved
At refinement iteration 4 (INCLUDED_ONLY) 0/83 variables, 67/124 constraints. Problems are: Problem set: 2 solved, 1 unsolved
At refinement iteration 5 (INCLUDED_ONLY) 0/83 variables, 0/124 constraints. Problems are: Problem set: 2 solved, 1 unsolved
All remaining problems are real, not stopping.
At refinement iteration 6 (OVERLAPS) 82/165 variables, 83/207 constraints. Problems are: Problem set: 2 solved, 1 unsolved
At refinement iteration 7 (INCLUDED_ONLY) 0/165 variables, 0/207 constraints. Problems are: Problem set: 2 solved, 1 unsolved
At refinement iteration 8 (OVERLAPS) 0/165 variables, 0/207 constraints. Problems are: Problem set: 2 solved, 1 unsolved
No progress, stopping.
After SMT solving in domain Real declared 165/165 variables, and 207 constraints, problems are : Problem set: 2 solved, 1 unsolved in 63 ms.
Refiners :[Domain max(s): 83/83 constraints, Positive P Invariants (semi-flows): 41/41 constraints, State Equation: 83/83 constraints, PredecessorRefiner: 3/3 constraints, Known Traps: 0/0 constraints]
Escalating to Integer solving :Problem set: 2 solved, 1 unsolved
At refinement iteration 0 (INCLUDED_ONLY) 0/5 variables, 5/5 constraints. Problems are: Problem set: 2 solved, 1 unsolved
At refinement iteration 1 (INCLUDED_ONLY) 0/5 variables, 0/5 constraints. Problems are: Problem set: 2 solved, 1 unsolved
At refinement iteration 2 (OVERLAPS) 6/11 variables, 5/10 constraints. Problems are: Problem set: 2 solved, 1 unsolved
At refinement iteration 3 (INCLUDED_ONLY) 0/11 variables, 6/16 constraints. Problems are: Problem set: 2 solved, 1 unsolved
At refinement iteration 4 (INCLUDED_ONLY) 0/11 variables, 0/16 constraints. Problems are: Problem set: 2 solved, 1 unsolved
At refinement iteration 5 (OVERLAPS) 72/83 variables, 36/52 constraints. Problems are: Problem set: 2 solved, 1 unsolved
At refinement iteration 6 (INCLUDED_ONLY) 0/83 variables, 72/124 constraints. Problems are: Problem set: 2 solved, 1 unsolved
At refinement iteration 7 (INCLUDED_ONLY) 0/83 variables, 0/124 constraints. Problems are: Problem set: 2 solved, 1 unsolved
At refinement iteration 8 (OVERLAPS) 82/165 variables, 83/207 constraints. Problems are: Problem set: 2 solved, 1 unsolved
At refinement iteration 9 (INCLUDED_ONLY) 0/165 variables, 1/208 constraints. Problems are: Problem set: 2 solved, 1 unsolved
At refinement iteration 10 (INCLUDED_ONLY) 0/165 variables, 0/208 constraints. Problems are: Problem set: 2 solved, 1 unsolved
At refinement iteration 11 (OVERLAPS) 0/165 variables, 0/208 constraints. Problems are: Problem set: 2 solved, 1 unsolved
No progress, stopping.
After SMT solving in domain Int declared 165/165 variables, and 208 constraints, problems are : Problem set: 2 solved, 1 unsolved in 87 ms.
Refiners :[Domain max(s): 83/83 constraints, Positive P Invariants (semi-flows): 41/41 constraints, State Equation: 83/83 constraints, PredecessorRefiner: 1/3 constraints, Known Traps: 0/0 constraints]
After SMT, in 155ms problems are : Problem set: 2 solved, 1 unsolved
Finished Parikh walk after 42 steps, including 0 resets, run visited all 1 properties in 2 ms. (steps per millisecond=21 )
Parikh walk visited 1 properties in 7 ms.
Successfully simplified 2 atomic propositions for a total of 15 simplifications.
[2024-06-01 21:01:44] [INFO ] Flatten gal took : 8 ms
[2024-06-01 21:01:44] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
FORMULA ShieldRVt-PT-010A-CTLFireability-2023-15 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2024-06-01 21:01:44] [INFO ] Flatten gal took : 7 ms
[2024-06-01 21:01:44] [INFO ] Input system was already deterministic with 82 transitions.
Support contains 66 out of 83 places (down from 68) after GAL structural reductions.
Computed a total of 1 stabilizing places and 1 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 83/83 places, 82/82 transitions.
Applied a total of 0 rules in 3 ms. Remains 83 /83 variables (removed 0) and now considering 82/82 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 83/83 places, 82/82 transitions.
[2024-06-01 21:01:44] [INFO ] Flatten gal took : 5 ms
[2024-06-01 21:01:44] [INFO ] Flatten gal took : 6 ms
[2024-06-01 21:01:44] [INFO ] Input system was already deterministic with 82 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 83/83 places, 82/82 transitions.
Reduce places removed 1 places and 1 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 0 with 3 rules applied. Total rules applied 3 place count 80 transition count 80
Applied a total of 3 rules in 18 ms. Remains 80 /83 variables (removed 3) and now considering 80/82 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 18 ms. Remains : 80/83 places, 80/82 transitions.
[2024-06-01 21:01:44] [INFO ] Flatten gal took : 4 ms
[2024-06-01 21:01:44] [INFO ] Flatten gal took : 5 ms
[2024-06-01 21:01:44] [INFO ] Input system was already deterministic with 80 transitions.
Starting structural reductions in LTL mode, iteration 0 : 83/83 places, 82/82 transitions.
Applied a total of 0 rules in 2 ms. Remains 83 /83 variables (removed 0) and now considering 82/82 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 83/83 places, 82/82 transitions.
[2024-06-01 21:01:45] [INFO ] Flatten gal took : 6 ms
[2024-06-01 21:01:45] [INFO ] Flatten gal took : 6 ms
[2024-06-01 21:01:45] [INFO ] Input system was already deterministic with 82 transitions.
Starting structural reductions in LTL mode, iteration 0 : 83/83 places, 82/82 transitions.
Applied a total of 0 rules in 2 ms. Remains 83 /83 variables (removed 0) and now considering 82/82 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 83/83 places, 82/82 transitions.
[2024-06-01 21:01:45] [INFO ] Flatten gal took : 6 ms
[2024-06-01 21:01:45] [INFO ] Flatten gal took : 6 ms
[2024-06-01 21:01:45] [INFO ] Input system was already deterministic with 82 transitions.
Starting structural reductions in LTL mode, iteration 0 : 83/83 places, 82/82 transitions.
Applied a total of 0 rules in 2 ms. Remains 83 /83 variables (removed 0) and now considering 82/82 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 83/83 places, 82/82 transitions.
[2024-06-01 21:01:45] [INFO ] Flatten gal took : 6 ms
[2024-06-01 21:01:45] [INFO ] Flatten gal took : 6 ms
[2024-06-01 21:01:45] [INFO ] Input system was already deterministic with 82 transitions.
Starting structural reductions in LTL mode, iteration 0 : 83/83 places, 82/82 transitions.
Applied a total of 0 rules in 3 ms. Remains 83 /83 variables (removed 0) and now considering 82/82 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 83/83 places, 82/82 transitions.
[2024-06-01 21:01:45] [INFO ] Flatten gal took : 5 ms
[2024-06-01 21:01:45] [INFO ] Flatten gal took : 5 ms
[2024-06-01 21:01:45] [INFO ] Input system was already deterministic with 82 transitions.
Starting structural reductions in LTL mode, iteration 0 : 83/83 places, 82/82 transitions.
Applied a total of 0 rules in 2 ms. Remains 83 /83 variables (removed 0) and now considering 82/82 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 83/83 places, 82/82 transitions.
[2024-06-01 21:01:45] [INFO ] Flatten gal took : 6 ms
[2024-06-01 21:01:45] [INFO ] Flatten gal took : 8 ms
[2024-06-01 21:01:45] [INFO ] Input system was already deterministic with 82 transitions.
Starting structural reductions in LTL mode, iteration 0 : 83/83 places, 82/82 transitions.
Applied a total of 0 rules in 3 ms. Remains 83 /83 variables (removed 0) and now considering 82/82 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 83/83 places, 82/82 transitions.
[2024-06-01 21:01:45] [INFO ] Flatten gal took : 5 ms
[2024-06-01 21:01:45] [INFO ] Flatten gal took : 5 ms
[2024-06-01 21:01:45] [INFO ] Input system was already deterministic with 82 transitions.
Starting structural reductions in LTL mode, iteration 0 : 83/83 places, 82/82 transitions.
Applied a total of 0 rules in 2 ms. Remains 83 /83 variables (removed 0) and now considering 82/82 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 83/83 places, 82/82 transitions.
[2024-06-01 21:01:45] [INFO ] Flatten gal took : 5 ms
[2024-06-01 21:01:45] [INFO ] Flatten gal took : 5 ms
[2024-06-01 21:01:45] [INFO ] Input system was already deterministic with 82 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 83/83 places, 82/82 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 0 with 2 rules applied. Total rules applied 2 place count 82 transition count 81
Applied a total of 2 rules in 7 ms. Remains 82 /83 variables (removed 1) and now considering 81/82 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 7 ms. Remains : 82/83 places, 81/82 transitions.
[2024-06-01 21:01:45] [INFO ] Flatten gal took : 5 ms
[2024-06-01 21:01:45] [INFO ] Flatten gal took : 5 ms
[2024-06-01 21:01:45] [INFO ] Input system was already deterministic with 81 transitions.
Starting structural reductions in LTL mode, iteration 0 : 83/83 places, 82/82 transitions.
Applied a total of 0 rules in 2 ms. Remains 83 /83 variables (removed 0) and now considering 82/82 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 83/83 places, 82/82 transitions.
[2024-06-01 21:01:45] [INFO ] Flatten gal took : 4 ms
[2024-06-01 21:01:45] [INFO ] Flatten gal took : 5 ms
[2024-06-01 21:01:45] [INFO ] Input system was already deterministic with 82 transitions.
Starting structural reductions in LTL mode, iteration 0 : 83/83 places, 82/82 transitions.
Applied a total of 0 rules in 1 ms. Remains 83 /83 variables (removed 0) and now considering 82/82 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 83/83 places, 82/82 transitions.
[2024-06-01 21:01:45] [INFO ] Flatten gal took : 4 ms
[2024-06-01 21:01:45] [INFO ] Flatten gal took : 5 ms
[2024-06-01 21:01:45] [INFO ] Input system was already deterministic with 82 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 83/83 places, 82/82 transitions.
Reduce places removed 1 places and 1 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 0 with 3 rules applied. Total rules applied 3 place count 80 transition count 80
Applied a total of 3 rules in 5 ms. Remains 80 /83 variables (removed 3) and now considering 80/82 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 6 ms. Remains : 80/83 places, 80/82 transitions.
[2024-06-01 21:01:45] [INFO ] Flatten gal took : 3 ms
[2024-06-01 21:01:45] [INFO ] Flatten gal took : 5 ms
[2024-06-01 21:01:45] [INFO ] Input system was already deterministic with 80 transitions.
RANDOM walk for 4 steps (0 resets) in 6 ms. (0 steps per ms) remains 0/1 properties
FORMULA ShieldRVt-PT-010A-CTLFireability-2023-12 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in SI_CTL mode, iteration 0 : 83/83 places, 82/82 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 0 with 2 rules applied. Total rules applied 2 place count 82 transition count 81
Applied a total of 2 rules in 5 ms. Remains 82 /83 variables (removed 1) and now considering 81/82 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 5 ms. Remains : 82/83 places, 81/82 transitions.
[2024-06-01 21:01:45] [INFO ] Flatten gal took : 4 ms
[2024-06-01 21:01:45] [INFO ] Flatten gal took : 4 ms
[2024-06-01 21:01:45] [INFO ] Input system was already deterministic with 81 transitions.
RANDOM walk for 6850 steps (1 resets) in 56 ms. (120 steps per ms) remains 0/1 properties
FORMULA ShieldRVt-PT-010A-CTLFireability-2023-13 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
[2024-06-01 21:01:45] [INFO ] Flatten gal took : 6 ms
[2024-06-01 21:01:45] [INFO ] Flatten gal took : 5 ms
[2024-06-01 21:01:45] [INFO ] Export to MCC of 12 properties in file /home/mcc/execution/CTLFireability.sr.xml took 3 ms.
[2024-06-01 21:01:45] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 83 places, 82 transitions and 344 arcs took 2 ms.
Total runtime 5101 ms.
There are residual formulas that ITS could not solve within timeout
Usage: pnml2lts-sym [-gvqh] [--order=]
[--mu-opt] [--saturation=]
[--sat-granularity=] [--save-sat-levels]
[--guidance=] [-d|--deadlock]
[--action=] [-i|--invariant=STRING] [-n|--no-exit]
[--trace=] [--type=]
[--mu=.mu] [--ctl-star=.ctl]
[--ctl=.ctl] [--ltl=.ltl] [--dot=STRING]
[--save-levels=STRING] [--pg-solve] [--attr=]
[--saturating-attractor] [--write-strategy=.spg]
[--check-strategy] [--interactive-play] [--player]
[--pg-write=.spg] [--no-matrix] [--noack=<1|2>]
[--edge-label=] [--labels] [-m|--matrix]
[--mucalc=.mcf|] [-c|--cache]
[--allow-undefined-edges] [--allow-undefined-values]
[-p|--por= (default: heur)]
[--weak=[valmari] (default: uses stronger left-commutativity)]
[--leap] [-r|--regroup=<(T,)+>] [--sloan-w1=] [--sloan-w2=]
[--cw-max-cols=] [--cw-max-rows=] [--col-ins=<(C.C',)+>]
[--mh-timeout=] [--row-perm=<(R,)+>] [--col-perm=<(C,)+>]
[--graph-metrics] [--regroup-exit] [--regroup-time]
[-g|--pins-guards] [--vset=] [--ldd32-step=]
[--ldd32-cache=] [--ldd-step=] [--ldd-cache=]
[--cache-ratio=] [--max-increase=]
[--min-free-nodes=] [--fdd-bits=]
[--fdd-reorder=]
[--vset-cache-diff=] [--no-soundness-check] [--precise]
[--next-union] [--peak-nodes] [--maxsum=]
[--block-size=] [--cluster-size=] [-v] [-q]
[--debug=] [--stats] [--where] [--when]
[--timeout=INT] [--version] [-h|--help] [--usage]
[OPTIONS] []
Could not compute solution for formula : ShieldRVt-PT-010A-CTLFireability-2024-00
Could not compute solution for formula : ShieldRVt-PT-010A-CTLFireability-2024-01
Could not compute solution for formula : ShieldRVt-PT-010A-CTLFireability-2024-02
Could not compute solution for formula : ShieldRVt-PT-010A-CTLFireability-2024-03
Could not compute solution for formula : ShieldRVt-PT-010A-CTLFireability-2024-04
Could not compute solution for formula : ShieldRVt-PT-010A-CTLFireability-2024-05
Could not compute solution for formula : ShieldRVt-PT-010A-CTLFireability-2024-06
Could not compute solution for formula : ShieldRVt-PT-010A-CTLFireability-2024-07
Could not compute solution for formula : ShieldRVt-PT-010A-CTLFireability-2024-08
Could not compute solution for formula : ShieldRVt-PT-010A-CTLFireability-2024-09
Could not compute solution for formula : ShieldRVt-PT-010A-CTLFireability-2024-10
Could not compute solution for formula : ShieldRVt-PT-010A-CTLFireability-2024-11

BK_STOP 1717275705673

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202405141337.jar
++ perl -pe 's/.*\.//g'
+ VERSION=202405141337
+ echo 'Running Version 202405141337'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
mcc2024
ctl formula name ShieldRVt-PT-010A-CTLFireability-2024-00
ctl formula formula --ctl=/tmp/501/ctl_0_
ctl formula name ShieldRVt-PT-010A-CTLFireability-2024-01
ctl formula formula --ctl=/tmp/501/ctl_1_
ctl formula name ShieldRVt-PT-010A-CTLFireability-2024-02
ctl formula formula --ctl=/tmp/501/ctl_2_
ctl formula name ShieldRVt-PT-010A-CTLFireability-2024-03
ctl formula formula --ctl=/tmp/501/ctl_3_
ctl formula name ShieldRVt-PT-010A-CTLFireability-2024-04
ctl formula formula --ctl=/tmp/501/ctl_4_
ctl formula name ShieldRVt-PT-010A-CTLFireability-2024-05
ctl formula formula --ctl=/tmp/501/ctl_5_
ctl formula name ShieldRVt-PT-010A-CTLFireability-2024-06
ctl formula formula --ctl=/tmp/501/ctl_6_
ctl formula name ShieldRVt-PT-010A-CTLFireability-2024-07
ctl formula formula --ctl=/tmp/501/ctl_7_
ctl formula name ShieldRVt-PT-010A-CTLFireability-2024-08
ctl formula formula --ctl=/tmp/501/ctl_8_
ctl formula name ShieldRVt-PT-010A-CTLFireability-2024-09
ctl formula formula --ctl=/tmp/501/ctl_9_
ctl formula name ShieldRVt-PT-010A-CTLFireability-2024-10
ctl formula formula --ctl=/tmp/501/ctl_10_
ctl formula name ShieldRVt-PT-010A-CTLFireability-2024-11
ctl formula formula --ctl=/tmp/501/ctl_11_
pnml2lts-sym, ** error **: unknown vector set implementation lddmc

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ShieldRVt-PT-010A"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="ltsminxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool ltsminxred"
echo " Input is ShieldRVt-PT-010A, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r528-tall-171683762200962"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/ShieldRVt-PT-010A.tgz
mv ShieldRVt-PT-010A execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;