Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r524-tall-171679081100810.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.....................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool ltsminxred
Input is SharedMemory-PT-000005, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r524-tall-171679081100810
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 784K
-rw-r--r-- 1 mcc users 13K Apr 12 15:17 CTLCardinality.txt
-rw-r--r-- 1 mcc users 94K Apr 12 15:17 CTLCardinality.xml
-rw-r--r-- 1 mcc users 19K Apr 12 15:06 CTLFireability.txt
-rw-r--r-- 1 mcc users 97K Apr 12 15:06 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:43 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K May 18 16:43 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 8.5K Apr 23 07:51 LTLCardinality.txt
-rw-r--r-- 1 mcc users 39K Apr 23 07:51 LTLCardinality.xml
-rw-r--r-- 1 mcc users 11K Apr 23 07:51 LTLFireability.txt
-rw-r--r-- 1 mcc users 42K Apr 23 07:51 LTLFireability.xml
-rw-r--r-- 1 mcc users 22K Apr 12 15:23 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 149K Apr 12 15:23 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 22K Apr 12 15:20 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 119K Apr 12 15:20 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.7K Apr 23 07:51 UpperBounds.txt
-rw-r--r-- 1 mcc users 6.0K Apr 23 07:51 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 7 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 83K May 18 16:43 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME SharedMemory-PT-000005-CTLFireability-2024-00
FORMULA_NAME SharedMemory-PT-000005-CTLFireability-2024-01
FORMULA_NAME SharedMemory-PT-000005-CTLFireability-2024-02
FORMULA_NAME SharedMemory-PT-000005-CTLFireability-2024-03
FORMULA_NAME SharedMemory-PT-000005-CTLFireability-2024-04
FORMULA_NAME SharedMemory-PT-000005-CTLFireability-2024-05
FORMULA_NAME SharedMemory-PT-000005-CTLFireability-2024-06
FORMULA_NAME SharedMemory-PT-000005-CTLFireability-2024-07
FORMULA_NAME SharedMemory-PT-000005-CTLFireability-2024-08
FORMULA_NAME SharedMemory-PT-000005-CTLFireability-2024-09
FORMULA_NAME SharedMemory-PT-000005-CTLFireability-2024-10
FORMULA_NAME SharedMemory-PT-000005-CTLFireability-2024-11
FORMULA_NAME SharedMemory-PT-000005-CTLFireability-2024-12
FORMULA_NAME SharedMemory-PT-000005-CTLFireability-2024-13
FORMULA_NAME SharedMemory-PT-000005-CTLFireability-2024-14
FORMULA_NAME SharedMemory-PT-000005-CTLFireability-2024-15

=== Now, execution of the tool begins

BK_START 1717239416131

Invoking MCC driver with
BK_TOOL=ltsminxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=SharedMemory-PT-000005
BK_MEMORY_CONFINEMENT=16384
Applying reductions before tool ltsmin
Invoking reducer
Running Version 202405141337
[2024-06-01 10:56:57] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2024-06-01 10:56:57] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2024-06-01 10:56:57] [INFO ] Load time of PNML (sax parser for PT used): 65 ms
[2024-06-01 10:56:57] [INFO ] Transformed 41 places.
[2024-06-01 10:56:57] [INFO ] Transformed 55 transitions.
[2024-06-01 10:56:57] [INFO ] Found NUPN structural information;
[2024-06-01 10:56:57] [INFO ] Parsed PT model containing 41 places and 55 transitions and 200 arcs in 164 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 17 ms.
Initial state reduction rules removed 3 formulas.
FORMULA SharedMemory-PT-000005-CTLFireability-2024-02 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA SharedMemory-PT-000005-CTLFireability-2024-07 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA SharedMemory-PT-000005-CTLFireability-2024-09 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 41 out of 41 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 41/41 places, 55/55 transitions.
Applied a total of 0 rules in 9 ms. Remains 41 /41 variables (removed 0) and now considering 55/55 (removed 0) transitions.
// Phase 1: matrix 55 rows 41 cols
[2024-06-01 10:56:57] [INFO ] Computed 11 invariants in 7 ms
[2024-06-01 10:56:57] [INFO ] Implicit Places using invariants in 175 ms returned []
[2024-06-01 10:56:57] [INFO ] Invariant cache hit.
[2024-06-01 10:56:57] [INFO ] Implicit Places using invariants and state equation in 71 ms returned []
Implicit Place search using SMT with State Equation took 280 ms to find 0 implicit places.
Running 45 sub problems to find dead transitions.
[2024-06-01 10:56:57] [INFO ] Invariant cache hit.
At refinement iteration 0 (INCLUDED_ONLY) 0/36 variables, 36/36 constraints. Problems are: Problem set: 0 solved, 45 unsolved
At refinement iteration 1 (INCLUDED_ONLY) 0/36 variables, 6/42 constraints. Problems are: Problem set: 0 solved, 45 unsolved
At refinement iteration 2 (INCLUDED_ONLY) 0/36 variables, 0/42 constraints. Problems are: Problem set: 0 solved, 45 unsolved
At refinement iteration 3 (OVERLAPS) 5/41 variables, 5/47 constraints. Problems are: Problem set: 0 solved, 45 unsolved
At refinement iteration 4 (INCLUDED_ONLY) 0/41 variables, 5/52 constraints. Problems are: Problem set: 0 solved, 45 unsolved
At refinement iteration 5 (INCLUDED_ONLY) 0/41 variables, 0/52 constraints. Problems are: Problem set: 0 solved, 45 unsolved
At refinement iteration 6 (OVERLAPS) 55/96 variables, 41/93 constraints. Problems are: Problem set: 0 solved, 45 unsolved
At refinement iteration 7 (INCLUDED_ONLY) 0/96 variables, 0/93 constraints. Problems are: Problem set: 0 solved, 45 unsolved
At refinement iteration 8 (OVERLAPS) 0/96 variables, 0/93 constraints. Problems are: Problem set: 0 solved, 45 unsolved
No progress, stopping.
After SMT solving in domain Real declared 96/96 variables, and 93 constraints, problems are : Problem set: 0 solved, 45 unsolved in 640 ms.
Refiners :[Domain max(s): 41/41 constraints, Positive P Invariants (semi-flows): 11/11 constraints, State Equation: 41/41 constraints, PredecessorRefiner: 45/45 constraints, Known Traps: 0/0 constraints]
Escalating to Integer solving :Problem set: 0 solved, 45 unsolved
At refinement iteration 0 (INCLUDED_ONLY) 0/36 variables, 36/36 constraints. Problems are: Problem set: 0 solved, 45 unsolved
At refinement iteration 1 (INCLUDED_ONLY) 0/36 variables, 6/42 constraints. Problems are: Problem set: 0 solved, 45 unsolved
At refinement iteration 2 (INCLUDED_ONLY) 0/36 variables, 0/42 constraints. Problems are: Problem set: 0 solved, 45 unsolved
At refinement iteration 3 (OVERLAPS) 5/41 variables, 5/47 constraints. Problems are: Problem set: 0 solved, 45 unsolved
At refinement iteration 4 (INCLUDED_ONLY) 0/41 variables, 5/52 constraints. Problems are: Problem set: 0 solved, 45 unsolved
At refinement iteration 5 (INCLUDED_ONLY) 0/41 variables, 0/52 constraints. Problems are: Problem set: 0 solved, 45 unsolved
At refinement iteration 6 (OVERLAPS) 55/96 variables, 41/93 constraints. Problems are: Problem set: 0 solved, 45 unsolved
At refinement iteration 7 (INCLUDED_ONLY) 0/96 variables, 45/138 constraints. Problems are: Problem set: 0 solved, 45 unsolved
At refinement iteration 8 (INCLUDED_ONLY) 0/96 variables, 0/138 constraints. Problems are: Problem set: 0 solved, 45 unsolved
At refinement iteration 9 (OVERLAPS) 0/96 variables, 0/138 constraints. Problems are: Problem set: 0 solved, 45 unsolved
No progress, stopping.
After SMT solving in domain Int declared 96/96 variables, and 138 constraints, problems are : Problem set: 0 solved, 45 unsolved in 572 ms.
Refiners :[Domain max(s): 41/41 constraints, Positive P Invariants (semi-flows): 11/11 constraints, State Equation: 41/41 constraints, PredecessorRefiner: 45/45 constraints, Known Traps: 0/0 constraints]
After SMT, in 1286ms problems are : Problem set: 0 solved, 45 unsolved
Search for dead transitions found 0 dead transitions in 1300ms
Finished structural reductions in LTL mode , in 1 iterations and 1608 ms. Remains : 41/41 places, 55/55 transitions.
Support contains 41 out of 41 places after structural reductions.
[2024-06-01 10:56:59] [INFO ] Flatten gal took : 28 ms
[2024-06-01 10:56:59] [INFO ] Flatten gal took : 14 ms
[2024-06-01 10:56:59] [INFO ] Input system was already deterministic with 55 transitions.
Reduction of identical properties reduced properties to check from 43 to 35
RANDOM walk for 40000 steps (8 resets) in 1221 ms. (32 steps per ms) remains 2/35 properties
BEST_FIRST walk for 40004 steps (8 resets) in 403 ms. (99 steps per ms) remains 2/2 properties
BEST_FIRST walk for 40004 steps (8 resets) in 100 ms. (396 steps per ms) remains 2/2 properties
[2024-06-01 10:57:00] [INFO ] Invariant cache hit.
Problem AtomicPropp5 is UNSAT
At refinement iteration 0 (INCLUDED_ONLY) 0/28 variables, 28/28 constraints. Problems are: Problem set: 1 solved, 1 unsolved
At refinement iteration 1 (INCLUDED_ONLY) 0/28 variables, 2/30 constraints. Problems are: Problem set: 1 solved, 1 unsolved
At refinement iteration 2 (INCLUDED_ONLY) 0/28 variables, 0/30 constraints. Problems are: Problem set: 1 solved, 1 unsolved
Problem AtomicPropp35 is UNSAT
After SMT solving in domain Real declared 41/96 variables, and 39 constraints, problems are : Problem set: 2 solved, 0 unsolved in 30 ms.
Refiners :[Domain max(s): 28/41 constraints, Positive P Invariants (semi-flows): 11/11 constraints, State Equation: 0/41 constraints, PredecessorRefiner: 2/2 constraints, Known Traps: 0/0 constraints]
After SMT, in 38ms problems are : Problem set: 2 solved, 0 unsolved
Skipping Parikh replay, no witness traces provided.
Successfully simplified 2 atomic propositions for a total of 13 simplifications.
[2024-06-01 10:57:00] [INFO ] Flatten gal took : 7 ms
[2024-06-01 10:57:00] [INFO ] Flatten gal took : 11 ms
[2024-06-01 10:57:00] [INFO ] Input system was already deterministic with 55 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 41/41 places, 55/55 transitions.
Applied a total of 0 rules in 1 ms. Remains 41 /41 variables (removed 0) and now considering 55/55 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 41/41 places, 55/55 transitions.
[2024-06-01 10:57:00] [INFO ] Flatten gal took : 5 ms
[2024-06-01 10:57:00] [INFO ] Flatten gal took : 5 ms
[2024-06-01 10:57:00] [INFO ] Input system was already deterministic with 55 transitions.
Starting structural reductions in LTL mode, iteration 0 : 41/41 places, 55/55 transitions.
Applied a total of 0 rules in 0 ms. Remains 41 /41 variables (removed 0) and now considering 55/55 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 41/41 places, 55/55 transitions.
[2024-06-01 10:57:00] [INFO ] Flatten gal took : 4 ms
[2024-06-01 10:57:00] [INFO ] Flatten gal took : 5 ms
[2024-06-01 10:57:00] [INFO ] Input system was already deterministic with 55 transitions.
Starting structural reductions in LTL mode, iteration 0 : 41/41 places, 55/55 transitions.
Applied a total of 0 rules in 1 ms. Remains 41 /41 variables (removed 0) and now considering 55/55 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 41/41 places, 55/55 transitions.
[2024-06-01 10:57:00] [INFO ] Flatten gal took : 4 ms
[2024-06-01 10:57:00] [INFO ] Flatten gal took : 6 ms
[2024-06-01 10:57:00] [INFO ] Input system was already deterministic with 55 transitions.
Starting structural reductions in LTL mode, iteration 0 : 41/41 places, 55/55 transitions.
Applied a total of 0 rules in 0 ms. Remains 41 /41 variables (removed 0) and now considering 55/55 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 41/41 places, 55/55 transitions.
[2024-06-01 10:57:00] [INFO ] Flatten gal took : 3 ms
[2024-06-01 10:57:00] [INFO ] Flatten gal took : 4 ms
[2024-06-01 10:57:00] [INFO ] Input system was already deterministic with 55 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 41/41 places, 55/55 transitions.
Applied a total of 0 rules in 5 ms. Remains 41 /41 variables (removed 0) and now considering 55/55 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 6 ms. Remains : 41/41 places, 55/55 transitions.
[2024-06-01 10:57:00] [INFO ] Flatten gal took : 3 ms
[2024-06-01 10:57:00] [INFO ] Flatten gal took : 4 ms
[2024-06-01 10:57:00] [INFO ] Input system was already deterministic with 55 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 41/41 places, 55/55 transitions.
Applied a total of 0 rules in 1 ms. Remains 41 /41 variables (removed 0) and now considering 55/55 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 3 ms. Remains : 41/41 places, 55/55 transitions.
[2024-06-01 10:57:00] [INFO ] Flatten gal took : 4 ms
[2024-06-01 10:57:00] [INFO ] Flatten gal took : 4 ms
[2024-06-01 10:57:00] [INFO ] Input system was already deterministic with 55 transitions.
Starting structural reductions in LTL mode, iteration 0 : 41/41 places, 55/55 transitions.
Applied a total of 0 rules in 1 ms. Remains 41 /41 variables (removed 0) and now considering 55/55 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 41/41 places, 55/55 transitions.
[2024-06-01 10:57:00] [INFO ] Flatten gal took : 4 ms
[2024-06-01 10:57:00] [INFO ] Flatten gal took : 4 ms
[2024-06-01 10:57:00] [INFO ] Input system was already deterministic with 55 transitions.
Starting structural reductions in LTL mode, iteration 0 : 41/41 places, 55/55 transitions.
Applied a total of 0 rules in 1 ms. Remains 41 /41 variables (removed 0) and now considering 55/55 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 41/41 places, 55/55 transitions.
[2024-06-01 10:57:00] [INFO ] Flatten gal took : 4 ms
[2024-06-01 10:57:00] [INFO ] Flatten gal took : 4 ms
[2024-06-01 10:57:00] [INFO ] Input system was already deterministic with 55 transitions.
Starting structural reductions in LTL mode, iteration 0 : 41/41 places, 55/55 transitions.
Applied a total of 0 rules in 1 ms. Remains 41 /41 variables (removed 0) and now considering 55/55 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 41/41 places, 55/55 transitions.
[2024-06-01 10:57:00] [INFO ] Flatten gal took : 3 ms
[2024-06-01 10:57:00] [INFO ] Flatten gal took : 4 ms
[2024-06-01 10:57:00] [INFO ] Input system was already deterministic with 55 transitions.
Starting structural reductions in LTL mode, iteration 0 : 41/41 places, 55/55 transitions.
Applied a total of 0 rules in 1 ms. Remains 41 /41 variables (removed 0) and now considering 55/55 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 41/41 places, 55/55 transitions.
[2024-06-01 10:57:00] [INFO ] Flatten gal took : 3 ms
[2024-06-01 10:57:00] [INFO ] Flatten gal took : 4 ms
[2024-06-01 10:57:00] [INFO ] Input system was already deterministic with 55 transitions.
Starting structural reductions in LTL mode, iteration 0 : 41/41 places, 55/55 transitions.
Applied a total of 0 rules in 1 ms. Remains 41 /41 variables (removed 0) and now considering 55/55 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 41/41 places, 55/55 transitions.
[2024-06-01 10:57:00] [INFO ] Flatten gal took : 3 ms
[2024-06-01 10:57:00] [INFO ] Flatten gal took : 4 ms
[2024-06-01 10:57:00] [INFO ] Input system was already deterministic with 55 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 41/41 places, 55/55 transitions.
Drop transitions (Trivial Post-Agglo cleanup.) removed 15 transitions
Trivial Post-agglo rules discarded 15 transitions
Performed 15 trivial Post agglomeration. Transition count delta: 15
Iterating post reduction 0 with 15 rules applied. Total rules applied 15 place count 41 transition count 40
Reduce places removed 16 places and 0 transitions.
Iterating post reduction 1 with 16 rules applied. Total rules applied 31 place count 25 transition count 40
Drop transitions (Redundant composition of simpler transitions.) removed 11 transitions
Redundant transition composition rules discarded 11 transitions
Iterating global reduction 2 with 11 rules applied. Total rules applied 42 place count 25 transition count 29
Applied a total of 42 rules in 12 ms. Remains 25 /41 variables (removed 16) and now considering 29/55 (removed 26) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 13 ms. Remains : 25/41 places, 29/55 transitions.
[2024-06-01 10:57:00] [INFO ] Flatten gal took : 2 ms
[2024-06-01 10:57:00] [INFO ] Flatten gal took : 1 ms
[2024-06-01 10:57:00] [INFO ] Input system was already deterministic with 29 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 41/41 places, 55/55 transitions.
Drop transitions (Trivial Post-Agglo cleanup.) removed 19 transitions
Trivial Post-agglo rules discarded 19 transitions
Performed 19 trivial Post agglomeration. Transition count delta: 19
Iterating post reduction 0 with 19 rules applied. Total rules applied 19 place count 41 transition count 36
Reduce places removed 23 places and 0 transitions.
Ensure Unique test removed 11 transitions
Reduce isomorphic transitions removed 11 transitions.
Graph (trivial) has 14 edges and 18 vertex of which 8 / 18 are part of one of the 4 SCC in 2 ms
Free SCC test removed 4 places
Iterating post reduction 1 with 35 rules applied. Total rules applied 54 place count 14 transition count 25
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 2 with 4 rules applied. Total rules applied 58 place count 14 transition count 21
Drop transitions (Redundant composition of simpler transitions.) removed 3 transitions
Redundant transition composition rules discarded 3 transitions
Iterating global reduction 3 with 3 rules applied. Total rules applied 61 place count 14 transition count 18
Applied a total of 61 rules in 15 ms. Remains 14 /41 variables (removed 27) and now considering 18/55 (removed 37) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 15 ms. Remains : 14/41 places, 18/55 transitions.
[2024-06-01 10:57:00] [INFO ] Flatten gal took : 1 ms
[2024-06-01 10:57:00] [INFO ] Flatten gal took : 1 ms
[2024-06-01 10:57:00] [INFO ] Input system was already deterministic with 18 transitions.
[2024-06-01 10:57:00] [INFO ] Flatten gal took : 7 ms
[2024-06-01 10:57:00] [INFO ] Flatten gal took : 7 ms
[2024-06-01 10:57:00] [INFO ] Export to MCC of 13 properties in file /home/mcc/execution/CTLFireability.sr.xml took 6 ms.
[2024-06-01 10:57:00] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 41 places, 55 transitions and 200 arcs took 3 ms.
Total runtime 3391 ms.
There are residual formulas that ITS could not solve within timeout
Usage: pnml2lts-sym [-gvqh] [--order=]
[--mu-opt] [--saturation=]
[--sat-granularity=] [--save-sat-levels]
[--guidance=] [-d|--deadlock]
[--action=] [-i|--invariant=STRING] [-n|--no-exit]
[--trace=] [--type=]
[--mu=.mu] [--ctl-star=.ctl]
[--ctl=.ctl] [--ltl=.ltl] [--dot=STRING]
[--save-levels=STRING] [--pg-solve] [--attr=]
[--saturating-attractor] [--write-strategy=.spg]
[--check-strategy] [--interactive-play] [--player]
[--pg-write=.spg] [--no-matrix] [--noack=<1|2>]
[--edge-label=] [--labels] [-m|--matrix]
[--mucalc=.mcf|] [-c|--cache]
[--allow-undefined-edges] [--allow-undefined-values]
[-p|--por= (default: heur)]
[--weak=[valmari] (default: uses stronger left-commutativity)]
[--leap] [-r|--regroup=<(T,)+>] [--sloan-w1=] [--sloan-w2=]
[--cw-max-cols=] [--cw-max-rows=] [--col-ins=<(C.C',)+>]
[--mh-timeout=] [--row-perm=<(R,)+>] [--col-perm=<(C,)+>]
[--graph-metrics] [--regroup-exit] [--regroup-time]
[-g|--pins-guards] [--vset=] [--ldd32-step=]
[--ldd32-cache=] [--ldd-step=] [--ldd-cache=]
[--cache-ratio=] [--max-increase=]
[--min-free-nodes=] [--fdd-bits=]
[--fdd-reorder=]
[--vset-cache-diff=] [--no-soundness-check] [--precise]
[--next-union] [--peak-nodes] [--maxsum=]
[--block-size=] [--cluster-size=] [-v] [-q]
[--debug=] [--stats] [--where] [--when]
[--timeout=INT] [--version] [-h|--help] [--usage]
[OPTIONS] []
Could not compute solution for formula : SharedMemory-PT-000005-CTLFireability-2024-00
Could not compute solution for formula : SharedMemory-PT-000005-CTLFireability-2024-01
Could not compute solution for formula : SharedMemory-PT-000005-CTLFireability-2024-03
Could not compute solution for formula : SharedMemory-PT-000005-CTLFireability-2024-04
Could not compute solution for formula : SharedMemory-PT-000005-CTLFireability-2024-05
Could not compute solution for formula : SharedMemory-PT-000005-CTLFireability-2024-06
Could not compute solution for formula : SharedMemory-PT-000005-CTLFireability-2024-08
Could not compute solution for formula : SharedMemory-PT-000005-CTLFireability-2024-10
Could not compute solution for formula : SharedMemory-PT-000005-CTLFireability-2024-11
Could not compute solution for formula : SharedMemory-PT-000005-CTLFireability-2024-12
Could not compute solution for formula : SharedMemory-PT-000005-CTLFireability-2024-13
Could not compute solution for formula : SharedMemory-PT-000005-CTLFireability-2024-14
Could not compute solution for formula : SharedMemory-PT-000005-CTLFireability-2024-15

BK_STOP 1717239421205

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202405141337.jar
+ VERSION=202405141337
+ echo 'Running Version 202405141337'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
mcc2024
ctl formula name SharedMemory-PT-000005-CTLFireability-2024-00
ctl formula formula --ctl=/tmp/505/ctl_0_
ctl formula name SharedMemory-PT-000005-CTLFireability-2024-01
ctl formula formula --ctl=/tmp/505/ctl_1_
ctl formula name SharedMemory-PT-000005-CTLFireability-2024-03
ctl formula formula --ctl=/tmp/505/ctl_2_
ctl formula name SharedMemory-PT-000005-CTLFireability-2024-04
ctl formula formula --ctl=/tmp/505/ctl_3_
ctl formula name SharedMemory-PT-000005-CTLFireability-2024-05
ctl formula formula --ctl=/tmp/505/ctl_4_
ctl formula name SharedMemory-PT-000005-CTLFireability-2024-06
ctl formula formula --ctl=/tmp/505/ctl_5_
ctl formula name SharedMemory-PT-000005-CTLFireability-2024-08
ctl formula formula --ctl=/tmp/505/ctl_6_
ctl formula name SharedMemory-PT-000005-CTLFireability-2024-10
ctl formula formula --ctl=/tmp/505/ctl_7_
ctl formula name SharedMemory-PT-000005-CTLFireability-2024-11
ctl formula formula --ctl=/tmp/505/ctl_8_
ctl formula name SharedMemory-PT-000005-CTLFireability-2024-12
ctl formula formula --ctl=/tmp/505/ctl_9_
ctl formula name SharedMemory-PT-000005-CTLFireability-2024-13
ctl formula formula --ctl=/tmp/505/ctl_10_
ctl formula name SharedMemory-PT-000005-CTLFireability-2024-14
ctl formula formula --ctl=/tmp/505/ctl_11_
ctl formula name SharedMemory-PT-000005-CTLFireability-2024-15
ctl formula formula --ctl=/tmp/505/ctl_12_
pnml2lts-sym, ** error **: unknown vector set implementation lddmc

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="SharedMemory-PT-000005"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="ltsminxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool ltsminxred"
echo " Input is SharedMemory-PT-000005, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r524-tall-171679081100810"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/SharedMemory-PT-000005.tgz
mv SharedMemory-PT-000005 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;