Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r524-tall-171679080100330.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...................
=====================================================================
Generated by BenchKit 2-5568
Executing tool ltsminxred
Input is RwMutex-PT-r0500w0010, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r524-tall-171679080100330
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.7M
-rw-r--r-- 1 mcc users 8.2K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 95K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.3K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 34K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:43 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K May 18 16:43 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.9K Apr 23 07:49 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K Apr 23 07:49 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K Apr 23 07:49 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K Apr 23 07:49 LTLFireability.xml
-rw-r--r-- 1 mcc users 15K Apr 13 06:45 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 161K Apr 13 06:45 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 15K Apr 13 06:42 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 136K Apr 13 06:42 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Apr 23 07:49 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Apr 23 07:49 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 11 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 1.1M May 18 16:43 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME RwMutex-PT-r0500w0010-CTLFireability-2024-00
FORMULA_NAME RwMutex-PT-r0500w0010-CTLFireability-2024-01
FORMULA_NAME RwMutex-PT-r0500w0010-CTLFireability-2024-02
FORMULA_NAME RwMutex-PT-r0500w0010-CTLFireability-2024-03
FORMULA_NAME RwMutex-PT-r0500w0010-CTLFireability-2024-04
FORMULA_NAME RwMutex-PT-r0500w0010-CTLFireability-2024-05
FORMULA_NAME RwMutex-PT-r0500w0010-CTLFireability-2024-06
FORMULA_NAME RwMutex-PT-r0500w0010-CTLFireability-2024-07
FORMULA_NAME RwMutex-PT-r0500w0010-CTLFireability-2024-08
FORMULA_NAME RwMutex-PT-r0500w0010-CTLFireability-2024-09
FORMULA_NAME RwMutex-PT-r0500w0010-CTLFireability-2024-10
FORMULA_NAME RwMutex-PT-r0500w0010-CTLFireability-2024-11
FORMULA_NAME RwMutex-PT-r0500w0010-CTLFireability-2023-12
FORMULA_NAME RwMutex-PT-r0500w0010-CTLFireability-2023-13
FORMULA_NAME RwMutex-PT-r0500w0010-CTLFireability-2023-14
FORMULA_NAME RwMutex-PT-r0500w0010-CTLFireability-2023-15

=== Now, execution of the tool begins

BK_START 1717221901155

Invoking MCC driver with
BK_TOOL=ltsminxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=RwMutex-PT-r0500w0010
BK_MEMORY_CONFINEMENT=16384
Applying reductions before tool ltsmin
Invoking reducer
Running Version 202405141337
[2024-06-01 06:05:02] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2024-06-01 06:05:02] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2024-06-01 06:05:02] [INFO ] Load time of PNML (sax parser for PT used): 195 ms
[2024-06-01 06:05:02] [INFO ] Transformed 1520 places.
[2024-06-01 06:05:02] [INFO ] Transformed 1020 transitions.
[2024-06-01 06:05:02] [INFO ] Found NUPN structural information;
[2024-06-01 06:05:02] [INFO ] Parsed PT model containing 1520 places and 1020 transitions and 13040 arcs in 313 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 11 ms.
Initial state reduction rules removed 1 formulas.
FORMULA RwMutex-PT-r0500w0010-CTLFireability-2023-14 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 562 out of 1520 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 1520/1520 places, 1020/1020 transitions.
Applied a total of 0 rules in 141 ms. Remains 1520 /1520 variables (removed 0) and now considering 1020/1020 (removed 0) transitions.
// Phase 1: matrix 1020 rows 1520 cols
[2024-06-01 06:05:02] [INFO ] Computed 1010 invariants in 52 ms
[2024-06-01 06:05:04] [INFO ] Implicit Places using invariants in 1415 ms returned [1, 2, 35, 46, 57, 68, 79, 90, 101, 112, 113, 124, 135, 146, 157, 168, 179, 190, 201, 212, 223, 224, 246, 257, 268, 290, 301, 323, 334, 335, 346, 357, 368, 379, 390, 401, 412, 423, 434, 445, 446, 457, 468, 479, 490, 501, 512, 523, 534, 545, 556, 557, 568, 579, 581, 582, 583, 584, 585, 586, 588, 589, 590, 591, 592, 593, 594, 596, 597, 598, 599, 600, 601, 603, 604, 605, 606, 607, 608, 609, 610, 611, 612, 613, 615, 616, 617, 618, 619, 620, 621, 622, 623, 624, 625, 626, 627, 628, 629, 630, 631, 632, 633, 634, 635, 636, 637, 638, 639, 640, 641, 642, 643, 644, 645, 646, 647, 648, 649, 650, 651, 652, 653, 654, 655, 656, 657, 658, 659, 660, 661, 662, 663, 664, 665, 666, 667, 668, 669, 670, 671, 672, 673, 674, 675, 676, 677, 678, 679, 680, 681, 682, 683, 684, 685, 686, 687, 688, 689, 690, 691, 692, 693, 694, 695, 697, 698, 699, 700, 701, 702, 703, 706, 707, 708, 709, 710, 711, 712, 713, 714, 715, 716, 717, 718, 719, 720, 721, 722, 723, 724, 726, 727, 729, 730, 731, 732, 733, 734, 735, 736, 737, 738, 740, 741, 742, 743, 744, 745, 746, 747, 748, 749, 750, 751, 752, 753, 754, 755, 756, 757, 758, 759, 760, 761, 762, 763, 764, 765, 766, 767, 769, 770, 771, 772, 773, 774, 775, 776, 778, 779, 780, 781, 782, 783, 784, 786, 787, 788, 789, 790, 791, 792, 793, 794, 795, 796, 797, 799, 800, 802, 803, 804, 805, 806, 807, 808, 809, 810, 811, 812, 813, 814, 815, 817, 818, 819, 820, 821, 823, 824, 825, 826, 827, 829, 830, 831, 832, 833, 834, 835, 836, 837, 838, 839, 840, 841, 842, 843, 844, 845, 847, 848, 849, 850, 851, 852, 853, 854, 855, 856, 857, 858, 859, 860, 861, 862, 863, 864, 865, 867, 868, 869, 870, 871, 872, 873, 874, 875, 876, 877, 878, 879, 880, 881, 882, 883, 884, 885, 886, 887, 888, 889, 890, 891, 892, 893, 894, 895, 896, 897, 898, 899, 900, 901, 902, 903, 904, 905, 907, 908, 909, 910, 911, 912, 913, 914, 915, 916, 917, 918, 919, 920, 921, 922, 923, 924, 925, 926, 927, 928, 929, 930, 931, 932, 933, 934, 935, 936, 937, 938, 939, 940, 941, 942, 943, 944, 945, 946, 947, 948, 949, 950, 951, 952, 954, 955, 956, 958, 961, 962, 963, 964, 965, 966, 967, 968, 969, 970, 971, 972, 973, 974, 975, 977, 978, 979, 988, 999, 1010, 1021, 1032, 1043, 1054, 1065, 1076, 1077, 1088, 1099, 1110, 1132, 1143, 1165, 1176, 1187, 1188, 1199, 1210, 1221, 1232, 1243, 1265, 1276, 1287, 1298, 1310, 1321, 1332, 1343, 1354, 1365, 1376, 1387, 1398, 1409, 1410, 1421, 1443, 1454, 1465, 1476, 1487, 1498, 1509]
Discarding 474 places :
Implicit Place search using SMT only with invariants took 1465 ms to find 474 implicit places.
Starting structural reductions in LTL mode, iteration 1 : 1046/1520 places, 1020/1020 transitions.
Discarding 8 places :
Symmetric choice reduction at 0 with 8 rule applications. Total rules 8 place count 1038 transition count 1012
Iterating global reduction 0 with 8 rules applied. Total rules applied 16 place count 1038 transition count 1012
Ensure Unique test removed 8 transitions
Reduce isomorphic transitions removed 8 transitions.
Iterating post reduction 0 with 8 rules applied. Total rules applied 24 place count 1038 transition count 1004
Applied a total of 24 rules in 65 ms. Remains 1038 /1046 variables (removed 8) and now considering 1004/1020 (removed 16) transitions.
// Phase 1: matrix 1004 rows 1038 cols
[2024-06-01 06:05:04] [INFO ] Computed 536 invariants in 7 ms
[2024-06-01 06:05:04] [INFO ] Implicit Places using invariants in 380 ms returned []
[2024-06-01 06:05:04] [INFO ] Invariant cache hit.
[2024-06-01 06:05:05] [INFO ] Implicit Places using invariants and state equation in 483 ms returned []
Implicit Place search using SMT with State Equation took 866 ms to find 0 implicit places.
Starting structural reductions in LTL mode, iteration 2 : 1038/1520 places, 1004/1020 transitions.
Finished structural reductions in LTL mode , in 2 iterations and 2554 ms. Remains : 1038/1520 places, 1004/1020 transitions.
Support contains 562 out of 1038 places after structural reductions.
[2024-06-01 06:05:05] [INFO ] Flatten gal took : 406 ms
[2024-06-01 06:05:06] [INFO ] Flatten gal took : 153 ms
[2024-06-01 06:05:06] [INFO ] Input system was already deterministic with 1004 transitions.
RANDOM walk for 8443 steps (0 resets) in 2322 ms. (3 steps per ms) remains 0/56 properties
[2024-06-01 06:05:07] [INFO ] Flatten gal took : 119 ms
[2024-06-01 06:05:07] [INFO ] Flatten gal took : 117 ms
[2024-06-01 06:05:07] [INFO ] Input system was already deterministic with 1004 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 1038/1038 places, 1004/1004 transitions.
Applied a total of 0 rules in 149 ms. Remains 1038 /1038 variables (removed 0) and now considering 1004/1004 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 163 ms. Remains : 1038/1038 places, 1004/1004 transitions.
[2024-06-01 06:05:07] [INFO ] Flatten gal took : 101 ms
[2024-06-01 06:05:07] [INFO ] Flatten gal took : 125 ms
[2024-06-01 06:05:07] [INFO ] Input system was already deterministic with 1004 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 1038/1038 places, 1004/1004 transitions.
Graph (trivial) has 928 edges and 1038 vertex of which 928 / 1038 are part of one of the 464 SCC in 17 ms
Free SCC test removed 464 places
Ensure Unique test removed 464 transitions
Reduce isomorphic transitions removed 464 transitions.
Drop transitions (Trivial Post-Agglo cleanup.) removed 34 transitions
Trivial Post-agglo rules discarded 34 transitions
Performed 34 trivial Post agglomeration. Transition count delta: 34
Iterating post reduction 0 with 34 rules applied. Total rules applied 35 place count 574 transition count 506
Reduce places removed 68 places and 0 transitions.
Iterating post reduction 1 with 68 rules applied. Total rules applied 103 place count 506 transition count 506
Applied a total of 103 rules in 249 ms. Remains 506 /1038 variables (removed 532) and now considering 506/1004 (removed 498) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 249 ms. Remains : 506/1038 places, 506/1004 transitions.
[2024-06-01 06:05:08] [INFO ] Flatten gal took : 99 ms
[2024-06-01 06:05:08] [INFO ] Flatten gal took : 122 ms
[2024-06-01 06:05:08] [INFO ] Input system was already deterministic with 506 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1038/1038 places, 1004/1004 transitions.
Applied a total of 0 rules in 229 ms. Remains 1038 /1038 variables (removed 0) and now considering 1004/1004 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 229 ms. Remains : 1038/1038 places, 1004/1004 transitions.
[2024-06-01 06:05:08] [INFO ] Flatten gal took : 99 ms
[2024-06-01 06:05:08] [INFO ] Flatten gal took : 100 ms
[2024-06-01 06:05:09] [INFO ] Input system was already deterministic with 1004 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 1038/1038 places, 1004/1004 transitions.
Graph (trivial) has 926 edges and 1038 vertex of which 926 / 1038 are part of one of the 463 SCC in 2 ms
Free SCC test removed 463 places
Ensure Unique test removed 463 transitions
Reduce isomorphic transitions removed 463 transitions.
Drop transitions (Trivial Post-Agglo cleanup.) removed 32 transitions
Trivial Post-agglo rules discarded 32 transitions
Performed 32 trivial Post agglomeration. Transition count delta: 32
Iterating post reduction 0 with 32 rules applied. Total rules applied 33 place count 575 transition count 509
Reduce places removed 64 places and 0 transitions.
Iterating post reduction 1 with 64 rules applied. Total rules applied 97 place count 511 transition count 509
Applied a total of 97 rules in 66 ms. Remains 511 /1038 variables (removed 527) and now considering 509/1004 (removed 495) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 66 ms. Remains : 511/1038 places, 509/1004 transitions.
[2024-06-01 06:05:09] [INFO ] Flatten gal took : 104 ms
[2024-06-01 06:05:09] [INFO ] Flatten gal took : 98 ms
[2024-06-01 06:05:09] [INFO ] Input system was already deterministic with 509 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1038/1038 places, 1004/1004 transitions.
Applied a total of 0 rules in 18 ms. Remains 1038 /1038 variables (removed 0) and now considering 1004/1004 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 18 ms. Remains : 1038/1038 places, 1004/1004 transitions.
[2024-06-01 06:05:09] [INFO ] Flatten gal took : 98 ms
[2024-06-01 06:05:09] [INFO ] Flatten gal took : 102 ms
[2024-06-01 06:05:09] [INFO ] Input system was already deterministic with 1004 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1038/1038 places, 1004/1004 transitions.
Applied a total of 0 rules in 18 ms. Remains 1038 /1038 variables (removed 0) and now considering 1004/1004 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 18 ms. Remains : 1038/1038 places, 1004/1004 transitions.
[2024-06-01 06:05:09] [INFO ] Flatten gal took : 103 ms
[2024-06-01 06:05:09] [INFO ] Flatten gal took : 96 ms
[2024-06-01 06:05:09] [INFO ] Input system was already deterministic with 1004 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1038/1038 places, 1004/1004 transitions.
Applied a total of 0 rules in 17 ms. Remains 1038 /1038 variables (removed 0) and now considering 1004/1004 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 18 ms. Remains : 1038/1038 places, 1004/1004 transitions.
[2024-06-01 06:05:09] [INFO ] Flatten gal took : 97 ms
[2024-06-01 06:05:10] [INFO ] Flatten gal took : 99 ms
[2024-06-01 06:05:10] [INFO ] Input system was already deterministic with 1004 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1038/1038 places, 1004/1004 transitions.
Applied a total of 0 rules in 21 ms. Remains 1038 /1038 variables (removed 0) and now considering 1004/1004 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 21 ms. Remains : 1038/1038 places, 1004/1004 transitions.
[2024-06-01 06:05:10] [INFO ] Flatten gal took : 94 ms
[2024-06-01 06:05:10] [INFO ] Flatten gal took : 96 ms
[2024-06-01 06:05:10] [INFO ] Input system was already deterministic with 1004 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1038/1038 places, 1004/1004 transitions.
Applied a total of 0 rules in 17 ms. Remains 1038 /1038 variables (removed 0) and now considering 1004/1004 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 17 ms. Remains : 1038/1038 places, 1004/1004 transitions.
[2024-06-01 06:05:10] [INFO ] Flatten gal took : 97 ms
[2024-06-01 06:05:10] [INFO ] Flatten gal took : 95 ms
[2024-06-01 06:05:10] [INFO ] Input system was already deterministic with 1004 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1038/1038 places, 1004/1004 transitions.
Applied a total of 0 rules in 9 ms. Remains 1038 /1038 variables (removed 0) and now considering 1004/1004 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 9 ms. Remains : 1038/1038 places, 1004/1004 transitions.
[2024-06-01 06:05:10] [INFO ] Flatten gal took : 96 ms
[2024-06-01 06:05:10] [INFO ] Flatten gal took : 98 ms
[2024-06-01 06:05:10] [INFO ] Input system was already deterministic with 1004 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1038/1038 places, 1004/1004 transitions.
Applied a total of 0 rules in 16 ms. Remains 1038 /1038 variables (removed 0) and now considering 1004/1004 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 17 ms. Remains : 1038/1038 places, 1004/1004 transitions.
[2024-06-01 06:05:11] [INFO ] Flatten gal took : 95 ms
[2024-06-01 06:05:11] [INFO ] Flatten gal took : 96 ms
[2024-06-01 06:05:11] [INFO ] Input system was already deterministic with 1004 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1038/1038 places, 1004/1004 transitions.
Applied a total of 0 rules in 22 ms. Remains 1038 /1038 variables (removed 0) and now considering 1004/1004 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 22 ms. Remains : 1038/1038 places, 1004/1004 transitions.
[2024-06-01 06:05:11] [INFO ] Flatten gal took : 97 ms
[2024-06-01 06:05:11] [INFO ] Flatten gal took : 99 ms
[2024-06-01 06:05:11] [INFO ] Input system was already deterministic with 1004 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 1038/1038 places, 1004/1004 transitions.
Graph (trivial) has 930 edges and 1038 vertex of which 930 / 1038 are part of one of the 465 SCC in 1 ms
Free SCC test removed 465 places
Ensure Unique test removed 465 transitions
Reduce isomorphic transitions removed 465 transitions.
Drop transitions (Trivial Post-Agglo cleanup.) removed 32 transitions
Trivial Post-agglo rules discarded 32 transitions
Performed 32 trivial Post agglomeration. Transition count delta: 32
Iterating post reduction 0 with 32 rules applied. Total rules applied 33 place count 573 transition count 507
Reduce places removed 64 places and 0 transitions.
Iterating post reduction 1 with 64 rules applied. Total rules applied 97 place count 509 transition count 507
Applied a total of 97 rules in 38 ms. Remains 509 /1038 variables (removed 529) and now considering 507/1004 (removed 497) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 38 ms. Remains : 509/1038 places, 507/1004 transitions.
[2024-06-01 06:05:11] [INFO ] Flatten gal took : 85 ms
[2024-06-01 06:05:11] [INFO ] Flatten gal took : 87 ms
[2024-06-01 06:05:11] [INFO ] Input system was already deterministic with 507 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1038/1038 places, 1004/1004 transitions.
Applied a total of 0 rules in 17 ms. Remains 1038 /1038 variables (removed 0) and now considering 1004/1004 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 17 ms. Remains : 1038/1038 places, 1004/1004 transitions.
[2024-06-01 06:05:11] [INFO ] Flatten gal took : 95 ms
[2024-06-01 06:05:12] [INFO ] Flatten gal took : 103 ms
[2024-06-01 06:05:12] [INFO ] Input system was already deterministic with 1004 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1038/1038 places, 1004/1004 transitions.
Applied a total of 0 rules in 17 ms. Remains 1038 /1038 variables (removed 0) and now considering 1004/1004 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 17 ms. Remains : 1038/1038 places, 1004/1004 transitions.
[2024-06-01 06:05:12] [INFO ] Flatten gal took : 96 ms
[2024-06-01 06:05:12] [INFO ] Flatten gal took : 97 ms
[2024-06-01 06:05:12] [INFO ] Input system was already deterministic with 1004 transitions.
[2024-06-01 06:05:12] [INFO ] Flatten gal took : 98 ms
[2024-06-01 06:05:12] [INFO ] Flatten gal took : 98 ms
[2024-06-01 06:05:12] [INFO ] Export to MCC of 15 properties in file /home/mcc/execution/CTLFireability.sr.xml took 5 ms.
[2024-06-01 06:05:12] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 1038 places, 1004 transitions and 4076 arcs took 8 ms.
Total runtime 10305 ms.
There are residual formulas that ITS could not solve within timeout
Usage: pnml2lts-sym [-gvqh] [--order=]
[--mu-opt] [--saturation=]
[--sat-granularity=] [--save-sat-levels]
[--guidance=] [-d|--deadlock]
[--action=] [-i|--invariant=STRING] [-n|--no-exit]
[--trace=] [--type=]
[--mu=.mu] [--ctl-star=.ctl]
[--ctl=.ctl] [--ltl=.ltl] [--dot=STRING]
[--save-levels=STRING] [--pg-solve] [--attr=]
[--saturating-attractor] [--write-strategy=.spg]
[--check-strategy] [--interactive-play] [--player]
[--pg-write=.spg] [--no-matrix] [--noack=<1|2>]
[--edge-label=] [--labels] [-m|--matrix]
[--mucalc=.mcf|] [-c|--cache]
[--allow-undefined-edges] [--allow-undefined-values]
[-p|--por= (default: heur)]
[--weak=[valmari] (default: uses stronger left-commutativity)]
[--leap] [-r|--regroup=<(T,)+>] [--sloan-w1=] [--sloan-w2=]
[--cw-max-cols=] [--cw-max-rows=] [--col-ins=<(C.C',)+>]
[--mh-timeout=] [--row-perm=<(R,)+>] [--col-perm=<(C,)+>]
[--graph-metrics] [--regroup-exit] [--regroup-time]
[-g|--pins-guards] [--vset=] [--ldd32-step=]
[--ldd32-cache=] [--ldd-step=] [--ldd-cache=]
[--cache-ratio=] [--max-increase=]
[--min-free-nodes=] [--fdd-bits=]
[--fdd-reorder=]
[--vset-cache-diff=] [--no-soundness-check] [--precise]
[--next-union] [--peak-nodes] [--maxsum=]
[--block-size=] [--cluster-size=] [-v] [-q]
[--debug=] [--stats] [--where] [--when]
[--timeout=INT] [--version] [-h|--help] [--usage]
[OPTIONS] []
Could not compute solution for formula : RwMutex-PT-r0500w0010-CTLFireability-2024-00
Could not compute solution for formula : RwMutex-PT-r0500w0010-CTLFireability-2024-01
Could not compute solution for formula : RwMutex-PT-r0500w0010-CTLFireability-2024-02
Could not compute solution for formula : RwMutex-PT-r0500w0010-CTLFireability-2024-03
Could not compute solution for formula : RwMutex-PT-r0500w0010-CTLFireability-2024-04
Could not compute solution for formula : RwMutex-PT-r0500w0010-CTLFireability-2024-05
Could not compute solution for formula : RwMutex-PT-r0500w0010-CTLFireability-2024-06
Could not compute solution for formula : RwMutex-PT-r0500w0010-CTLFireability-2024-07
Could not compute solution for formula : RwMutex-PT-r0500w0010-CTLFireability-2024-08
Could not compute solution for formula : RwMutex-PT-r0500w0010-CTLFireability-2024-09
Could not compute solution for formula : RwMutex-PT-r0500w0010-CTLFireability-2024-10
Could not compute solution for formula : RwMutex-PT-r0500w0010-CTLFireability-2024-11
Could not compute solution for formula : RwMutex-PT-r0500w0010-CTLFireability-2023-12
Could not compute solution for formula : RwMutex-PT-r0500w0010-CTLFireability-2023-13
Could not compute solution for formula : RwMutex-PT-r0500w0010-CTLFireability-2023-15

BK_STOP 1717221912957

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202405141337.jar
+ VERSION=202405141337
+ echo 'Running Version 202405141337'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
mcc2024
ctl formula name RwMutex-PT-r0500w0010-CTLFireability-2024-00
ctl formula formula --ctl=/tmp/506/ctl_0_
ctl formula name RwMutex-PT-r0500w0010-CTLFireability-2024-01
ctl formula formula --ctl=/tmp/506/ctl_1_
ctl formula name RwMutex-PT-r0500w0010-CTLFireability-2024-02
ctl formula formula --ctl=/tmp/506/ctl_2_
ctl formula name RwMutex-PT-r0500w0010-CTLFireability-2024-03
ctl formula formula --ctl=/tmp/506/ctl_3_
ctl formula name RwMutex-PT-r0500w0010-CTLFireability-2024-04
ctl formula formula --ctl=/tmp/506/ctl_4_
ctl formula name RwMutex-PT-r0500w0010-CTLFireability-2024-05
ctl formula formula --ctl=/tmp/506/ctl_5_
ctl formula name RwMutex-PT-r0500w0010-CTLFireability-2024-06
ctl formula formula --ctl=/tmp/506/ctl_6_
ctl formula name RwMutex-PT-r0500w0010-CTLFireability-2024-07
ctl formula formula --ctl=/tmp/506/ctl_7_
ctl formula name RwMutex-PT-r0500w0010-CTLFireability-2024-08
ctl formula formula --ctl=/tmp/506/ctl_8_
ctl formula name RwMutex-PT-r0500w0010-CTLFireability-2024-09
ctl formula formula --ctl=/tmp/506/ctl_9_
ctl formula name RwMutex-PT-r0500w0010-CTLFireability-2024-10
ctl formula formula --ctl=/tmp/506/ctl_10_
ctl formula name RwMutex-PT-r0500w0010-CTLFireability-2024-11
ctl formula formula --ctl=/tmp/506/ctl_11_
ctl formula name RwMutex-PT-r0500w0010-CTLFireability-2023-12
ctl formula formula --ctl=/tmp/506/ctl_12_
ctl formula name RwMutex-PT-r0500w0010-CTLFireability-2023-13
ctl formula formula --ctl=/tmp/506/ctl_13_
ctl formula name RwMutex-PT-r0500w0010-CTLFireability-2023-15
ctl formula formula --ctl=/tmp/506/ctl_14_
pnml2lts-sym, ** error **: unknown vector set implementation lddmc

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="RwMutex-PT-r0500w0010"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="ltsminxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool ltsminxred"
echo " Input is RwMutex-PT-r0500w0010, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r524-tall-171679080100330"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/RwMutex-PT-r0500w0010.tgz
mv RwMutex-PT-r0500w0010 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;