Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r520-tall-171662338100218.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool ltsminxred
Input is RERS17pb114-PT-5, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r520-tall-171662338100218
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 73M
-rw-r--r-- 1 mcc users 8.5K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 98K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.0K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 44K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:43 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K May 18 16:43 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.5K Apr 23 07:45 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Apr 23 07:45 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.8K May 19 07:28 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K May 19 18:49 LTLFireability.xml
-rw-r--r-- 1 mcc users 9.4K May 14 13:22 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 95K May 14 13:22 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 13K May 14 13:22 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 79K May 14 13:22 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.5K May 19 07:14 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K May 19 15:29 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 2 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 73M May 18 16:43 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME RERS17pb114-PT-5-CTLFireability-2024-00
FORMULA_NAME RERS17pb114-PT-5-CTLFireability-2024-01
FORMULA_NAME RERS17pb114-PT-5-CTLFireability-2024-02
FORMULA_NAME RERS17pb114-PT-5-CTLFireability-2024-03
FORMULA_NAME RERS17pb114-PT-5-CTLFireability-2024-04
FORMULA_NAME RERS17pb114-PT-5-CTLFireability-2024-05
FORMULA_NAME RERS17pb114-PT-5-CTLFireability-2024-06
FORMULA_NAME RERS17pb114-PT-5-CTLFireability-2024-07
FORMULA_NAME RERS17pb114-PT-5-CTLFireability-2024-08
FORMULA_NAME RERS17pb114-PT-5-CTLFireability-2024-09
FORMULA_NAME RERS17pb114-PT-5-CTLFireability-2024-10
FORMULA_NAME RERS17pb114-PT-5-CTLFireability-2024-11
FORMULA_NAME RERS17pb114-PT-5-CTLFireability-2023-12
FORMULA_NAME RERS17pb114-PT-5-CTLFireability-2023-13
FORMULA_NAME RERS17pb114-PT-5-CTLFireability-2023-14
FORMULA_NAME RERS17pb114-PT-5-CTLFireability-2023-15

=== Now, execution of the tool begins

BK_START 1717231698597

Invoking MCC driver with
BK_TOOL=ltsminxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=RERS17pb114-PT-5
BK_MEMORY_CONFINEMENT=16384
Applying reductions before tool ltsmin
Invoking reducer
Running Version 202405141337
[2024-06-01 08:48:19] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2024-06-01 08:48:19] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2024-06-01 08:48:21] [INFO ] Load time of PNML (sax parser for PT used): 1985 ms
[2024-06-01 08:48:21] [INFO ] Transformed 1446 places.
[2024-06-01 08:48:22] [INFO ] Transformed 151085 transitions.
[2024-06-01 08:48:22] [INFO ] Parsed PT model containing 1446 places and 151085 transitions and 604252 arcs in 2521 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 47 ms.
Support contains 166 out of 1446 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 1446/1446 places, 151085/151085 transitions.
Ensure Unique test removed 17 places
Iterating post reduction 0 with 17 rules applied. Total rules applied 17 place count 1429 transition count 151085
Applied a total of 17 rules in 1296 ms. Remains 1429 /1446 variables (removed 17) and now considering 151085/151085 (removed 0) transitions.
[2024-06-01 08:48:24] [INFO ] Flow matrix only has 84691 transitions (discarded 66394 similar events)
// Phase 1: matrix 84691 rows 1429 cols
[2024-06-01 08:48:25] [INFO ] Computed 18 invariants in 532 ms
[2024-06-01 08:48:34] [INFO ] Implicit Places using invariants in 9486 ms returned []
Implicit Place search using SMT only with invariants took 9520 ms to find 0 implicit places.
Running 151084 sub problems to find dead transitions.
[2024-06-01 08:48:35] [INFO ] Flow matrix only has 84691 transitions (discarded 66394 similar events)
[2024-06-01 08:48:35] [INFO ] Invariant cache hit.
[2024-06-01 08:48:41] [INFO ] State equation strengthened by 2342 read => feed constraints.
Usage: pnml2lts-sym [-gvqh] [--order=]
[--mu-opt] [--saturation=]
[--sat-granularity=] [--save-sat-levels]
[--guidance=] [-d|--deadlock]
[--action=] [-i|--invariant=STRING] [-n|--no-exit]
[--trace=] [--type=]
[--mu=.mu] [--ctl-star=.ctl]
[--ctl=.ctl] [--ltl=.ltl] [--dot=STRING]
[--save-levels=STRING] [--pg-solve] [--attr=]
[--saturating-attractor] [--write-strategy=.spg]
[--check-strategy] [--interactive-play] [--player]
[--pg-write=.spg] [--no-matrix] [--noack=<1|2>]
[--edge-label=] [--labels] [-m|--matrix]
[--mucalc=.mcf|] [-c|--cache]
[--allow-undefined-edges] [--allow-undefined-values]
[-p|--por= (default: heur)]
[--weak=[valmari] (default: uses stronger left-commutativity)]
[--leap] [-r|--regroup=<(T,)+>] [--sloan-w1=] [--sloan-w2=]
[--cw-max-cols=] [--cw-max-rows=] [--col-ins=<(C.C',)+>]
[--mh-timeout=] [--row-perm=<(R,)+>] [--col-perm=<(C,)+>]
[--graph-metrics] [--regroup-exit] [--regroup-time]
[-g|--pins-guards] [--vset=] [--ldd32-step=]
[--ldd32-cache=] [--ldd-step=] [--ldd-cache=]
[--cache-ratio=] [--max-increase=]
[--min-free-nodes=] [--fdd-bits=]
[--fdd-reorder=]
[--vset-cache-diff=] [--no-soundness-check] [--precise]
[--next-union] [--peak-nodes] [--maxsum=]
[--block-size=] [--cluster-size=] [-v] [-q]
[--debug=] [--stats] [--where] [--when]
[--timeout=INT] [--version] [-h|--help] [--usage]
[OPTIONS] []
Could not compute solution for formula : RERS17pb114-PT-5-CTLFireability-2024-00
Could not compute solution for formula : RERS17pb114-PT-5-CTLFireability-2024-01
Could not compute solution for formula : RERS17pb114-PT-5-CTLFireability-2024-02
Could not compute solution for formula : RERS17pb114-PT-5-CTLFireability-2024-03
Could not compute solution for formula : RERS17pb114-PT-5-CTLFireability-2024-04
Could not compute solution for formula : RERS17pb114-PT-5-CTLFireability-2024-05
Could not compute solution for formula : RERS17pb114-PT-5-CTLFireability-2024-06
Could not compute solution for formula : RERS17pb114-PT-5-CTLFireability-2024-07
Could not compute solution for formula : RERS17pb114-PT-5-CTLFireability-2024-08
Could not compute solution for formula : RERS17pb114-PT-5-CTLFireability-2024-09
Could not compute solution for formula : RERS17pb114-PT-5-CTLFireability-2024-10
Could not compute solution for formula : RERS17pb114-PT-5-CTLFireability-2024-11
Could not compute solution for formula : RERS17pb114-PT-5-CTLFireability-2023-12
Could not compute solution for formula : RERS17pb114-PT-5-CTLFireability-2023-13
Could not compute solution for formula : RERS17pb114-PT-5-CTLFireability-2023-14
Could not compute solution for formula : RERS17pb114-PT-5-CTLFireability-2023-15

BK_STOP 1717232031824

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202405141337.jar
+ VERSION=202405141337
+ echo 'Running Version 202405141337'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
mcc2024
ctl formula name RERS17pb114-PT-5-CTLFireability-2024-00
ctl formula formula --ctl=/tmp/550/ctl_0_
ctl formula name RERS17pb114-PT-5-CTLFireability-2024-01
ctl formula formula --ctl=/tmp/550/ctl_1_
ctl formula name RERS17pb114-PT-5-CTLFireability-2024-02
ctl formula formula --ctl=/tmp/550/ctl_2_
ctl formula name RERS17pb114-PT-5-CTLFireability-2024-03
ctl formula formula --ctl=/tmp/550/ctl_3_
ctl formula name RERS17pb114-PT-5-CTLFireability-2024-04
ctl formula formula --ctl=/tmp/550/ctl_4_
ctl formula name RERS17pb114-PT-5-CTLFireability-2024-05
ctl formula formula --ctl=/tmp/550/ctl_5_
ctl formula name RERS17pb114-PT-5-CTLFireability-2024-06
ctl formula formula --ctl=/tmp/550/ctl_6_
ctl formula name RERS17pb114-PT-5-CTLFireability-2024-07
ctl formula formula --ctl=/tmp/550/ctl_7_
ctl formula name RERS17pb114-PT-5-CTLFireability-2024-08
ctl formula formula --ctl=/tmp/550/ctl_8_
ctl formula name RERS17pb114-PT-5-CTLFireability-2024-09
ctl formula formula --ctl=/tmp/550/ctl_9_
ctl formula name RERS17pb114-PT-5-CTLFireability-2024-10
ctl formula formula --ctl=/tmp/550/ctl_10_
ctl formula name RERS17pb114-PT-5-CTLFireability-2024-11
ctl formula formula --ctl=/tmp/550/ctl_11_
ctl formula name RERS17pb114-PT-5-CTLFireability-2023-12
ctl formula formula --ctl=/tmp/550/ctl_12_
ctl formula name RERS17pb114-PT-5-CTLFireability-2023-13
ctl formula formula --ctl=/tmp/550/ctl_13_
ctl formula name RERS17pb114-PT-5-CTLFireability-2023-14
ctl formula formula --ctl=/tmp/550/ctl_14_
ctl formula name RERS17pb114-PT-5-CTLFireability-2023-15
ctl formula formula --ctl=/tmp/550/ctl_15_
pnml2lts-sym, ** error **: unknown vector set implementation lddmc

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="RERS17pb114-PT-5"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="ltsminxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool ltsminxred"
echo " Input is RERS17pb114-PT-5, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r520-tall-171662338100218"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/RERS17pb114-PT-5.tgz
mv RERS17pb114-PT-5 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;