fond
Model Checking Contest 2024
14th edition, Geneva, Switzerland, June 25, 2024
Execution of r520-tall-171662337800110
Last Updated
July 7, 2024

About the Execution of LTSMin+red for QuasiCertifProtocol-PT-32

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
5905.220 31300.00 59823.00 70.00 TTTFFFTFFFTFTFTT normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r520-tall-171662337800110.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool ltsminxred
Input is QuasiCertifProtocol-PT-32, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r520-tall-171662337800110
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 5.0M
-rw-r--r-- 1 mcc users 80K Apr 13 04:10 CTLCardinality.txt
-rw-r--r-- 1 mcc users 499K Apr 13 04:10 CTLCardinality.xml
-rw-r--r-- 1 mcc users 24K Apr 13 03:48 CTLFireability.txt
-rw-r--r-- 1 mcc users 148K Apr 13 03:48 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:43 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.8K May 18 16:43 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 49K Apr 23 07:44 LTLCardinality.txt
-rw-r--r-- 1 mcc users 216K Apr 23 07:44 LTLCardinality.xml
-rw-r--r-- 1 mcc users 8.2K Apr 23 07:44 LTLFireability.txt
-rw-r--r-- 1 mcc users 45K Apr 23 07:44 LTLFireability.xml
-rw-r--r-- 1 mcc users 387K Apr 13 04:34 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 2.3M Apr 13 04:34 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 40K Apr 13 04:13 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 236K Apr 13 04:13 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.9K Apr 23 07:44 UpperBounds.txt
-rw-r--r-- 1 mcc users 7.5K Apr 23 07:44 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 3 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 942K May 18 16:43 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME QuasiCertifProtocol-PT-32-ReachabilityCardinality-2024-00
FORMULA_NAME QuasiCertifProtocol-PT-32-ReachabilityCardinality-2024-01
FORMULA_NAME QuasiCertifProtocol-PT-32-ReachabilityCardinality-2024-02
FORMULA_NAME QuasiCertifProtocol-PT-32-ReachabilityCardinality-2024-03
FORMULA_NAME QuasiCertifProtocol-PT-32-ReachabilityCardinality-2024-04
FORMULA_NAME QuasiCertifProtocol-PT-32-ReachabilityCardinality-2024-05
FORMULA_NAME QuasiCertifProtocol-PT-32-ReachabilityCardinality-2024-06
FORMULA_NAME QuasiCertifProtocol-PT-32-ReachabilityCardinality-2024-07
FORMULA_NAME QuasiCertifProtocol-PT-32-ReachabilityCardinality-2024-08
FORMULA_NAME QuasiCertifProtocol-PT-32-ReachabilityCardinality-2024-09
FORMULA_NAME QuasiCertifProtocol-PT-32-ReachabilityCardinality-2024-10
FORMULA_NAME QuasiCertifProtocol-PT-32-ReachabilityCardinality-2024-11
FORMULA_NAME QuasiCertifProtocol-PT-32-ReachabilityCardinality-2024-12
FORMULA_NAME QuasiCertifProtocol-PT-32-ReachabilityCardinality-2024-13
FORMULA_NAME QuasiCertifProtocol-PT-32-ReachabilityCardinality-2024-14
FORMULA_NAME QuasiCertifProtocol-PT-32-ReachabilityCardinality-2024-15

=== Now, execution of the tool begins

BK_START 1717221922195

Invoking MCC driver with
BK_TOOL=ltsminxred
BK_EXAMINATION=ReachabilityCardinality
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=QuasiCertifProtocol-PT-32
BK_MEMORY_CONFINEMENT=16384
Applying reductions before tool ltsmin
Invoking reducer
Running Version 202405141337
[2024-06-01 06:05:23] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityCardinality, -timeout, 360, -rebuildPNML]
[2024-06-01 06:05:23] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2024-06-01 06:05:23] [INFO ] Load time of PNML (sax parser for PT used): 158 ms
[2024-06-01 06:05:23] [INFO ] Transformed 3806 places.
[2024-06-01 06:05:23] [INFO ] Transformed 506 transitions.
[2024-06-01 06:05:23] [INFO ] Parsed PT model containing 3806 places and 506 transitions and 8173 arcs in 279 ms.
Parsed 16 properties from file /home/mcc/execution/ReachabilityCardinality.xml in 97 ms.
Working with output stream class java.io.PrintStream
RANDOM walk for 40000 steps (1071 resets) in 3302 ms. (12 steps per ms) remains 15/16 properties
FORMULA QuasiCertifProtocol-PT-32-ReachabilityCardinality-2024-00 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
BEST_FIRST walk for 4004 steps (8 resets) in 812 ms. (4 steps per ms) remains 15/15 properties
BEST_FIRST walk for 4004 steps (8 resets) in 37 ms. (105 steps per ms) remains 15/15 properties
BEST_FIRST walk for 4004 steps (8 resets) in 924 ms. (4 steps per ms) remains 15/15 properties
BEST_FIRST walk for 4004 steps (8 resets) in 211 ms. (18 steps per ms) remains 15/15 properties
BEST_FIRST walk for 4004 steps (8 resets) in 674 ms. (5 steps per ms) remains 15/15 properties
BEST_FIRST walk for 4004 steps (8 resets) in 246 ms. (16 steps per ms) remains 15/15 properties
BEST_FIRST walk for 4004 steps (8 resets) in 43 ms. (91 steps per ms) remains 15/15 properties
BEST_FIRST walk for 4004 steps (8 resets) in 32 ms. (121 steps per ms) remains 15/15 properties
BEST_FIRST walk for 4004 steps (8 resets) in 18 ms. (210 steps per ms) remains 15/15 properties
BEST_FIRST walk for 4004 steps (8 resets) in 34 ms. (114 steps per ms) remains 15/15 properties
BEST_FIRST walk for 4004 steps (8 resets) in 18 ms. (210 steps per ms) remains 15/15 properties
BEST_FIRST walk for 4004 steps (8 resets) in 22 ms. (174 steps per ms) remains 15/15 properties
BEST_FIRST walk for 4004 steps (8 resets) in 18 ms. (210 steps per ms) remains 15/15 properties
BEST_FIRST walk for 4004 steps (8 resets) in 17 ms. (222 steps per ms) remains 15/15 properties
BEST_FIRST walk for 4004 steps (8 resets) in 18 ms. (210 steps per ms) remains 15/15 properties
Interrupted probabilistic random walk after 303679 steps, run timeout after 3001 ms. (steps per millisecond=101 ) properties seen :0 out of 15
Probabilistic random walk after 303679 steps, saw 39352 distinct states, run finished after 3024 ms. (steps per millisecond=100 ) properties seen :0
// Phase 1: matrix 506 rows 3806 cols
[2024-06-01 06:05:29] [INFO ] Computed 3301 invariants in 266 ms
Problem QuasiCertifProtocol-PT-32-ReachabilityCardinality-2024-01 is UNSAT
FORMULA QuasiCertifProtocol-PT-32-ReachabilityCardinality-2024-01 TRUE TECHNIQUES SMT_REFINEMENT
Problem QuasiCertifProtocol-PT-32-ReachabilityCardinality-2024-02 is UNSAT
FORMULA QuasiCertifProtocol-PT-32-ReachabilityCardinality-2024-02 TRUE TECHNIQUES SMT_REFINEMENT
Problem QuasiCertifProtocol-PT-32-ReachabilityCardinality-2024-03 is UNSAT
FORMULA QuasiCertifProtocol-PT-32-ReachabilityCardinality-2024-03 FALSE TECHNIQUES SMT_REFINEMENT
Problem QuasiCertifProtocol-PT-32-ReachabilityCardinality-2024-04 is UNSAT
FORMULA QuasiCertifProtocol-PT-32-ReachabilityCardinality-2024-04 FALSE TECHNIQUES SMT_REFINEMENT
Problem QuasiCertifProtocol-PT-32-ReachabilityCardinality-2024-05 is UNSAT
FORMULA QuasiCertifProtocol-PT-32-ReachabilityCardinality-2024-05 FALSE TECHNIQUES SMT_REFINEMENT
Problem QuasiCertifProtocol-PT-32-ReachabilityCardinality-2024-06 is UNSAT
FORMULA QuasiCertifProtocol-PT-32-ReachabilityCardinality-2024-06 TRUE TECHNIQUES SMT_REFINEMENT
Problem QuasiCertifProtocol-PT-32-ReachabilityCardinality-2024-07 is UNSAT
FORMULA QuasiCertifProtocol-PT-32-ReachabilityCardinality-2024-07 FALSE TECHNIQUES SMT_REFINEMENT
All remaining problems are real, not stopping.
At refinement iteration 0 (INCLUDED_ONLY) 0/3806 variables, 3/3 constraints. Problems are: Problem set: 7 solved, 8 unsolved
At refinement iteration 1 (INCLUDED_ONLY) 0/3806 variables, 3298/3301 constraints. Problems are: Problem set: 7 solved, 8 unsolved
At refinement iteration 2 (INCLUDED_ONLY) 0/3806 variables, 0/3301 constraints. Problems are: Problem set: 7 solved, 8 unsolved
Problem QuasiCertifProtocol-PT-32-ReachabilityCardinality-2024-11 is UNSAT
FORMULA QuasiCertifProtocol-PT-32-ReachabilityCardinality-2024-11 FALSE TECHNIQUES SMT_REFINEMENT
Problem QuasiCertifProtocol-PT-32-ReachabilityCardinality-2024-12 is UNSAT
FORMULA QuasiCertifProtocol-PT-32-ReachabilityCardinality-2024-12 TRUE TECHNIQUES SMT_REFINEMENT
Solver is answering 'unknown', stopping.
After SMT solving in domain Real declared 4312/4312 variables, and 7107 constraints, problems are : Problem set: 9 solved, 6 unsolved in 5095 ms.
Refiners :[Positive P Invariants (semi-flows): 3/3 constraints, Generalized P Invariants (flows): 3298/3298 constraints, State Equation: 3806/3806 constraints, PredecessorRefiner: 15/15 constraints, Known Traps: 0/0 constraints]
Escalating to Integer solving :Problem set: 9 solved, 6 unsolved
At refinement iteration 0 (INCLUDED_ONLY) 0/159 variables, 0/0 constraints. Problems are: Problem set: 9 solved, 6 unsolved
At refinement iteration 1 (OVERLAPS) 230/389 variables, 2/2 constraints. Problems are: Problem set: 9 solved, 6 unsolved
[2024-06-01 06:05:39] [INFO ] Deduced a trap composed of 8 places in 137 ms of which 18 ms to minimize.
At refinement iteration 2 (INCLUDED_ONLY) 0/389 variables, 1/3 constraints. Problems are: Problem set: 9 solved, 6 unsolved
At refinement iteration 3 (INCLUDED_ONLY) 0/389 variables, 0/3 constraints. Problems are: Problem set: 9 solved, 6 unsolved
At refinement iteration 4 (OVERLAPS) 2/391 variables, 1/4 constraints. Problems are: Problem set: 9 solved, 6 unsolved
At refinement iteration 5 (INCLUDED_ONLY) 0/391 variables, 0/4 constraints. Problems are: Problem set: 9 solved, 6 unsolved
At refinement iteration 6 (OVERLAPS) 1755/2146 variables, 1723/1727 constraints. Problems are: Problem set: 9 solved, 6 unsolved
[2024-06-01 06:05:42] [INFO ] Deduced a trap composed of 6 places in 1381 ms of which 16 ms to minimize.
[2024-06-01 06:05:43] [INFO ] Deduced a trap composed of 4 places in 695 ms of which 14 ms to minimize.
[2024-06-01 06:05:44] [INFO ] Deduced a trap composed of 4 places in 692 ms of which 10 ms to minimize.
[2024-06-01 06:05:44] [INFO ] Deduced a trap composed of 11 places in 405 ms of which 8 ms to minimize.
SMT process timed out in 15818ms, After SMT, problems are : Problem set: 9 solved, 6 unsolved
Skipping Parikh replay, no witness traces provided.
Support contains 159 out of 3806 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 3806/3806 places, 506/506 transitions.
Graph (complete) has 43474 edges and 3806 vertex of which 3603 are kept as prefixes of interest. Removing 203 places using SCC suffix rule.19 ms
Discarding 203 places :
Also discarding 4 output transitions
Drop transitions (Output transitions of discarded places.) removed 4 transitions
Drop transitions (Empty/Sink Transition effects.) removed 227 transitions
Reduce isomorphic transitions removed 227 transitions.
Discarding 64 places :
Implicit places reduction removed 64 places
Drop transitions (Trivial Post-Agglo cleanup.) removed 3 transitions
Trivial Post-agglo rules discarded 3 transitions
Performed 3 trivial Post agglomeration. Transition count delta: 3
Iterating post reduction 0 with 294 rules applied. Total rules applied 295 place count 3539 transition count 272
Reduce places removed 3 places and 0 transitions.
Performed 4 Post agglomeration using F-continuation condition.Transition count delta: 4
Iterating post reduction 1 with 7 rules applied. Total rules applied 302 place count 3536 transition count 268
Reduce places removed 4 places and 0 transitions.
Iterating post reduction 2 with 4 rules applied. Total rules applied 306 place count 3532 transition count 268
Performed 63 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 63 Pre rules applied. Total rules applied 306 place count 3532 transition count 205
Deduced a syphon composed of 63 places in 2 ms
Ensure Unique test removed 85 places
Reduce places removed 148 places and 0 transitions.
Iterating global reduction 3 with 211 rules applied. Total rules applied 517 place count 3384 transition count 205
Performed 36 Post agglomeration using F-continuation condition.Transition count delta: 36
Deduced a syphon composed of 36 places in 4 ms
Ensure Unique test removed 257 places
Reduce places removed 293 places and 0 transitions.
Iterating global reduction 3 with 329 rules applied. Total rules applied 846 place count 3091 transition count 169
Applied a total of 846 rules in 863 ms. Remains 3091 /3806 variables (removed 715) and now considering 169/506 (removed 337) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 875 ms. Remains : 3091/3806 places, 169/506 transitions.
RANDOM walk for 40000 steps (4944 resets) in 451 ms. (88 steps per ms) remains 6/6 properties
BEST_FIRST walk for 40003 steps (1335 resets) in 318 ms. (125 steps per ms) remains 6/6 properties
BEST_FIRST walk for 40003 steps (1410 resets) in 223 ms. (178 steps per ms) remains 6/6 properties
BEST_FIRST walk for 40002 steps (1701 resets) in 247 ms. (161 steps per ms) remains 6/6 properties
BEST_FIRST walk for 40004 steps (1268 resets) in 206 ms. (193 steps per ms) remains 6/6 properties
BEST_FIRST walk for 40003 steps (1313 resets) in 242 ms. (164 steps per ms) remains 6/6 properties
BEST_FIRST walk for 40001 steps (1289 resets) in 147 ms. (270 steps per ms) remains 6/6 properties
Interrupted probabilistic random walk after 181911 steps, run timeout after 3001 ms. (steps per millisecond=60 ) properties seen :0 out of 6
Probabilistic random walk after 181911 steps, saw 26091 distinct states, run finished after 3004 ms. (steps per millisecond=60 ) properties seen :0
// Phase 1: matrix 169 rows 3091 cols
[2024-06-01 06:05:49] [INFO ] Computed 2922 invariants in 55 ms
All remaining problems are real, not stopping.
At refinement iteration 0 (INCLUDED_ONLY) 0/159 variables, 0/0 constraints. Problems are: Problem set: 0 solved, 6 unsolved
At refinement iteration 1 (OVERLAPS) 163/322 variables, 132/132 constraints. Problems are: Problem set: 0 solved, 6 unsolved
At refinement iteration 2 (INCLUDED_ONLY) 0/322 variables, 0/132 constraints. Problems are: Problem set: 0 solved, 6 unsolved
Problem QuasiCertifProtocol-PT-32-ReachabilityCardinality-2024-08 is UNSAT
FORMULA QuasiCertifProtocol-PT-32-ReachabilityCardinality-2024-08 FALSE TECHNIQUES SMT_REFINEMENT
Problem QuasiCertifProtocol-PT-32-ReachabilityCardinality-2024-09 is UNSAT
FORMULA QuasiCertifProtocol-PT-32-ReachabilityCardinality-2024-09 FALSE TECHNIQUES SMT_REFINEMENT
Problem QuasiCertifProtocol-PT-32-ReachabilityCardinality-2024-13 is UNSAT
FORMULA QuasiCertifProtocol-PT-32-ReachabilityCardinality-2024-13 FALSE TECHNIQUES SMT_REFINEMENT
Problem QuasiCertifProtocol-PT-32-ReachabilityCardinality-2024-14 is UNSAT
FORMULA QuasiCertifProtocol-PT-32-ReachabilityCardinality-2024-14 TRUE TECHNIQUES SMT_REFINEMENT
At refinement iteration 3 (OVERLAPS) 2033/2355 variables, 2054/2186 constraints. Problems are: Problem set: 4 solved, 2 unsolved
At refinement iteration 4 (INCLUDED_ONLY) 0/2355 variables, 0/2186 constraints. Problems are: Problem set: 4 solved, 2 unsolved
At refinement iteration 5 (OVERLAPS) 736/3091 variables, 736/2922 constraints. Problems are: Problem set: 4 solved, 2 unsolved
At refinement iteration 6 (INCLUDED_ONLY) 0/3091 variables, 0/2922 constraints. Problems are: Problem set: 4 solved, 2 unsolved
Problem QuasiCertifProtocol-PT-32-ReachabilityCardinality-2024-15 is UNSAT
FORMULA QuasiCertifProtocol-PT-32-ReachabilityCardinality-2024-15 TRUE TECHNIQUES SMT_REFINEMENT
At refinement iteration 7 (OVERLAPS) 169/3260 variables, 3091/6013 constraints. Problems are: Problem set: 5 solved, 1 unsolved
At refinement iteration 8 (INCLUDED_ONLY) 0/3260 variables, 0/6013 constraints. Problems are: Problem set: 5 solved, 1 unsolved
At refinement iteration 9 (OVERLAPS) 0/3260 variables, 0/6013 constraints. Problems are: Problem set: 5 solved, 1 unsolved
No progress, stopping.
After SMT solving in domain Real declared 3260/3260 variables, and 6013 constraints, problems are : Problem set: 5 solved, 1 unsolved in 2353 ms.
Refiners :[Positive P Invariants (semi-flows): 132/132 constraints, Generalized P Invariants (flows): 2790/2790 constraints, State Equation: 3091/3091 constraints, PredecessorRefiner: 6/6 constraints, Known Traps: 0/0 constraints]
Escalating to Integer solving :Problem set: 5 solved, 1 unsolved
At refinement iteration 0 (INCLUDED_ONLY) 0/109 variables, 0/0 constraints. Problems are: Problem set: 5 solved, 1 unsolved
At refinement iteration 1 (OVERLAPS) 166/275 variables, 132/132 constraints. Problems are: Problem set: 5 solved, 1 unsolved
At refinement iteration 2 (INCLUDED_ONLY) 0/275 variables, 0/132 constraints. Problems are: Problem set: 5 solved, 1 unsolved
At refinement iteration 3 (OVERLAPS) 2050/2325 variables, 2024/2156 constraints. Problems are: Problem set: 5 solved, 1 unsolved
At refinement iteration 4 (INCLUDED_ONLY) 0/2325 variables, 0/2156 constraints. Problems are: Problem set: 5 solved, 1 unsolved
At refinement iteration 5 (OVERLAPS) 766/3091 variables, 766/2922 constraints. Problems are: Problem set: 5 solved, 1 unsolved
At refinement iteration 6 (INCLUDED_ONLY) 0/3091 variables, 0/2922 constraints. Problems are: Problem set: 5 solved, 1 unsolved
Problem QuasiCertifProtocol-PT-32-ReachabilityCardinality-2024-10 is UNSAT
FORMULA QuasiCertifProtocol-PT-32-ReachabilityCardinality-2024-10 TRUE TECHNIQUES SMT_REFINEMENT
After SMT solving in domain Int declared 3260/3260 variables, and 6013 constraints, problems are : Problem set: 6 solved, 0 unsolved in 1671 ms.
Refiners :[Positive P Invariants (semi-flows): 132/132 constraints, Generalized P Invariants (flows): 2790/2790 constraints, State Equation: 3091/3091 constraints, PredecessorRefiner: 0/6 constraints, Known Traps: 0/0 constraints]
After SMT, in 4202ms problems are : Problem set: 6 solved, 0 unsolved
Skipping Parikh replay, no witness traces provided.
All properties solved without resorting to model-checking.
Total runtime 30044 ms.
ITS solved all properties within timeout

BK_STOP 1717221953495

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202405141337.jar
+ VERSION=202405141337
+ echo 'Running Version 202405141337'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination ReachabilityCardinality -timeout 360 -rebuildPNML

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="QuasiCertifProtocol-PT-32"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="ltsminxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool ltsminxred"
echo " Input is QuasiCertifProtocol-PT-32, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r520-tall-171662337800110"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/QuasiCertifProtocol-PT-32.tgz
mv QuasiCertifProtocol-PT-32 execution
cd execution
if [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "UpperBounds" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] || [ "ReachabilityCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME ReachabilityCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;