fond
Model Checking Contest 2024
14th edition, Geneva, Switzerland, June 25, 2024
Execution of r512-smll-171654407000154
Last Updated
July 7, 2024

About the Execution of LTSMin+red for PermAdmissibility-PT-01

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
1419.703 71896.00 103418.00 389.70 F???TF?????????F normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r512-smll-171654407000154.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool ltsminxred
Input is PermAdmissibility-PT-01, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r512-smll-171654407000154
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.9M
-rw-r--r-- 1 mcc users 13K Apr 12 09:15 CTLCardinality.txt
-rw-r--r-- 1 mcc users 116K Apr 12 09:15 CTLCardinality.xml
-rw-r--r-- 1 mcc users 59K Apr 12 09:12 CTLFireability.txt
-rw-r--r-- 1 mcc users 306K Apr 12 09:12 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:43 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K May 18 16:43 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.9K Apr 23 07:42 LTLCardinality.txt
-rw-r--r-- 1 mcc users 28K Apr 23 07:42 LTLCardinality.xml
-rw-r--r-- 1 mcc users 18K Apr 23 07:42 LTLFireability.txt
-rw-r--r-- 1 mcc users 73K Apr 23 07:42 LTLFireability.xml
-rw-r--r-- 1 mcc users 21K Apr 12 09:27 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 179K Apr 12 09:27 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 87K Apr 12 09:26 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 424K Apr 12 09:26 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.0K Apr 23 07:42 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.7K Apr 23 07:42 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 3 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 484K May 18 16:43 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME PermAdmissibility-PT-01-CTLFireability-2024-00
FORMULA_NAME PermAdmissibility-PT-01-CTLFireability-2024-01
FORMULA_NAME PermAdmissibility-PT-01-CTLFireability-2024-02
FORMULA_NAME PermAdmissibility-PT-01-CTLFireability-2024-03
FORMULA_NAME PermAdmissibility-PT-01-CTLFireability-2024-04
FORMULA_NAME PermAdmissibility-PT-01-CTLFireability-2024-05
FORMULA_NAME PermAdmissibility-PT-01-CTLFireability-2024-06
FORMULA_NAME PermAdmissibility-PT-01-CTLFireability-2024-07
FORMULA_NAME PermAdmissibility-PT-01-CTLFireability-2024-08
FORMULA_NAME PermAdmissibility-PT-01-CTLFireability-2024-09
FORMULA_NAME PermAdmissibility-PT-01-CTLFireability-2024-10
FORMULA_NAME PermAdmissibility-PT-01-CTLFireability-2024-11
FORMULA_NAME PermAdmissibility-PT-01-CTLFireability-2024-12
FORMULA_NAME PermAdmissibility-PT-01-CTLFireability-2024-13
FORMULA_NAME PermAdmissibility-PT-01-CTLFireability-2024-14
FORMULA_NAME PermAdmissibility-PT-01-CTLFireability-2024-15

=== Now, execution of the tool begins

BK_START 1717252404402

Invoking MCC driver with
BK_TOOL=ltsminxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=PermAdmissibility-PT-01
BK_MEMORY_CONFINEMENT=16384
Applying reductions before tool ltsmin
Invoking reducer
Running Version 202405141337
[2024-06-01 14:33:26] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2024-06-01 14:33:26] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2024-06-01 14:33:26] [INFO ] Load time of PNML (sax parser for PT used): 175 ms
[2024-06-01 14:33:26] [INFO ] Transformed 168 places.
[2024-06-01 14:33:26] [INFO ] Transformed 592 transitions.
[2024-06-01 14:33:26] [INFO ] Parsed PT model containing 168 places and 592 transitions and 3456 arcs in 342 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 42 ms.
Support contains 104 out of 168 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 168/168 places, 592/592 transitions.
Reduce places removed 64 places and 0 transitions.
Iterating post reduction 0 with 64 rules applied. Total rules applied 64 place count 104 transition count 592
Applied a total of 64 rules in 43 ms. Remains 104 /168 variables (removed 64) and now considering 592/592 (removed 0) transitions.
// Phase 1: matrix 592 rows 104 cols
[2024-06-01 14:33:26] [INFO ] Computed 16 invariants in 42 ms
[2024-06-01 14:33:27] [INFO ] Implicit Places using invariants in 297 ms returned []
[2024-06-01 14:33:27] [INFO ] Invariant cache hit.
[2024-06-01 14:33:27] [INFO ] Implicit Places using invariants and state equation in 394 ms returned []
Implicit Place search using SMT with State Equation took 740 ms to find 0 implicit places.
Running 588 sub problems to find dead transitions.
[2024-06-01 14:33:27] [INFO ] Invariant cache hit.
At refinement iteration 0 (INCLUDED_ONLY) 0/103 variables, 3/3 constraints. Problems are: Problem set: 0 solved, 588 unsolved
At refinement iteration 1 (INCLUDED_ONLY) 0/103 variables, 0/3 constraints. Problems are: Problem set: 0 solved, 588 unsolved
At refinement iteration 2 (OVERLAPS) 1/104 variables, 13/16 constraints. Problems are: Problem set: 0 solved, 588 unsolved
At refinement iteration 3 (INCLUDED_ONLY) 0/104 variables, 0/16 constraints. Problems are: Problem set: 0 solved, 588 unsolved
Problem TDEAD0 is UNSAT
Problem TDEAD12 is UNSAT
Problem TDEAD19 is UNSAT
Problem TDEAD23 is UNSAT
Problem TDEAD32 is UNSAT
Problem TDEAD41 is UNSAT
Problem TDEAD57 is UNSAT
Problem TDEAD58 is UNSAT
Problem TDEAD67 is UNSAT
Problem TDEAD72 is UNSAT
Problem TDEAD79 is UNSAT
Problem TDEAD96 is UNSAT
Problem TDEAD105 is UNSAT
Problem TDEAD114 is UNSAT
Problem TDEAD122 is UNSAT
Problem TDEAD129 is UNSAT
Problem TDEAD134 is UNSAT
Problem TDEAD143 is UNSAT
Problem TDEAD144 is UNSAT
Problem TDEAD164 is UNSAT
Problem TDEAD165 is UNSAT
Problem TDEAD174 is UNSAT
Problem TDEAD182 is UNSAT
Problem TDEAD189 is UNSAT
Problem TDEAD202 is UNSAT
Problem TDEAD211 is UNSAT
Problem TDEAD212 is UNSAT
Problem TDEAD215 is UNSAT
Problem TDEAD233 is UNSAT
Problem TDEAD242 is UNSAT
Problem TDEAD264 is UNSAT
Problem TDEAD269 is UNSAT
Problem TDEAD316 is UNSAT
Problem TDEAD355 is UNSAT
Problem TDEAD363 is UNSAT
Problem TDEAD369 is UNSAT
Problem TDEAD370 is UNSAT
Problem TDEAD373 is UNSAT
Problem TDEAD382 is UNSAT
Problem TDEAD392 is UNSAT
Problem TDEAD399 is UNSAT
Problem TDEAD415 is UNSAT
Problem TDEAD423 is UNSAT
Problem TDEAD429 is UNSAT
Problem TDEAD430 is UNSAT
Problem TDEAD441 is UNSAT
Problem TDEAD450 is UNSAT
Problem TDEAD460 is UNSAT
Problem TDEAD467 is UNSAT
Problem TDEAD476 is UNSAT
Problem TDEAD489 is UNSAT
Problem TDEAD490 is UNSAT
Problem TDEAD500 is UNSAT
Problem TDEAD501 is UNSAT
Problem TDEAD510 is UNSAT
Problem TDEAD520 is UNSAT
Problem TDEAD527 is UNSAT
Problem TDEAD536 is UNSAT
Problem TDEAD549 is UNSAT
Problem TDEAD555 is UNSAT
Problem TDEAD564 is UNSAT
Problem TDEAD573 is UNSAT
Problem TDEAD583 is UNSAT
Problem TDEAD590 is UNSAT
At refinement iteration 4 (OVERLAPS) 592/696 variables, 104/120 constraints. Problems are: Problem set: 64 solved, 524 unsolved
At refinement iteration 5 (INCLUDED_ONLY) 0/696 variables, 0/120 constraints. Problems are: Problem set: 64 solved, 524 unsolved
At refinement iteration 6 (OVERLAPS) 0/696 variables, 0/120 constraints. Problems are: Problem set: 64 solved, 524 unsolved
No progress, stopping.
After SMT solving in domain Real declared 696/696 variables, and 120 constraints, problems are : Problem set: 64 solved, 524 unsolved in 28735 ms.
Refiners :[Generalized P Invariants (flows): 16/16 constraints, State Equation: 104/104 constraints, PredecessorRefiner: 588/588 constraints, Known Traps: 0/0 constraints]
Escalating to Integer solving :Problem set: 64 solved, 524 unsolved
At refinement iteration 0 (INCLUDED_ONLY) 0/103 variables, 3/3 constraints. Problems are: Problem set: 64 solved, 524 unsolved
At refinement iteration 1 (INCLUDED_ONLY) 0/103 variables, 0/3 constraints. Problems are: Problem set: 64 solved, 524 unsolved
At refinement iteration 2 (OVERLAPS) 1/104 variables, 13/16 constraints. Problems are: Problem set: 64 solved, 524 unsolved
At refinement iteration 3 (INCLUDED_ONLY) 0/104 variables, 0/16 constraints. Problems are: Problem set: 64 solved, 524 unsolved
At refinement iteration 4 (OVERLAPS) 592/696 variables, 104/120 constraints. Problems are: Problem set: 64 solved, 524 unsolved
At refinement iteration 5 (INCLUDED_ONLY) 0/696 variables, 524/644 constraints. Problems are: Problem set: 64 solved, 524 unsolved
Solver is answering 'unknown', stopping.
After SMT solving in domain Int declared 696/696 variables, and 644 constraints, problems are : Problem set: 64 solved, 524 unsolved in 30055 ms.
Refiners :[Generalized P Invariants (flows): 16/16 constraints, State Equation: 104/104 constraints, PredecessorRefiner: 524/588 constraints, Known Traps: 0/0 constraints]
After SMT, in 60946ms problems are : Problem set: 64 solved, 524 unsolved
Search for dead transitions found 64 dead transitions in 60987ms
Found 64 dead transitions using SMT.
Drop transitions (Dead Transitions using SMT only with invariants) removed 64 transitions
Dead transitions reduction (with SMT) removed 64 transitions
Starting structural reductions in LTL mode, iteration 1 : 104/168 places, 528/592 transitions.
Applied a total of 0 rules in 4 ms. Remains 104 /104 variables (removed 0) and now considering 528/528 (removed 0) transitions.
Finished structural reductions in LTL mode , in 2 iterations and 61814 ms. Remains : 104/168 places, 528/592 transitions.
Support contains 104 out of 104 places after structural reductions.
[2024-06-01 14:34:29] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
[2024-06-01 14:34:29] [INFO ] Flatten gal took : 179 ms
FORMULA PermAdmissibility-PT-01-CTLFireability-2024-05 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2024-06-01 14:34:29] [INFO ] Flatten gal took : 132 ms
[2024-06-01 14:34:30] [INFO ] Input system was already deterministic with 528 transitions.
Reduction of identical properties reduced properties to check from 53 to 52
RANDOM walk for 40000 steps (2352 resets) in 3862 ms. (10 steps per ms) remains 6/52 properties
BEST_FIRST walk for 40004 steps (816 resets) in 1176 ms. (33 steps per ms) remains 6/6 properties
BEST_FIRST walk for 40004 steps (816 resets) in 1273 ms. (31 steps per ms) remains 6/6 properties
BEST_FIRST walk for 40004 steps (816 resets) in 349 ms. (114 steps per ms) remains 6/6 properties
BEST_FIRST walk for 40004 steps (816 resets) in 406 ms. (98 steps per ms) remains 6/6 properties
BEST_FIRST walk for 40004 steps (816 resets) in 229 ms. (173 steps per ms) remains 6/6 properties
BEST_FIRST walk for 40004 steps (816 resets) in 387 ms. (103 steps per ms) remains 6/6 properties
// Phase 1: matrix 528 rows 104 cols
[2024-06-01 14:34:32] [INFO ] Computed 16 invariants in 10 ms
All remaining problems are real, not stopping.
At refinement iteration 0 (INCLUDED_ONLY) 0/89 variables, 3/3 constraints. Problems are: Problem set: 0 solved, 6 unsolved
At refinement iteration 1 (INCLUDED_ONLY) 0/89 variables, 0/3 constraints. Problems are: Problem set: 0 solved, 6 unsolved
At refinement iteration 2 (OVERLAPS) 15/104 variables, 13/16 constraints. Problems are: Problem set: 0 solved, 6 unsolved
At refinement iteration 3 (INCLUDED_ONLY) 0/104 variables, 0/16 constraints. Problems are: Problem set: 0 solved, 6 unsolved
Problem AtomicPropp0 is UNSAT
Problem AtomicPropp5 is UNSAT
Problem AtomicPropp21 is UNSAT
Problem AtomicPropp45 is UNSAT
Problem AtomicPropp51 is UNSAT
Problem AtomicPropp52 is UNSAT
After SMT solving in domain Real declared 632/632 variables, and 120 constraints, problems are : Problem set: 6 solved, 0 unsolved in 407 ms.
Refiners :[Generalized P Invariants (flows): 16/16 constraints, State Equation: 104/104 constraints, PredecessorRefiner: 6/6 constraints, Known Traps: 0/0 constraints]
After SMT, in 808ms problems are : Problem set: 6 solved, 0 unsolved
Skipping Parikh replay, no witness traces provided.
Successfully simplified 6 atomic propositions for a total of 15 simplifications.
FORMULA PermAdmissibility-PT-01-CTLFireability-2024-00 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA PermAdmissibility-PT-01-CTLFireability-2024-15 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2024-06-01 14:34:33] [INFO ] Flatten gal took : 71 ms
[2024-06-01 14:34:33] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
FORMULA PermAdmissibility-PT-01-CTLFireability-2024-04 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2024-06-01 14:34:33] [INFO ] Flatten gal took : 59 ms
[2024-06-01 14:34:33] [INFO ] Input system was already deterministic with 528 transitions.
Support contains 102 out of 104 places (down from 103) after GAL structural reductions.
Computed a total of 104 stabilizing places and 528 stable transitions
Complete graph has no SCC; deadlocks are unavoidable. place count 104 transition count 528
Detected that all paths lead to deadlock. Applying this knowledge to assert that all AP eventually converge (and all enablings converge to false).
Starting structural reductions in LTL mode, iteration 0 : 104/104 places, 528/528 transitions.
Applied a total of 0 rules in 5 ms. Remains 104 /104 variables (removed 0) and now considering 528/528 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 104/104 places, 528/528 transitions.
[2024-06-01 14:34:33] [INFO ] Flatten gal took : 37 ms
[2024-06-01 14:34:33] [INFO ] Flatten gal took : 41 ms
[2024-06-01 14:34:34] [INFO ] Input system was already deterministic with 528 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 104/104 places, 528/528 transitions.
Graph (complete) has 975 edges and 104 vertex of which 22 are kept as prefixes of interest. Removing 82 places using SCC suffix rule.5 ms
Discarding 82 places :
Also discarding 480 output transitions
Drop transitions (Output transitions of discarded places.) removed 480 transitions
Applied a total of 1 rules in 19 ms. Remains 22 /104 variables (removed 82) and now considering 48/528 (removed 480) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 19 ms. Remains : 22/104 places, 48/528 transitions.
[2024-06-01 14:34:34] [INFO ] Flatten gal took : 3 ms
[2024-06-01 14:34:34] [INFO ] Flatten gal took : 3 ms
[2024-06-01 14:34:34] [INFO ] Input system was already deterministic with 48 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 104/104 places, 528/528 transitions.
Applied a total of 0 rules in 39 ms. Remains 104 /104 variables (removed 0) and now considering 528/528 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 40 ms. Remains : 104/104 places, 528/528 transitions.
[2024-06-01 14:34:34] [INFO ] Flatten gal took : 30 ms
[2024-06-01 14:34:34] [INFO ] Flatten gal took : 34 ms
[2024-06-01 14:34:34] [INFO ] Input system was already deterministic with 528 transitions.
Starting structural reductions in LTL mode, iteration 0 : 104/104 places, 528/528 transitions.
Applied a total of 0 rules in 4 ms. Remains 104 /104 variables (removed 0) and now considering 528/528 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 104/104 places, 528/528 transitions.
[2024-06-01 14:34:34] [INFO ] Flatten gal took : 32 ms
[2024-06-01 14:34:34] [INFO ] Flatten gal took : 35 ms
[2024-06-01 14:34:34] [INFO ] Input system was already deterministic with 528 transitions.
Starting structural reductions in LTL mode, iteration 0 : 104/104 places, 528/528 transitions.
Applied a total of 0 rules in 6 ms. Remains 104 /104 variables (removed 0) and now considering 528/528 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 7 ms. Remains : 104/104 places, 528/528 transitions.
[2024-06-01 14:34:34] [INFO ] Flatten gal took : 29 ms
[2024-06-01 14:34:34] [INFO ] Flatten gal took : 34 ms
[2024-06-01 14:34:34] [INFO ] Input system was already deterministic with 528 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 104/104 places, 528/528 transitions.
Applied a total of 0 rules in 31 ms. Remains 104 /104 variables (removed 0) and now considering 528/528 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 31 ms. Remains : 104/104 places, 528/528 transitions.
[2024-06-01 14:34:34] [INFO ] Flatten gal took : 48 ms
[2024-06-01 14:34:34] [INFO ] Flatten gal took : 30 ms
[2024-06-01 14:34:34] [INFO ] Input system was already deterministic with 528 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 104/104 places, 528/528 transitions.
Graph (complete) has 975 edges and 104 vertex of which 86 are kept as prefixes of interest. Removing 18 places using SCC suffix rule.3 ms
Discarding 18 places :
Also discarding 112 output transitions
Drop transitions (Output transitions of discarded places.) removed 112 transitions
Applied a total of 1 rules in 22 ms. Remains 86 /104 variables (removed 18) and now considering 416/528 (removed 112) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 22 ms. Remains : 86/104 places, 416/528 transitions.
[2024-06-01 14:34:34] [INFO ] Flatten gal took : 20 ms
[2024-06-01 14:34:34] [INFO ] Flatten gal took : 22 ms
[2024-06-01 14:34:34] [INFO ] Input system was already deterministic with 416 transitions.
Starting structural reductions in LTL mode, iteration 0 : 104/104 places, 528/528 transitions.
Applied a total of 0 rules in 5 ms. Remains 104 /104 variables (removed 0) and now considering 528/528 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 104/104 places, 528/528 transitions.
[2024-06-01 14:34:34] [INFO ] Flatten gal took : 27 ms
[2024-06-01 14:34:34] [INFO ] Flatten gal took : 32 ms
[2024-06-01 14:34:35] [INFO ] Input system was already deterministic with 528 transitions.
Starting structural reductions in LTL mode, iteration 0 : 104/104 places, 528/528 transitions.
Applied a total of 0 rules in 4 ms. Remains 104 /104 variables (removed 0) and now considering 528/528 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 104/104 places, 528/528 transitions.
[2024-06-01 14:34:35] [INFO ] Flatten gal took : 24 ms
[2024-06-01 14:34:35] [INFO ] Flatten gal took : 27 ms
[2024-06-01 14:34:35] [INFO ] Input system was already deterministic with 528 transitions.
Starting structural reductions in LTL mode, iteration 0 : 104/104 places, 528/528 transitions.
Applied a total of 0 rules in 4 ms. Remains 104 /104 variables (removed 0) and now considering 528/528 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 104/104 places, 528/528 transitions.
[2024-06-01 14:34:35] [INFO ] Flatten gal took : 24 ms
[2024-06-01 14:34:35] [INFO ] Flatten gal took : 28 ms
[2024-06-01 14:34:35] [INFO ] Input system was already deterministic with 528 transitions.
Starting structural reductions in LTL mode, iteration 0 : 104/104 places, 528/528 transitions.
Applied a total of 0 rules in 4 ms. Remains 104 /104 variables (removed 0) and now considering 528/528 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 104/104 places, 528/528 transitions.
[2024-06-01 14:34:35] [INFO ] Flatten gal took : 24 ms
[2024-06-01 14:34:35] [INFO ] Flatten gal took : 28 ms
[2024-06-01 14:34:35] [INFO ] Input system was already deterministic with 528 transitions.
Starting structural reductions in LTL mode, iteration 0 : 104/104 places, 528/528 transitions.
Applied a total of 0 rules in 4 ms. Remains 104 /104 variables (removed 0) and now considering 528/528 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 104/104 places, 528/528 transitions.
[2024-06-01 14:34:35] [INFO ] Flatten gal took : 23 ms
[2024-06-01 14:34:35] [INFO ] Flatten gal took : 27 ms
[2024-06-01 14:34:35] [INFO ] Input system was already deterministic with 528 transitions.
[2024-06-01 14:34:35] [INFO ] Flatten gal took : 39 ms
[2024-06-01 14:34:35] [INFO ] Flatten gal took : 36 ms
[2024-06-01 14:34:35] [INFO ] Export to MCC of 12 properties in file /home/mcc/execution/CTLFireability.sr.xml took 16 ms.
[2024-06-01 14:34:35] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 104 places, 528 transitions and 2664 arcs took 8 ms.
Total runtime 69667 ms.
There are residual formulas that ITS could not solve within timeout
Usage: pnml2lts-sym [-gvqh] [--order=]
[--mu-opt] [--saturation=]
[--sat-granularity=] [--save-sat-levels]
[--guidance=] [-d|--deadlock]
[--action=] [-i|--invariant=STRING] [-n|--no-exit]
[--trace=] [--type=]
[--mu=.mu] [--ctl-star=.ctl]
[--ctl=.ctl] [--ltl=.ltl] [--dot=STRING]
[--save-levels=STRING] [--pg-solve] [--attr=]
[--saturating-attractor] [--write-strategy=.spg]
[--check-strategy] [--interactive-play] [--player]
[--pg-write=.spg] [--no-matrix] [--noack=<1|2>]
[--edge-label=] [--labels] [-m|--matrix]
[--mucalc=.mcf|] [-c|--cache]
[--allow-undefined-edges] [--allow-undefined-values]
[-p|--por= (default: heur)]
[--weak=[valmari] (default: uses stronger left-commutativity)]
[--leap] [-r|--regroup=<(T,)+>] [--sloan-w1=] [--sloan-w2=]
[--cw-max-cols=] [--cw-max-rows=] [--col-ins=<(C.C',)+>]
[--mh-timeout=] [--row-perm=<(R,)+>] [--col-perm=<(C,)+>]
[--graph-metrics] [--regroup-exit] [--regroup-time]
[-g|--pins-guards] [--vset=] [--ldd32-step=]
[--ldd32-cache=] [--ldd-step=] [--ldd-cache=]
[--cache-ratio=] [--max-increase=]
[--min-free-nodes=] [--fdd-bits=]
[--fdd-reorder=]
[--vset-cache-diff=] [--no-soundness-check] [--precise]
[--next-union] [--peak-nodes] [--maxsum=]
[--block-size=] [--cluster-size=] [-v] [-q]
[--debug=] [--stats] [--where] [--when]
[--timeout=INT] [--version] [-h|--help] [--usage]
[OPTIONS] []
Could not compute solution for formula : PermAdmissibility-PT-01-CTLFireability-2024-01
Could not compute solution for formula : PermAdmissibility-PT-01-CTLFireability-2024-02
Could not compute solution for formula : PermAdmissibility-PT-01-CTLFireability-2024-03
Could not compute solution for formula : PermAdmissibility-PT-01-CTLFireability-2024-06
Could not compute solution for formula : PermAdmissibility-PT-01-CTLFireability-2024-07
Could not compute solution for formula : PermAdmissibility-PT-01-CTLFireability-2024-08
Could not compute solution for formula : PermAdmissibility-PT-01-CTLFireability-2024-09
Could not compute solution for formula : PermAdmissibility-PT-01-CTLFireability-2024-10
Could not compute solution for formula : PermAdmissibility-PT-01-CTLFireability-2024-11
Could not compute solution for formula : PermAdmissibility-PT-01-CTLFireability-2024-12
Could not compute solution for formula : PermAdmissibility-PT-01-CTLFireability-2024-13
Could not compute solution for formula : PermAdmissibility-PT-01-CTLFireability-2024-14

BK_STOP 1717252476298

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202405141337.jar
+ VERSION=202405141337
+ echo 'Running Version 202405141337'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
mcc2024
ctl formula name PermAdmissibility-PT-01-CTLFireability-2024-01
ctl formula formula --ctl=/tmp/522/ctl_0_
ctl formula name PermAdmissibility-PT-01-CTLFireability-2024-02
ctl formula formula --ctl=/tmp/522/ctl_1_
ctl formula name PermAdmissibility-PT-01-CTLFireability-2024-03
ctl formula formula --ctl=/tmp/522/ctl_2_
ctl formula name PermAdmissibility-PT-01-CTLFireability-2024-06
ctl formula formula --ctl=/tmp/522/ctl_3_
ctl formula name PermAdmissibility-PT-01-CTLFireability-2024-07
ctl formula formula --ctl=/tmp/522/ctl_4_
ctl formula name PermAdmissibility-PT-01-CTLFireability-2024-08
ctl formula formula --ctl=/tmp/522/ctl_5_
ctl formula name PermAdmissibility-PT-01-CTLFireability-2024-09
ctl formula formula --ctl=/tmp/522/ctl_6_
ctl formula name PermAdmissibility-PT-01-CTLFireability-2024-10
ctl formula formula --ctl=/tmp/522/ctl_7_
ctl formula name PermAdmissibility-PT-01-CTLFireability-2024-11
ctl formula formula --ctl=/tmp/522/ctl_8_
ctl formula name PermAdmissibility-PT-01-CTLFireability-2024-12
ctl formula formula --ctl=/tmp/522/ctl_9_
ctl formula name PermAdmissibility-PT-01-CTLFireability-2024-13
ctl formula formula --ctl=/tmp/522/ctl_10_
ctl formula name PermAdmissibility-PT-01-CTLFireability-2024-14
ctl formula formula --ctl=/tmp/522/ctl_11_
pnml2lts-sym, ** error **: unknown vector set implementation lddmc

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="PermAdmissibility-PT-01"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="ltsminxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool ltsminxred"
echo " Input is PermAdmissibility-PT-01, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r512-smll-171654407000154"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/PermAdmissibility-PT-01.tgz
mv PermAdmissibility-PT-01 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;