About the Execution of LTSMin+red for Kanban-PT-05000
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 273.275 | 3875.00 | 8789.00 | 62.40 | ??????????????T? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r504-tall-171649612200170.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool ltsminxred
Input is Kanban-PT-05000, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r504-tall-171649612200170
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 492K
-rw-r--r-- 1 mcc users 9.0K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 99K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.3K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 57K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.5K Apr 22 14:51 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Apr 22 14:51 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K Apr 22 14:51 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Apr 22 14:51 LTLFireability.xml
-rw-r--r-- 1 mcc users 9.6K Apr 13 07:24 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 97K Apr 13 07:24 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.3K Apr 13 07:23 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 80K Apr 13 07:23 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Apr 22 14:51 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Apr 22 14:51 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 6 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 14K May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME Kanban-PT-05000-CTLFireability-2024-00
FORMULA_NAME Kanban-PT-05000-CTLFireability-2024-01
FORMULA_NAME Kanban-PT-05000-CTLFireability-2024-02
FORMULA_NAME Kanban-PT-05000-CTLFireability-2024-03
FORMULA_NAME Kanban-PT-05000-CTLFireability-2024-04
FORMULA_NAME Kanban-PT-05000-CTLFireability-2024-05
FORMULA_NAME Kanban-PT-05000-CTLFireability-2024-06
FORMULA_NAME Kanban-PT-05000-CTLFireability-2024-07
FORMULA_NAME Kanban-PT-05000-CTLFireability-2024-08
FORMULA_NAME Kanban-PT-05000-CTLFireability-2024-09
FORMULA_NAME Kanban-PT-05000-CTLFireability-2024-10
FORMULA_NAME Kanban-PT-05000-CTLFireability-2024-11
FORMULA_NAME Kanban-PT-05000-CTLFireability-2023-12
FORMULA_NAME Kanban-PT-05000-CTLFireability-2023-13
FORMULA_NAME Kanban-PT-05000-CTLFireability-2023-14
FORMULA_NAME Kanban-PT-05000-CTLFireability-2023-15
=== Now, execution of the tool begins
BK_START 1717224265168
Invoking MCC driver with
BK_TOOL=ltsminxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=Kanban-PT-05000
BK_MEMORY_CONFINEMENT=16384
Applying reductions before tool ltsmin
Invoking reducer
Running Version 202405141337
[2024-06-01 06:44:26] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2024-06-01 06:44:26] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2024-06-01 06:44:26] [INFO ] Load time of PNML (sax parser for PT used): 34 ms
[2024-06-01 06:44:26] [INFO ] Transformed 16 places.
[2024-06-01 06:44:26] [INFO ] Transformed 16 transitions.
[2024-06-01 06:44:26] [INFO ] Parsed PT model containing 16 places and 16 transitions and 40 arcs in 130 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 24 ms.
Initial state reduction rules removed 1 formulas.
FORMULA Kanban-PT-05000-CTLFireability-2023-14 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 16 out of 16 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 16/16 places, 16/16 transitions.
Applied a total of 0 rules in 8 ms. Remains 16 /16 variables (removed 0) and now considering 16/16 (removed 0) transitions.
// Phase 1: matrix 16 rows 16 cols
[2024-06-01 06:44:26] [INFO ] Computed 5 invariants in 6 ms
[2024-06-01 06:44:26] [INFO ] Implicit Places using invariants in 120 ms returned []
[2024-06-01 06:44:26] [INFO ] Invariant cache hit.
[2024-06-01 06:44:26] [INFO ] Implicit Places using invariants and state equation in 57 ms returned []
Implicit Place search using SMT with State Equation took 209 ms to find 0 implicit places.
Running 15 sub problems to find dead transitions.
[2024-06-01 06:44:26] [INFO ] Invariant cache hit.
At refinement iteration 0 (INCLUDED_ONLY) 0/15 variables, 3/3 constraints. Problems are: Problem set: 0 solved, 15 unsolved
At refinement iteration 1 (INCLUDED_ONLY) 0/15 variables, 1/4 constraints. Problems are: Problem set: 0 solved, 15 unsolved
At refinement iteration 2 (INCLUDED_ONLY) 0/15 variables, 0/4 constraints. Problems are: Problem set: 0 solved, 15 unsolved
At refinement iteration 3 (OVERLAPS) 1/16 variables, 1/5 constraints. Problems are: Problem set: 0 solved, 15 unsolved
At refinement iteration 4 (INCLUDED_ONLY) 0/16 variables, 0/5 constraints. Problems are: Problem set: 0 solved, 15 unsolved
At refinement iteration 5 (OVERLAPS) 16/32 variables, 16/21 constraints. Problems are: Problem set: 0 solved, 15 unsolved
At refinement iteration 6 (INCLUDED_ONLY) 0/32 variables, 0/21 constraints. Problems are: Problem set: 0 solved, 15 unsolved
At refinement iteration 7 (OVERLAPS) 0/32 variables, 0/21 constraints. Problems are: Problem set: 0 solved, 15 unsolved
No progress, stopping.
After SMT solving in domain Real declared 32/32 variables, and 21 constraints, problems are : Problem set: 0 solved, 15 unsolved in 262 ms.
Refiners :[Positive P Invariants (semi-flows): 4/4 constraints, Generalized P Invariants (flows): 1/1 constraints, State Equation: 16/16 constraints, PredecessorRefiner: 15/15 constraints, Known Traps: 0/0 constraints]
Escalating to Integer solving :Problem set: 0 solved, 15 unsolved
At refinement iteration 0 (INCLUDED_ONLY) 0/15 variables, 3/3 constraints. Problems are: Problem set: 0 solved, 15 unsolved
At refinement iteration 1 (INCLUDED_ONLY) 0/15 variables, 1/4 constraints. Problems are: Problem set: 0 solved, 15 unsolved
At refinement iteration 2 (INCLUDED_ONLY) 0/15 variables, 0/4 constraints. Problems are: Problem set: 0 solved, 15 unsolved
At refinement iteration 3 (OVERLAPS) 1/16 variables, 1/5 constraints. Problems are: Problem set: 0 solved, 15 unsolved
At refinement iteration 4 (INCLUDED_ONLY) 0/16 variables, 0/5 constraints. Problems are: Problem set: 0 solved, 15 unsolved
At refinement iteration 5 (OVERLAPS) 16/32 variables, 16/21 constraints. Problems are: Problem set: 0 solved, 15 unsolved
At refinement iteration 6 (INCLUDED_ONLY) 0/32 variables, 15/36 constraints. Problems are: Problem set: 0 solved, 15 unsolved
At refinement iteration 7 (INCLUDED_ONLY) 0/32 variables, 0/36 constraints. Problems are: Problem set: 0 solved, 15 unsolved
At refinement iteration 8 (OVERLAPS) 0/32 variables, 0/36 constraints. Problems are: Problem set: 0 solved, 15 unsolved
No progress, stopping.
After SMT solving in domain Int declared 32/32 variables, and 36 constraints, problems are : Problem set: 0 solved, 15 unsolved in 184 ms.
Refiners :[Positive P Invariants (semi-flows): 4/4 constraints, Generalized P Invariants (flows): 1/1 constraints, State Equation: 16/16 constraints, PredecessorRefiner: 15/15 constraints, Known Traps: 0/0 constraints]
After SMT, in 487ms problems are : Problem set: 0 solved, 15 unsolved
Search for dead transitions found 0 dead transitions in 496ms
Finished structural reductions in LTL mode , in 1 iterations and 738 ms. Remains : 16/16 places, 16/16 transitions.
Support contains 16 out of 16 places after structural reductions.
[2024-06-01 06:44:27] [INFO ] Flatten gal took : 15 ms
[2024-06-01 06:44:27] [INFO ] Flatten gal took : 5 ms
[2024-06-01 06:44:27] [INFO ] Input system was already deterministic with 16 transitions.
Reduction of identical properties reduced properties to check from 35 to 34
RANDOM walk for 40012 steps (4 resets) in 56 ms. (701 steps per ms) remains 28/34 properties
BEST_FIRST walk for 4003 steps (8 resets) in 104 ms. (38 steps per ms) remains 0/28 properties
[2024-06-01 06:44:27] [INFO ] Flatten gal took : 2 ms
[2024-06-01 06:44:27] [INFO ] Flatten gal took : 3 ms
[2024-06-01 06:44:27] [INFO ] Input system was already deterministic with 16 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 16/16 places, 16/16 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 15 transition count 15
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 15 transition count 15
Applied a total of 2 rules in 7 ms. Remains 15 /16 variables (removed 1) and now considering 15/16 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 7 ms. Remains : 15/16 places, 15/16 transitions.
[2024-06-01 06:44:27] [INFO ] Flatten gal took : 1 ms
[2024-06-01 06:44:27] [INFO ] Flatten gal took : 2 ms
[2024-06-01 06:44:27] [INFO ] Input system was already deterministic with 15 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 16/16 places, 16/16 transitions.
Graph (trivial) has 7 edges and 16 vertex of which 2 / 16 are part of one of the 1 SCC in 1 ms
Free SCC test removed 1 places
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Ensure Unique test removed 1 places
Drop transitions (Trivial Post-Agglo cleanup.) removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 2 place count 14 transition count 14
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 3 place count 13 transition count 14
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 2 with 2 rules applied. Total rules applied 5 place count 12 transition count 13
Applied a total of 5 rules in 343 ms. Remains 12 /16 variables (removed 4) and now considering 13/16 (removed 3) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 344 ms. Remains : 12/16 places, 13/16 transitions.
[2024-06-01 06:44:28] [INFO ] Flatten gal took : 1 ms
[2024-06-01 06:44:28] [INFO ] Flatten gal took : 1 ms
[2024-06-01 06:44:28] [INFO ] Input system was already deterministic with 13 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 16/16 places, 16/16 transitions.
Graph (trivial) has 11 edges and 16 vertex of which 6 / 16 are part of one of the 3 SCC in 0 ms
Free SCC test removed 3 places
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Ensure Unique test removed 1 places
Drop transitions (Trivial Post-Agglo cleanup.) removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 2 place count 12 transition count 12
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 3 place count 11 transition count 12
Applied a total of 3 rules in 2 ms. Remains 11 /16 variables (removed 5) and now considering 12/16 (removed 4) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2 ms. Remains : 11/16 places, 12/16 transitions.
[2024-06-01 06:44:28] [INFO ] Flatten gal took : 0 ms
[2024-06-01 06:44:28] [INFO ] Flatten gal took : 1 ms
[2024-06-01 06:44:28] [INFO ] Input system was already deterministic with 12 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 16/16 places, 16/16 transitions.
Ensure Unique test removed 1 places
Applied a total of 0 rules in 1 ms. Remains 15 /16 variables (removed 1) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1 ms. Remains : 15/16 places, 16/16 transitions.
[2024-06-01 06:44:28] [INFO ] Flatten gal took : 1 ms
[2024-06-01 06:44:28] [INFO ] Flatten gal took : 1 ms
[2024-06-01 06:44:28] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in LTL mode, iteration 0 : 16/16 places, 16/16 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 15 transition count 16
Applied a total of 1 rules in 1 ms. Remains 15 /16 variables (removed 1) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 15/16 places, 16/16 transitions.
[2024-06-01 06:44:28] [INFO ] Flatten gal took : 2 ms
[2024-06-01 06:44:28] [INFO ] Flatten gal took : 1 ms
[2024-06-01 06:44:28] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in LTL mode, iteration 0 : 16/16 places, 16/16 transitions.
Applied a total of 0 rules in 0 ms. Remains 16 /16 variables (removed 0) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 16/16 places, 16/16 transitions.
[2024-06-01 06:44:28] [INFO ] Flatten gal took : 1 ms
[2024-06-01 06:44:28] [INFO ] Flatten gal took : 1 ms
[2024-06-01 06:44:28] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 16/16 places, 16/16 transitions.
Graph (trivial) has 10 edges and 16 vertex of which 6 / 16 are part of one of the 3 SCC in 0 ms
Free SCC test removed 3 places
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Ensure Unique test removed 1 places
Drop transitions (Trivial Post-Agglo cleanup.) removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 2 place count 12 transition count 12
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 3 place count 11 transition count 12
Applied a total of 3 rules in 1 ms. Remains 11 /16 variables (removed 5) and now considering 12/16 (removed 4) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2 ms. Remains : 11/16 places, 12/16 transitions.
[2024-06-01 06:44:28] [INFO ] Flatten gal took : 1 ms
[2024-06-01 06:44:28] [INFO ] Flatten gal took : 3 ms
[2024-06-01 06:44:28] [INFO ] Input system was already deterministic with 12 transitions.
Starting structural reductions in LTL mode, iteration 0 : 16/16 places, 16/16 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 15 transition count 16
Applied a total of 1 rules in 0 ms. Remains 15 /16 variables (removed 1) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 15/16 places, 16/16 transitions.
[2024-06-01 06:44:28] [INFO ] Flatten gal took : 1 ms
[2024-06-01 06:44:28] [INFO ] Flatten gal took : 1 ms
[2024-06-01 06:44:28] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 16/16 places, 16/16 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 0 with 2 rules applied. Total rules applied 2 place count 15 transition count 15
Applied a total of 2 rules in 220 ms. Remains 15 /16 variables (removed 1) and now considering 15/16 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 220 ms. Remains : 15/16 places, 15/16 transitions.
[2024-06-01 06:44:28] [INFO ] Flatten gal took : 1 ms
[2024-06-01 06:44:28] [INFO ] Flatten gal took : 1 ms
[2024-06-01 06:44:28] [INFO ] Input system was already deterministic with 15 transitions.
Starting structural reductions in LTL mode, iteration 0 : 16/16 places, 16/16 transitions.
Applied a total of 0 rules in 0 ms. Remains 16 /16 variables (removed 0) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 16/16 places, 16/16 transitions.
[2024-06-01 06:44:28] [INFO ] Flatten gal took : 1 ms
[2024-06-01 06:44:28] [INFO ] Flatten gal took : 1 ms
[2024-06-01 06:44:28] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in LTL mode, iteration 0 : 16/16 places, 16/16 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 15 transition count 16
Applied a total of 1 rules in 1 ms. Remains 15 /16 variables (removed 1) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 15/16 places, 16/16 transitions.
[2024-06-01 06:44:28] [INFO ] Flatten gal took : 6 ms
[2024-06-01 06:44:28] [INFO ] Flatten gal took : 1 ms
[2024-06-01 06:44:28] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in LTL mode, iteration 0 : 16/16 places, 16/16 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 15 transition count 16
Discarding 1 places :
Symmetric choice reduction at 1 with 1 rule applications. Total rules 2 place count 14 transition count 15
Iterating global reduction 1 with 1 rules applied. Total rules applied 3 place count 14 transition count 15
Applied a total of 3 rules in 1 ms. Remains 14 /16 variables (removed 2) and now considering 15/16 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 14/16 places, 15/16 transitions.
[2024-06-01 06:44:28] [INFO ] Flatten gal took : 0 ms
[2024-06-01 06:44:28] [INFO ] Flatten gal took : 0 ms
[2024-06-01 06:44:28] [INFO ] Input system was already deterministic with 15 transitions.
Starting structural reductions in LTL mode, iteration 0 : 16/16 places, 16/16 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 15 transition count 16
Discarding 1 places :
Symmetric choice reduction at 1 with 1 rule applications. Total rules 2 place count 14 transition count 15
Iterating global reduction 1 with 1 rules applied. Total rules applied 3 place count 14 transition count 15
Applied a total of 3 rules in 1 ms. Remains 14 /16 variables (removed 2) and now considering 15/16 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 14/16 places, 15/16 transitions.
[2024-06-01 06:44:28] [INFO ] Flatten gal took : 1 ms
[2024-06-01 06:44:28] [INFO ] Flatten gal took : 1 ms
[2024-06-01 06:44:28] [INFO ] Input system was already deterministic with 15 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 16/16 places, 16/16 transitions.
Graph (trivial) has 4 edges and 16 vertex of which 2 / 16 are part of one of the 1 SCC in 0 ms
Free SCC test removed 1 places
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Ensure Unique test removed 1 places
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 0 with 2 rules applied. Total rules applied 3 place count 13 transition count 14
Applied a total of 3 rules in 193 ms. Remains 13 /16 variables (removed 3) and now considering 14/16 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 193 ms. Remains : 13/16 places, 14/16 transitions.
[2024-06-01 06:44:28] [INFO ] Flatten gal took : 1 ms
[2024-06-01 06:44:28] [INFO ] Flatten gal took : 1 ms
[2024-06-01 06:44:28] [INFO ] Input system was already deterministic with 14 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 16/16 places, 16/16 transitions.
Applied a total of 0 rules in 1 ms. Remains 16 /16 variables (removed 0) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1 ms. Remains : 16/16 places, 16/16 transitions.
[2024-06-01 06:44:28] [INFO ] Flatten gal took : 1 ms
[2024-06-01 06:44:28] [INFO ] Flatten gal took : 1 ms
[2024-06-01 06:44:28] [INFO ] Input system was already deterministic with 16 transitions.
[2024-06-01 06:44:28] [INFO ] Flatten gal took : 2 ms
[2024-06-01 06:44:28] [INFO ] Flatten gal took : 3 ms
[2024-06-01 06:44:28] [INFO ] Export to MCC of 15 properties in file /home/mcc/execution/CTLFireability.sr.xml took 2 ms.
[2024-06-01 06:44:28] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 16 places, 16 transitions and 40 arcs took 3 ms.
Total runtime 2296 ms.
There are residual formulas that ITS could not solve within timeout
Usage: pnml2lts-sym [-gvqh] [--order=
[--mu-opt] [--saturation=
[--sat-granularity=
[--guidance=
[--action=
[--trace=
[--mu=
[--ctl=
[--save-levels=STRING] [--pg-solve] [--attr=
[--saturating-attractor] [--write-strategy=
[--check-strategy] [--interactive-play] [--player]
[--pg-write=
[--edge-label=
[--mucalc=
[--allow-undefined-edges] [--allow-undefined-values]
[-p|--por=
[--weak=[valmari] (default: uses stronger left-commutativity)]
[--leap] [-r|--regroup=<(T,)+>] [--sloan-w1=
[--cw-max-cols=
[--mh-timeout=
[--graph-metrics] [--regroup-exit] [--regroup-time]
[-g|--pins-guards] [--vset=
[--ldd32-cache=
[--cache-ratio=
[--min-free-nodes=
[--fdd-reorder=
[--vset-cache-diff=
[--next-union] [--peak-nodes] [--maxsum=
[--block-size=
[--debug=
[--timeout=INT] [--version] [-h|--help] [--usage]
[OPTIONS]
Could not compute solution for formula : Kanban-PT-05000-CTLFireability-2024-00
Could not compute solution for formula : Kanban-PT-05000-CTLFireability-2024-01
Could not compute solution for formula : Kanban-PT-05000-CTLFireability-2024-02
Could not compute solution for formula : Kanban-PT-05000-CTLFireability-2024-03
Could not compute solution for formula : Kanban-PT-05000-CTLFireability-2024-04
Could not compute solution for formula : Kanban-PT-05000-CTLFireability-2024-05
Could not compute solution for formula : Kanban-PT-05000-CTLFireability-2024-06
Could not compute solution for formula : Kanban-PT-05000-CTLFireability-2024-07
Could not compute solution for formula : Kanban-PT-05000-CTLFireability-2024-08
Could not compute solution for formula : Kanban-PT-05000-CTLFireability-2024-09
Could not compute solution for formula : Kanban-PT-05000-CTLFireability-2024-10
Could not compute solution for formula : Kanban-PT-05000-CTLFireability-2024-11
Could not compute solution for formula : Kanban-PT-05000-CTLFireability-2023-12
Could not compute solution for formula : Kanban-PT-05000-CTLFireability-2023-13
Could not compute solution for formula : Kanban-PT-05000-CTLFireability-2023-15
BK_STOP 1717224269043
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202405141337.jar
++ perl -pe 's/.*\.//g'
+ VERSION=202405141337
+ echo 'Running Version 202405141337'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
mcc2024
ctl formula name Kanban-PT-05000-CTLFireability-2024-00
ctl formula formula --ctl=/tmp/501/ctl_0_
ctl formula name Kanban-PT-05000-CTLFireability-2024-01
ctl formula formula --ctl=/tmp/501/ctl_1_
ctl formula name Kanban-PT-05000-CTLFireability-2024-02
ctl formula formula --ctl=/tmp/501/ctl_2_
ctl formula name Kanban-PT-05000-CTLFireability-2024-03
ctl formula formula --ctl=/tmp/501/ctl_3_
ctl formula name Kanban-PT-05000-CTLFireability-2024-04
ctl formula formula --ctl=/tmp/501/ctl_4_
ctl formula name Kanban-PT-05000-CTLFireability-2024-05
ctl formula formula --ctl=/tmp/501/ctl_5_
ctl formula name Kanban-PT-05000-CTLFireability-2024-06
ctl formula formula --ctl=/tmp/501/ctl_6_
ctl formula name Kanban-PT-05000-CTLFireability-2024-07
ctl formula formula --ctl=/tmp/501/ctl_7_
ctl formula name Kanban-PT-05000-CTLFireability-2024-08
ctl formula formula --ctl=/tmp/501/ctl_8_
ctl formula name Kanban-PT-05000-CTLFireability-2024-09
ctl formula formula --ctl=/tmp/501/ctl_9_
ctl formula name Kanban-PT-05000-CTLFireability-2024-10
ctl formula formula --ctl=/tmp/501/ctl_10_
ctl formula name Kanban-PT-05000-CTLFireability-2024-11
ctl formula formula --ctl=/tmp/501/ctl_11_
ctl formula name Kanban-PT-05000-CTLFireability-2023-12
ctl formula formula --ctl=/tmp/501/ctl_12_
ctl formula name Kanban-PT-05000-CTLFireability-2023-13
ctl formula formula --ctl=/tmp/501/ctl_13_
ctl formula name Kanban-PT-05000-CTLFireability-2023-15
ctl formula formula --ctl=/tmp/501/ctl_14_
pnml2lts-sym, ** error **: unknown vector set implementation lddmc
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="Kanban-PT-05000"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="ltsminxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool ltsminxred"
echo " Input is Kanban-PT-05000, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r504-tall-171649612200170"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/Kanban-PT-05000.tgz
mv Kanban-PT-05000 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;