Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r492-smll-171636266900458.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool ltsminxred
Input is FamilyReunion-COL-L05000M0500C250P250G125, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r492-smll-171636266900458
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 848K
-rw-r--r-- 1 mcc users 6.2K Apr 11 20:13 CTLCardinality.txt
-rw-r--r-- 1 mcc users 61K Apr 11 20:13 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.6K Apr 11 20:13 CTLFireability.txt
-rw-r--r-- 1 mcc users 35K Apr 11 20:13 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 7.0K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.8K Apr 22 14:44 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Apr 22 14:44 LTLCardinality.xml
-rw-r--r-- 1 mcc users 3.2K Apr 22 14:44 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Apr 22 14:44 LTLFireability.xml
-rw-r--r-- 1 mcc users 9.9K Apr 11 20:13 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 103K Apr 11 20:13 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.1K Apr 11 20:13 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 48K Apr 11 20:13 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.0K Apr 22 14:44 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.0K Apr 22 14:44 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:42 equiv_pt
-rw-r--r-- 1 mcc users 24 May 18 16:42 instance
-rw-r--r-- 1 mcc users 5 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 462K May 18 16:42 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-2024-00
FORMULA_NAME FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-2024-01
FORMULA_NAME FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-2024-02
FORMULA_NAME FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-2024-03
FORMULA_NAME FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-2024-04
FORMULA_NAME FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-2024-05
FORMULA_NAME FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-2024-06
FORMULA_NAME FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-2024-07
FORMULA_NAME FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-2024-08
FORMULA_NAME FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-2024-09
FORMULA_NAME FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-2024-10
FORMULA_NAME FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-2024-11
FORMULA_NAME FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-2024-12
FORMULA_NAME FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-2024-13
FORMULA_NAME FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-2024-14
FORMULA_NAME FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-2024-15

=== Now, execution of the tool begins

BK_START 1717274120408

Invoking MCC driver with
BK_TOOL=ltsminxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=FamilyReunion-COL-L05000M0500C250P250G125
BK_MEMORY_CONFINEMENT=16384
Applying reductions before tool ltsmin
Invoking reducer
Running Version 202405141337
[2024-06-01 20:35:22] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2024-06-01 20:35:22] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2024-06-01 20:35:23] [INFO ] Detected file is not PT type :http://www.pnml.org/version-2009/grammar/symmetricnet
log4j:WARN No appenders could be found for logger (org.apache.axiom.locator.DefaultOMMetaFactoryLocator).
log4j:WARN Please initialize the log4j system properly.
log4j:WARN See http://logging.apache.org/log4j/1.2/faq.html#noconfig for more info.
[2024-06-01 20:35:24] [WARNING] Using fallBack plugin, rng conformance not checked
[2024-06-01 20:35:24] [INFO ] Load time of PNML (colored model parsed with PNMLFW) : 1797 ms
[2024-06-01 20:35:25] [INFO ] Detected 5 constant HL places corresponding to 1256 PT places.
[2024-06-01 20:35:25] [INFO ] Imported 104 HL places and 66 HL transitions for a total of 78600109 PT places and 7.536032E7 transition bindings in 906 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 25 ms.
[2024-06-01 20:35:26] [INFO ] Built PT skeleton of HLPN with 104 places and 66 transitions 198 arcs in 81 ms.
[2024-06-01 20:35:26] [INFO ] Skeletonized 16 HLPN properties in 6 ms.
Initial state reduction rules removed 2 formulas.
FORMULA FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-2024-06 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-2024-12 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Computed a total of 104 stabilizing places and 66 stable transitions
Complete graph has no SCC; deadlocks are unavoidable. place count 104 transition count 66
Detected that all paths lead to deadlock. Applying this knowledge to assert that all AP eventually converge (and all enablings converge to false).
AF dead knowledge conclusive for 5 formulas.
FORMULA FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-2024-11 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Remains 12 properties that can be checked using skeleton over-approximation.
Reduce places removed 5 places and 0 transitions.
Computed a total of 99 stabilizing places and 66 stable transitions
Complete graph has no SCC; deadlocks are unavoidable. place count 99 transition count 66
Detected that all paths lead to deadlock. Applying this knowledge to assert that all AP eventually converge (and all enablings converge to false).
Reduction of identical properties reduced properties to check from 30 to 28
RANDOM walk for 40020 steps (4 resets) in 108 ms. (367 steps per ms) remains 28/28 properties
BEST_FIRST walk for 4004 steps (8 resets) in 292 ms. (13 steps per ms) remains 17/28 properties
BEST_FIRST walk for 4004 steps (8 resets) in 141 ms. (28 steps per ms) remains 17/17 properties
BEST_FIRST walk for 4004 steps (8 resets) in 129 ms. (30 steps per ms) remains 17/17 properties
BEST_FIRST walk for 4004 steps (8 resets) in 102 ms. (38 steps per ms) remains 17/17 properties
BEST_FIRST walk for 4004 steps (8 resets) in 93 ms. (42 steps per ms) remains 17/17 properties
BEST_FIRST walk for 4003 steps (8 resets) in 92 ms. (43 steps per ms) remains 17/17 properties
BEST_FIRST walk for 4002 steps (8 resets) in 58 ms. (67 steps per ms) remains 17/17 properties
BEST_FIRST walk for 4004 steps (8 resets) in 57 ms. (69 steps per ms) remains 17/17 properties
BEST_FIRST walk for 4003 steps (8 resets) in 37 ms. (105 steps per ms) remains 17/17 properties
BEST_FIRST walk for 4004 steps (8 resets) in 22 ms. (174 steps per ms) remains 17/17 properties
BEST_FIRST walk for 4003 steps (8 resets) in 41 ms. (95 steps per ms) remains 17/17 properties
BEST_FIRST walk for 4004 steps (8 resets) in 34 ms. (114 steps per ms) remains 17/17 properties
BEST_FIRST walk for 4004 steps (8 resets) in 31 ms. (125 steps per ms) remains 14/17 properties
BEST_FIRST walk for 4004 steps (8 resets) in 22 ms. (174 steps per ms) remains 14/14 properties
BEST_FIRST walk for 4004 steps (8 resets) in 48 ms. (81 steps per ms) remains 14/14 properties
BEST_FIRST walk for 4003 steps (8 resets) in 30 ms. (129 steps per ms) remains 14/14 properties
BEST_FIRST walk for 4003 steps (8 resets) in 21 ms. (181 steps per ms) remains 14/14 properties
// Phase 1: matrix 66 rows 99 cols
[2024-06-01 20:35:26] [INFO ] Computed 33 invariants in 15 ms
At refinement iteration 0 (INCLUDED_ONLY) 0/23 variables, 1/1 constraints. Problems are: Problem set: 0 solved, 14 unsolved
At refinement iteration 1 (INCLUDED_ONLY) 0/23 variables, 0/1 constraints. Problems are: Problem set: 0 solved, 14 unsolved
At refinement iteration 2 (OVERLAPS) 30/53 variables, 3/4 constraints. Problems are: Problem set: 0 solved, 14 unsolved
At refinement iteration 3 (INCLUDED_ONLY) 0/53 variables, 1/5 constraints. Problems are: Problem set: 0 solved, 14 unsolved
At refinement iteration 4 (INCLUDED_ONLY) 0/53 variables, 0/5 constraints. Problems are: Problem set: 0 solved, 14 unsolved
At refinement iteration 5 (OVERLAPS) 10/63 variables, 1/6 constraints. Problems are: Problem set: 0 solved, 14 unsolved
At refinement iteration 6 (INCLUDED_ONLY) 0/63 variables, 1/7 constraints. Problems are: Problem set: 0 solved, 14 unsolved
At refinement iteration 7 (INCLUDED_ONLY) 0/63 variables, 0/7 constraints. Problems are: Problem set: 0 solved, 14 unsolved
At refinement iteration 8 (OVERLAPS) 36/99 variables, 26/33 constraints. Problems are: Problem set: 0 solved, 14 unsolved
At refinement iteration 9 (INCLUDED_ONLY) 0/99 variables, 0/33 constraints. Problems are: Problem set: 0 solved, 14 unsolved
At refinement iteration 10 (OVERLAPS) 66/165 variables, 99/132 constraints. Problems are: Problem set: 0 solved, 14 unsolved
At refinement iteration 11 (INCLUDED_ONLY) 0/165 variables, 0/132 constraints. Problems are: Problem set: 0 solved, 14 unsolved
At refinement iteration 12 (OVERLAPS) 0/165 variables, 0/132 constraints. Problems are: Problem set: 0 solved, 14 unsolved
No progress, stopping.
After SMT solving in domain Real declared 165/165 variables, and 132 constraints, problems are : Problem set: 0 solved, 14 unsolved in 1469 ms.
Refiners :[Positive P Invariants (semi-flows): 4/4 constraints, Generalized P Invariants (flows): 29/29 constraints, State Equation: 99/99 constraints, PredecessorRefiner: 14/14 constraints, Known Traps: 0/0 constraints]
Escalating to Integer solving :Problem set: 0 solved, 14 unsolved
At refinement iteration 0 (INCLUDED_ONLY) 0/23 variables, 1/1 constraints. Problems are: Problem set: 0 solved, 14 unsolved
At refinement iteration 1 (INCLUDED_ONLY) 0/23 variables, 0/1 constraints. Problems are: Problem set: 0 solved, 14 unsolved
At refinement iteration 2 (OVERLAPS) 30/53 variables, 3/4 constraints. Problems are: Problem set: 0 solved, 14 unsolved
At refinement iteration 3 (INCLUDED_ONLY) 0/53 variables, 1/5 constraints. Problems are: Problem set: 0 solved, 14 unsolved
At refinement iteration 4 (INCLUDED_ONLY) 0/53 variables, 0/5 constraints. Problems are: Problem set: 0 solved, 14 unsolved
At refinement iteration 5 (OVERLAPS) 10/63 variables, 1/6 constraints. Problems are: Problem set: 0 solved, 14 unsolved
At refinement iteration 6 (INCLUDED_ONLY) 0/63 variables, 1/7 constraints. Problems are: Problem set: 0 solved, 14 unsolved
At refinement iteration 7 (INCLUDED_ONLY) 0/63 variables, 0/7 constraints. Problems are: Problem set: 0 solved, 14 unsolved
At refinement iteration 8 (OVERLAPS) 36/99 variables, 26/33 constraints. Problems are: Problem set: 0 solved, 14 unsolved
At refinement iteration 9 (INCLUDED_ONLY) 0/99 variables, 0/33 constraints. Problems are: Problem set: 0 solved, 14 unsolved
At refinement iteration 10 (OVERLAPS) 66/165 variables, 99/132 constraints. Problems are: Problem set: 0 solved, 14 unsolved
At refinement iteration 11 (INCLUDED_ONLY) 0/165 variables, 14/146 constraints. Problems are: Problem set: 0 solved, 14 unsolved
At refinement iteration 12 (INCLUDED_ONLY) 0/165 variables, 0/146 constraints. Problems are: Problem set: 0 solved, 14 unsolved
At refinement iteration 13 (OVERLAPS) 0/165 variables, 0/146 constraints. Problems are: Problem set: 0 solved, 14 unsolved
No progress, stopping.
After SMT solving in domain Int declared 165/165 variables, and 146 constraints, problems are : Problem set: 0 solved, 14 unsolved in 863 ms.
Refiners :[Positive P Invariants (semi-flows): 4/4 constraints, Generalized P Invariants (flows): 29/29 constraints, State Equation: 99/99 constraints, PredecessorRefiner: 14/14 constraints, Known Traps: 0/0 constraints]
After SMT, in 2408ms problems are : Problem set: 0 solved, 14 unsolved
Fused 14 Parikh solutions to 1 different solutions.
Finished Parikh walk after 767 steps, including 0 resets, run visited all 14 properties in 25 ms. (steps per millisecond=30 )
Parikh walk visited 14 properties in 33 ms.
[2024-06-01 20:35:29] [INFO ] Flatten gal took : 39 ms
[2024-06-01 20:35:29] [INFO ] Flatten gal took : 14 ms
Transition Gate2ANDJoin forces synchronizations/join behavior on parameter l of sort LegalResident
Transition ReceiveLangChoice forces synchronizations/join behavior on parameter m of sort MICSystem
Symmetric sort wr.t. initial and guards and successors and join/free detected :CINFORMI
Symmetric sort wr.t. initial detected :CINFORMI
Symmetric sort wr.t. initial and guards detected :CINFORMI
Applying symmetric unfolding of full symmetric sort :CINFORMI domain size was 251
Transition Gate1ANDJoin forces synchronizations/join behavior on parameter p of sort PublicAdminOffice
Symmetric sort wr.t. initial and guards and successors and join/free detected :GovernmentCommission
Symmetric sort wr.t. initial detected :GovernmentCommission
Symmetric sort wr.t. initial and guards detected :GovernmentCommission
Applying symmetric unfolding of full symmetric sort :GovernmentCommission domain size was 126
Symmetric sort wr.t. initial and guards and successors and join/free detected :Response
Symmetric sort wr.t. initial detected :Response
Transition SendClearanceToRel : guard parameter $r(Response:2) in guard (EQ $r 0)introduces in Response(2) partition with 2 elements
Usage: pnml2lts-sym [-gvqh] [--order=]
[--mu-opt] [--saturation=]
[--sat-granularity=] [--save-sat-levels]
[--guidance=] [-d|--deadlock]
[--action=] [-i|--invariant=STRING] [-n|--no-exit]
[--trace=] [--type=]
[--mu=.mu] [--ctl-star=.ctl]
[--ctl=.ctl] [--ltl=.ltl] [--dot=STRING]
[--save-levels=STRING] [--pg-solve] [--attr=]
[--saturating-attractor] [--write-strategy=.spg]
[--check-strategy] [--interactive-play] [--player]
[--pg-write=.spg] [--no-matrix] [--noack=<1|2>]
[--edge-label=] [--labels] [-m|--matrix]
[--mucalc=.mcf|] [-c|--cache]
[--allow-undefined-edges] [--allow-undefined-values]
[-p|--por= (default: heur)]
[--weak=[valmari] (default: uses stronger left-commutativity)]
[--leap] [-r|--regroup=<(T,)+>] [--sloan-w1=] [--sloan-w2=]
[--cw-max-cols=] [--cw-max-rows=] [--col-ins=<(C.C',)+>]
[--mh-timeout=] [--row-perm=<(R,)+>] [--col-perm=<(C,)+>]
[--graph-metrics] [--regroup-exit] [--regroup-time]
[-g|--pins-guards] [--vset=] [--ldd32-step=]
[--ldd32-cache=] [--ldd-step=] [--ldd-cache=]
[--cache-ratio=] [--max-increase=]
[--min-free-nodes=] [--fdd-bits=]
[--fdd-reorder=]
[--vset-cache-diff=] [--no-soundness-check] [--precise]
[--next-union] [--peak-nodes] [--maxsum=]
[--block-size=] [--cluster-size=] [-v] [-q]
[--debug=] [--stats] [--where] [--when]
[--timeout=INT] [--version] [-h|--help] [--usage]
[OPTIONS] []
Could not compute solution for formula : FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-2024-00
Could not compute solution for formula : FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-2024-01
Could not compute solution for formula : FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-2024-02
Could not compute solution for formula : FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-2024-03
Could not compute solution for formula : FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-2024-04
Could not compute solution for formula : FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-2024-05
Could not compute solution for formula : FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-2024-06
Could not compute solution for formula : FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-2024-07
Could not compute solution for formula : FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-2024-08
Could not compute solution for formula : FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-2024-09
Could not compute solution for formula : FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-2024-10
Could not compute solution for formula : FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-2024-11
Could not compute solution for formula : FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-2024-12
Could not compute solution for formula : FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-2024-13
Could not compute solution for formula : FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-2024-14
Could not compute solution for formula : FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-2024-15

BK_STOP 1717274165188

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202405141337.jar
+ VERSION=202405141337
+ echo 'Running Version 202405141337'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
mcc2024
ctl formula name FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-2024-00
ctl formula formula --ctl=/tmp/504/ctl_0_
ctl formula name FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-2024-01
ctl formula formula --ctl=/tmp/504/ctl_1_
ctl formula name FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-2024-02
ctl formula formula --ctl=/tmp/504/ctl_2_
ctl formula name FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-2024-03
ctl formula formula --ctl=/tmp/504/ctl_3_
ctl formula name FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-2024-04
ctl formula formula --ctl=/tmp/504/ctl_4_
ctl formula name FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-2024-05
ctl formula formula --ctl=/tmp/504/ctl_5_
ctl formula name FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-2024-06
ctl formula formula --ctl=/tmp/504/ctl_6_
ctl formula name FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-2024-07
ctl formula formula --ctl=/tmp/504/ctl_7_
ctl formula name FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-2024-08
ctl formula formula --ctl=/tmp/504/ctl_8_
ctl formula name FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-2024-09
ctl formula formula --ctl=/tmp/504/ctl_9_
ctl formula name FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-2024-10
ctl formula formula --ctl=/tmp/504/ctl_10_
ctl formula name FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-2024-11
ctl formula formula --ctl=/tmp/504/ctl_11_
ctl formula name FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-2024-12
ctl formula formula --ctl=/tmp/504/ctl_12_
ctl formula name FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-2024-13
ctl formula formula --ctl=/tmp/504/ctl_13_
ctl formula name FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-2024-14
ctl formula formula --ctl=/tmp/504/ctl_14_
ctl formula name FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-2024-15
ctl formula formula --ctl=/tmp/504/ctl_15_
pnml2lts-sym, ** error **: unknown vector set implementation lddmc

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="FamilyReunion-COL-L05000M0500C250P250G125"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="ltsminxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool ltsminxred"
echo " Input is FamilyReunion-COL-L05000M0500C250P250G125, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r492-smll-171636266900458"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/FamilyReunion-COL-L05000M0500C250P250G125.tgz
mv FamilyReunion-COL-L05000M0500C250P250G125 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;