Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r464-smll-171620118300306.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................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=====================================================================
Generated by BenchKit 2-5568
Executing tool ltsminxred
Input is AirplaneLD-PT-4000, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r464-smll-171620118300306
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 88M
-rw-r--r-- 1 mcc users 1.9M Apr 12 10:01 CTLCardinality.txt
-rw-r--r-- 1 mcc users 5.6M Apr 12 10:01 CTLCardinality.xml
-rw-r--r-- 1 mcc users 1.9M Apr 12 07:07 CTLFireability.txt
-rw-r--r-- 1 mcc users 11M Apr 12 07:07 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 1.4M Apr 22 14:27 LTLCardinality.txt
-rw-r--r-- 1 mcc users 3.4M Apr 22 14:27 LTLCardinality.xml
-rw-r--r-- 1 mcc users 900K Apr 22 14:27 LTLFireability.txt
-rw-r--r-- 1 mcc users 3.7M Apr 22 14:27 LTLFireability.xml
-rw-r--r-- 1 mcc users 5.0M Apr 12 16:19 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 16M Apr 12 16:19 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 3.3M Apr 12 13:51 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 18M Apr 12 13:51 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 191K Apr 22 14:27 UpperBounds.txt
-rw-r--r-- 1 mcc users 358K Apr 22 14:27 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 5 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 18M May 18 16:42 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME AirplaneLD-PT-4000-CTLFireability-2024-00
FORMULA_NAME AirplaneLD-PT-4000-CTLFireability-2024-01
FORMULA_NAME AirplaneLD-PT-4000-CTLFireability-2024-02
FORMULA_NAME AirplaneLD-PT-4000-CTLFireability-2024-03
FORMULA_NAME AirplaneLD-PT-4000-CTLFireability-2024-04
FORMULA_NAME AirplaneLD-PT-4000-CTLFireability-2024-05
FORMULA_NAME AirplaneLD-PT-4000-CTLFireability-2024-06
FORMULA_NAME AirplaneLD-PT-4000-CTLFireability-2024-07
FORMULA_NAME AirplaneLD-PT-4000-CTLFireability-2024-08
FORMULA_NAME AirplaneLD-PT-4000-CTLFireability-2024-09
FORMULA_NAME AirplaneLD-PT-4000-CTLFireability-2024-10
FORMULA_NAME AirplaneLD-PT-4000-CTLFireability-2024-11
FORMULA_NAME AirplaneLD-PT-4000-CTLFireability-2024-12
FORMULA_NAME AirplaneLD-PT-4000-CTLFireability-2024-13
FORMULA_NAME AirplaneLD-PT-4000-CTLFireability-2024-14
FORMULA_NAME AirplaneLD-PT-4000-CTLFireability-2024-15

=== Now, execution of the tool begins

BK_START 1717252928581

Invoking MCC driver with
BK_TOOL=ltsminxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=AirplaneLD-PT-4000
BK_MEMORY_CONFINEMENT=16384
Applying reductions before tool ltsmin
Invoking reducer
Running Version 202405141337
[2024-06-01 14:42:10] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2024-06-01 14:42:10] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2024-06-01 14:42:12] [INFO ] Load time of PNML (sax parser for PT used): 1718 ms
[2024-06-01 14:42:12] [INFO ] Transformed 28019 places.
[2024-06-01 14:42:12] [INFO ] Transformed 32008 transitions.
[2024-06-01 14:42:12] [INFO ] Found NUPN structural information;
[2024-06-01 14:42:12] [INFO ] Parsed PT model containing 28019 places and 32008 transitions and 122028 arcs in 2096 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 337 ms.
Reduce places removed 12002 places and 0 transitions.
Support contains 14016 out of 16017 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 16017/16017 places, 32008/32008 transitions.
Reduce places removed 3 places and 0 transitions.
Iterating post reduction 0 with 3 rules applied. Total rules applied 3 place count 16014 transition count 32008
Discarding 1997 places :
Symmetric choice reduction at 1 with 1997 rule applications. Total rules 2000 place count 14017 transition count 30011
Iterating global reduction 1 with 1997 rules applied. Total rules applied 3997 place count 14017 transition count 30011
Ensure Unique test removed 1997 transitions
Reduce isomorphic transitions removed 1997 transitions.
Iterating post reduction 1 with 1997 rules applied. Total rules applied 5994 place count 14017 transition count 28014
Applied a total of 5994 rules in 755 ms. Remains 14017 /16017 variables (removed 2000) and now considering 28014/32008 (removed 3994) transitions.
// Phase 1: matrix 28014 rows 14017 cols
[2024-06-01 14:42:43] [INFO ] Computed 1 invariants in 24413 ms
[2024-06-01 14:42:46] [INFO ] Implicit Places using invariants in 28192 ms returned []
Implicit Place search using SMT only with invariants took 28239 ms to find 0 implicit places.
Running 14007 sub problems to find dead transitions.
[2024-06-01 14:42:47] [INFO ] Invariant cache hit.
Error getting values : (error "Error writing to Z3 solver: java.io.IOException: Broken pipe")
Solver is answering 'unknown', stopping.
After SMT solving in domain Real declared 14012/42031 variables, and 0 constraints, problems are : Problem set: 0 solved, 14007 unsolved in 30353 ms.
Refiners :[Generalized P Invariants (flows): 0/1 constraints, State Equation: 0/14017 constraints, PredecessorRefiner: 14007/4 constraints, Known Traps: 0/0 constraints]
Escalating to Integer solving :Problem set: 0 solved, 14007 unsolved
Error getting values : (error "Error writing to Z3 solver: java.io.IOException: Broken pipe")
Solver is answering 'unknown', stopping.
After SMT solving in domain Int declared 14012/42031 variables, and 0 constraints, problems are : Problem set: 0 solved, 14007 unsolved in 30235 ms.
Refiners :[Generalized P Invariants (flows): 0/1 constraints, State Equation: 0/14017 constraints, PredecessorRefiner: 14003/4 constraints, Known Traps: 0/0 constraints]
After SMT, in 282802ms problems are : Problem set: 0 solved, 14007 unsolved
Search for dead transitions found 0 dead transitions in 283103ms
Starting structural reductions in LTL mode, iteration 1 : 14017/16017 places, 28014/32008 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 312235 ms. Remains : 14017/16017 places, 28014/32008 transitions.
Support contains 14016 out of 14017 places after structural reductions.
[2024-06-01 14:47:33] [INFO ] Flatten gal took : 1550 ms
[2024-06-01 14:47:39] [INFO ] Flatten gal took : 1443 ms
[2024-06-01 14:47:45] [INFO ] Input system was already deterministic with 28014 transitions.
Support contains 14015 out of 14017 places (down from 14016) after GAL structural reductions.
Reduction of identical properties reduced properties to check from 53 to 49
RANDOM walk for 22543 steps (2837 resets) in 120045 ms. (0 steps per ms) remains 22/49 properties
BEST_FIRST walk for 4004 steps (0 resets) in 6074 ms. (0 steps per ms) remains 22/22 properties
BEST_FIRST walk for 4004 steps (0 resets) in 57 ms. (69 steps per ms) remains 22/22 properties
BEST_FIRST walk for 4004 steps (0 resets) in 1431 ms. (2 steps per ms) remains 22/22 properties
BEST_FIRST walk for 4004 steps (0 resets) in 677 ms. (5 steps per ms) remains 22/22 properties
BEST_FIRST walk for 4004 steps (0 resets) in 37 ms. (105 steps per ms) remains 22/22 properties
BEST_FIRST walk for 4004 steps (0 resets) in 30 ms. (129 steps per ms) remains 22/22 properties
BEST_FIRST walk for 4004 steps (0 resets) in 31 ms. (125 steps per ms) remains 22/22 properties
BEST_FIRST walk for 4004 steps (0 resets) in 32 ms. (121 steps per ms) remains 22/22 properties
BEST_FIRST walk for 4004 steps (0 resets) in 31 ms. (125 steps per ms) remains 22/22 properties
BEST_FIRST walk for 4004 steps (0 resets) in 41 ms. (95 steps per ms) remains 22/22 properties
BEST_FIRST walk for 4004 steps (0 resets) in 32 ms. (121 steps per ms) remains 22/22 properties
BEST_FIRST walk for 4004 steps (0 resets) in 32 ms. (121 steps per ms) remains 22/22 properties
BEST_FIRST walk for 4004 steps (0 resets) in 34 ms. (114 steps per ms) remains 22/22 properties
BEST_FIRST walk for 4004 steps (0 resets) in 37 ms. (105 steps per ms) remains 22/22 properties
BEST_FIRST walk for 4004 steps (0 resets) in 36 ms. (108 steps per ms) remains 22/22 properties
BEST_FIRST walk for 4004 steps (0 resets) in 31 ms. (125 steps per ms) remains 22/22 properties
BEST_FIRST walk for 4004 steps (0 resets) in 31 ms. (125 steps per ms) remains 22/22 properties
BEST_FIRST walk for 4004 steps (0 resets) in 31 ms. (125 steps per ms) remains 22/22 properties
BEST_FIRST walk for 4004 steps (0 resets) in 31 ms. (125 steps per ms) remains 22/22 properties
BEST_FIRST walk for 4004 steps (0 resets) in 37 ms. (105 steps per ms) remains 22/22 properties
BEST_FIRST walk for 4004 steps (0 resets) in 39 ms. (100 steps per ms) remains 22/22 properties
BEST_FIRST walk for 4004 steps (0 resets) in 30 ms. (129 steps per ms) remains 22/22 properties
[2024-06-01 14:48:19] [INFO ] Invariant cache hit.
Usage: pnml2lts-sym [-gvqh] [--order=]
[--mu-opt] [--saturation=]
[--sat-granularity=] [--save-sat-levels]
[--guidance=] [-d|--deadlock]
[--action=] [-i|--invariant=STRING] [-n|--no-exit]
[--trace=] [--type=]
[--mu=.mu] [--ctl-star=.ctl]
[--ctl=.ctl] [--ltl=.ltl] [--dot=STRING]
[--save-levels=STRING] [--pg-solve] [--attr=]
[--saturating-attractor] [--write-strategy=.spg]
[--check-strategy] [--interactive-play] [--player]
[--pg-write=.spg] [--no-matrix] [--noack=<1|2>]
[--edge-label=] [--labels] [-m|--matrix]
[--mucalc=.mcf|] [-c|--cache]
[--allow-undefined-edges] [--allow-undefined-values]
[-p|--por= (default: heur)]
[--weak=[valmari] (default: uses stronger left-commutativity)]
[--leap] [-r|--regroup=<(T,)+>] [--sloan-w1=] [--sloan-w2=]
[--cw-max-cols=] [--cw-max-rows=] [--col-ins=<(C.C',)+>]
[--mh-timeout=] [--row-perm=<(R,)+>] [--col-perm=<(C,)+>]
[--graph-metrics] [--regroup-exit] [--regroup-time]
[-g|--pins-guards] [--vset=] [--ldd32-step=]
[--ldd32-cache=] [--ldd-step=] [--ldd-cache=]
[--cache-ratio=] [--max-increase=]
[--min-free-nodes=] [--fdd-bits=]
[--fdd-reorder=]
[--vset-cache-diff=] [--no-soundness-check] [--precise]
[--next-union] [--peak-nodes] [--maxsum=]
[--block-size=] [--cluster-size=] [-v] [-q]
[--debug=] [--stats] [--where] [--when]
[--timeout=INT] [--version] [-h|--help] [--usage]
[OPTIONS] []
Could not compute solution for formula : AirplaneLD-PT-4000-CTLFireability-2024-00
Could not compute solution for formula : AirplaneLD-PT-4000-CTLFireability-2024-01
Could not compute solution for formula : AirplaneLD-PT-4000-CTLFireability-2024-02
Could not compute solution for formula : AirplaneLD-PT-4000-CTLFireability-2024-03
Could not compute solution for formula : AirplaneLD-PT-4000-CTLFireability-2024-04
Could not compute solution for formula : AirplaneLD-PT-4000-CTLFireability-2024-05
Could not compute solution for formula : AirplaneLD-PT-4000-CTLFireability-2024-06
Could not compute solution for formula : AirplaneLD-PT-4000-CTLFireability-2024-07
Could not compute solution for formula : AirplaneLD-PT-4000-CTLFireability-2024-08
Could not compute solution for formula : AirplaneLD-PT-4000-CTLFireability-2024-09
Could not compute solution for formula : AirplaneLD-PT-4000-CTLFireability-2024-10
Could not compute solution for formula : AirplaneLD-PT-4000-CTLFireability-2024-11
Could not compute solution for formula : AirplaneLD-PT-4000-CTLFireability-2024-12
Could not compute solution for formula : AirplaneLD-PT-4000-CTLFireability-2024-13
Could not compute solution for formula : AirplaneLD-PT-4000-CTLFireability-2024-14
Could not compute solution for formula : AirplaneLD-PT-4000-CTLFireability-2024-15

BK_STOP 1717253327797

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202405141337.jar
+ VERSION=202405141337
+ echo 'Running Version 202405141337'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
mcc2024
ctl formula name AirplaneLD-PT-4000-CTLFireability-2024-00
ctl formula formula --ctl=/tmp/523/ctl_0_
ctl formula name AirplaneLD-PT-4000-CTLFireability-2024-01
ctl formula formula --ctl=/tmp/523/ctl_1_
ctl formula name AirplaneLD-PT-4000-CTLFireability-2024-02
ctl formula formula --ctl=/tmp/523/ctl_2_
ctl formula name AirplaneLD-PT-4000-CTLFireability-2024-03
ctl formula formula --ctl=/tmp/523/ctl_3_
ctl formula name AirplaneLD-PT-4000-CTLFireability-2024-04
ctl formula formula --ctl=/tmp/523/ctl_4_
ctl formula name AirplaneLD-PT-4000-CTLFireability-2024-05
ctl formula formula --ctl=/tmp/523/ctl_5_
ctl formula name AirplaneLD-PT-4000-CTLFireability-2024-06
ctl formula formula --ctl=/tmp/523/ctl_6_
ctl formula name AirplaneLD-PT-4000-CTLFireability-2024-07
ctl formula formula --ctl=/tmp/523/ctl_7_
ctl formula name AirplaneLD-PT-4000-CTLFireability-2024-08
ctl formula formula --ctl=/tmp/523/ctl_8_
ctl formula name AirplaneLD-PT-4000-CTLFireability-2024-09
ctl formula formula --ctl=/tmp/523/ctl_9_
ctl formula name AirplaneLD-PT-4000-CTLFireability-2024-10
ctl formula formula --ctl=/tmp/523/ctl_10_
ctl formula name AirplaneLD-PT-4000-CTLFireability-2024-11
ctl formula formula --ctl=/tmp/523/ctl_11_
ctl formula name AirplaneLD-PT-4000-CTLFireability-2024-12
ctl formula formula --ctl=/tmp/523/ctl_12_
ctl formula name AirplaneLD-PT-4000-CTLFireability-2024-13
ctl formula formula --ctl=/tmp/523/ctl_13_
ctl formula name AirplaneLD-PT-4000-CTLFireability-2024-14
ctl formula formula --ctl=/tmp/523/ctl_14_
ctl formula name AirplaneLD-PT-4000-CTLFireability-2024-15
ctl formula formula --ctl=/tmp/523/ctl_15_
pnml2lts-sym, ** error **: unknown vector set implementation lddmc

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="AirplaneLD-PT-4000"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="ltsminxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool ltsminxred"
echo " Input is AirplaneLD-PT-4000, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r464-smll-171620118300306"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/AirplaneLD-PT-4000.tgz
mv AirplaneLD-PT-4000 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;