About the Execution of LoLA for UtilityControlRoom-PT-Z4T4N08
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
11347.455 | 3600000.00 | 939390.00 | 9494.20 | ??FFTTFTT?TTTFT? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r445-smll-171701112200265.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.........................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is UtilityControlRoom-PT-Z4T4N08, examination is CTLCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r445-smll-171701112200265
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 2.3M
-rw-r--r-- 1 mcc users 52K Apr 13 05:52 CTLCardinality.txt
-rw-r--r-- 1 mcc users 251K Apr 13 05:52 CTLCardinality.xml
-rw-r--r-- 1 mcc users 74K Apr 13 05:48 CTLFireability.txt
-rw-r--r-- 1 mcc users 279K Apr 13 05:48 CTLFireability.xml
-rw-r--r-- 1 mcc users 14K Apr 23 08:04 LTLCardinality.txt
-rw-r--r-- 1 mcc users 49K Apr 23 08:04 LTLCardinality.xml
-rw-r--r-- 1 mcc users 28K Apr 23 08:04 LTLFireability.txt
-rw-r--r-- 1 mcc users 81K Apr 23 08:04 LTLFireability.xml
-rw-r--r-- 1 mcc users 43K Apr 13 06:06 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 214K Apr 13 06:06 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 196K Apr 13 06:03 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 758K Apr 13 06:03 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 7.5K Apr 23 08:04 UpperBounds.txt
-rw-r--r-- 1 mcc users 17K Apr 23 08:04 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 8 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 255K May 18 16:43 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00
FORMULA_NAME UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01
FORMULA_NAME UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02
FORMULA_NAME UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03
FORMULA_NAME UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04
FORMULA_NAME UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05
FORMULA_NAME UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06
FORMULA_NAME UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07
FORMULA_NAME UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08
FORMULA_NAME UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09
FORMULA_NAME UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10
FORMULA_NAME UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11
FORMULA_NAME UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12
FORMULA_NAME UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13
FORMULA_NAME UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14
FORMULA_NAME UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15
=== Now, execution of the tool begins
BK_START 1717127154559
FORMULA UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_TIME_CONFINEMENT_REACHED
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLCardinality.xml[0m
[[35mlola[0m][I] LAUNCH task # 62 (type SKEL/FNDP) for 6 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 63 (type SKEL/EQUN) for 6 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 64 (type SKEL/SRCH) for 6 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] FINISHED task # 64 (type SKEL/SRCH) for UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 7
[[35mlola[0m][I] fired transitions : 6
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 62 (type FNDP) for UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02 (obsolete)
[[35mlola[0m][W] CANCELED task # 63 (type EQUN) for UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02 (obsolete)
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 65 (type SKEL/SRCH) for 6 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 65 (type SKEL/SRCH) for UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02
[[35mlola[0m][I] result : false
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] FINISHED task # 62 (type SKEL/FNDP) for UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[*** LOG ERROR #0001 ***] [2024-05-31 03:45:59] [status_logger] string pointer is null
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] FINISHED task # 63 (type SKEL/EQUN) for UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02
[[35mlola[0m][I] result : true
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 66 (type SKEL/SRCH) for 24 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 66 (type SKEL/SRCH) for UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04
[[35mlola[0m][I] result : true
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 67 (type SKEL/SRCH) for 27 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 67 (type SKEL/SRCH) for UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05
[[35mlola[0m][I] result : true
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 34 (type CNST) for 33 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 34 (type CNST) for UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 22 (type CNST) for 21 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] LAUNCH task # 52 (type CNST) for 51 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 22 (type CNST) for UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03
[[35mlola[0m][I] result : false
[[35mlola[0m][I] FINISHED task # 52 (type CNST) for UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13
[[35mlola[0m][I] result : false
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 71 (type EXCL) for 6 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02
[[35mlola[0m][I] time limit : 171 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 69 (type FNDP) for 6 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 70 (type EQUN) for 6 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 71 (type EXCL) for UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 7
[[35mlola[0m][I] fired transitions : 6
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 69 (type FNDP) for UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02 (obsolete)
[[35mlola[0m][W] CANCELED task # 70 (type EQUN) for UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02 (obsolete)
[[35mlola[0m][I] LAUNCH task # 25 (type EXCL) for 24 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04
[[35mlola[0m][I] time limit : 199 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 25 (type EXCL) for UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04
[[35mlola[0m][I] result : true
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] FINISHED task # 69 (type FNDP) for UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] LAUNCH task # 46 (type CNST) for 45 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 46 (type CNST) for UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 70 (type EQUN) for UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 19 (type EXCL) for 6 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02
[[35mlola[0m][I] time limit : 276 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 19 (type EXCL) for UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 67
[[35mlola[0m][I] fired transitions : 71
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 73 (type EXCL) for 48 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12
[[35mlola[0m][I] time limit : 326 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 82 (type EQUN) for 48 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] FINISHED task # 73 (type EXCL) for UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 43
[[35mlola[0m][I] fired transitions : 43
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 82 (type EQUN) for UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12 (obsolete)
[[35mlola[0m][I] LAUNCH task # 55 (type EXCL) for 54 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14
[[35mlola[0m][I] time limit : 399 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 55 (type EXCL) for UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 40
[[35mlola[0m][I] fired transitions : 40
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 43 (type EXCL) for 42 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10
[[35mlola[0m][I] time limit : 449 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 43 (type EXCL) for UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 39
[[35mlola[0m][I] fired transitions : 40
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 37 (type EXCL) for 36 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08
[[35mlola[0m][I] time limit : 513 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 37 (type EXCL) for UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 40
[[35mlola[0m][I] fired transitions : 120
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 31 (type EXCL) for 30 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06
[[35mlola[0m][I] time limit : 599 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 31 (type EXCL) for UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 40
[[35mlola[0m][I] fired transitions : 40
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 28 (type EXCL) for 27 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05
[[35mlola[0m][I] time limit : 718 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 28 (type EXCL) for UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05
[[35mlola[0m][I] result : true
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 4 (type EXCL) for 3 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01
[[35mlola[0m][I] time limit : 898 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 82 (type EQUN) for UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12
[[35mlola[0m][I] result : true
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 4/898 2/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 285909 m, 57181 m/sec, 947059 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 9/898 4/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 561051 m, 55028 m/sec, 1867501 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 15 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 14/898 6/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 852411 m, 58272 m/sec, 2858364 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 20 secs. Pages in use: 6
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 19/898 8/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 1136826 m, 56883 m/sec, 3861409 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 25 secs. Pages in use: 8
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 24/898 10/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 1381896 m, 49014 m/sec, 4743854 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 30 secs. Pages in use: 10
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 29/898 11/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 1630028 m, 49626 m/sec, 5649545 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 35 secs. Pages in use: 11
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 34/898 13/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 1907419 m, 55478 m/sec, 6584150 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 40 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 39/898 15/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 2169522 m, 52420 m/sec, 7537366 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 45 secs. Pages in use: 15
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 44/898 16/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 2420726 m, 50240 m/sec, 8468228 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 50 secs. Pages in use: 16
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 49/898 18/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 2679240 m, 51702 m/sec, 9428797 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 55 secs. Pages in use: 18
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 54/898 20/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 2924763 m, 49104 m/sec, 10338814 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 60 secs. Pages in use: 20
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 59/898 21/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 3174435 m, 49934 m/sec, 11273044 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 65 secs. Pages in use: 21
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 64/898 23/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 3463366 m, 57786 m/sec, 12253498 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 70 secs. Pages in use: 23
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 69/898 25/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 3714415 m, 50209 m/sec, 13207239 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 75 secs. Pages in use: 25
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 74/898 26/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 3970407 m, 51198 m/sec, 14156987 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 80 secs. Pages in use: 26
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 79/898 28/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 4227834 m, 51485 m/sec, 15113801 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 85 secs. Pages in use: 28
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 84/898 30/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 4475314 m, 49496 m/sec, 16060647 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 90 secs. Pages in use: 30
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 89/898 31/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 4721226 m, 49182 m/sec, 17006741 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 95 secs. Pages in use: 31
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 94/898 33/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 4969579 m, 49670 m/sec, 17950340 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 100 secs. Pages in use: 33
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 99/898 34/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 5224610 m, 51006 m/sec, 18902812 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 105 secs. Pages in use: 34
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 104/898 36/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 5467098 m, 48497 m/sec, 19839169 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 110 secs. Pages in use: 36
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 109/898 37/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 5708553 m, 48291 m/sec, 20783591 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 115 secs. Pages in use: 37
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 114/898 39/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 5949248 m, 48139 m/sec, 21728218 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 120 secs. Pages in use: 39
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 119/898 41/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 6192845 m, 48719 m/sec, 22674779 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 125 secs. Pages in use: 41
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 124/898 42/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 6445005 m, 50432 m/sec, 23625508 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 130 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 129/898 44/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 6685900 m, 48179 m/sec, 24562697 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 135 secs. Pages in use: 44
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 134/898 45/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 6924243 m, 47668 m/sec, 25501774 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 140 secs. Pages in use: 45
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 139/898 47/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 7166210 m, 48393 m/sec, 26436677 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 145 secs. Pages in use: 47
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 144/898 48/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 7422432 m, 51244 m/sec, 27378500 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 150 secs. Pages in use: 48
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 149/898 50/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 7662219 m, 47957 m/sec, 28313429 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 155 secs. Pages in use: 50
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 154/898 51/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 7902826 m, 48121 m/sec, 29244293 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 160 secs. Pages in use: 51
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 159/898 53/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 8145035 m, 48441 m/sec, 30184568 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 165 secs. Pages in use: 53
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 164/898 54/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 8381447 m, 47282 m/sec, 31119477 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 170 secs. Pages in use: 54
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 169/898 56/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 8618348 m, 47380 m/sec, 32049350 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 175 secs. Pages in use: 56
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 174/898 57/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 8852938 m, 46918 m/sec, 32982144 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 180 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 179/898 59/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 9073945 m, 44201 m/sec, 33863801 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 185 secs. Pages in use: 59
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 184/898 60/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 9313677 m, 47946 m/sec, 34779659 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 190 secs. Pages in use: 60
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 189/898 62/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 9551226 m, 47509 m/sec, 35712202 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 195 secs. Pages in use: 62
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 194/898 63/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 9800207 m, 49796 m/sec, 36629568 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 200 secs. Pages in use: 63
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 199/898 65/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 10035243 m, 47007 m/sec, 37559649 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 205 secs. Pages in use: 65
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 204/898 66/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 10285505 m, 50052 m/sec, 38489101 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 210 secs. Pages in use: 66
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 209/898 68/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 10517638 m, 46426 m/sec, 39416621 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 215 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 214/898 69/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 10749494 m, 46371 m/sec, 40342462 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 220 secs. Pages in use: 69
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 219/898 71/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 10981916 m, 46484 m/sec, 41261805 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 225 secs. Pages in use: 71
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 224/898 72/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 11210324 m, 45681 m/sec, 42164748 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 230 secs. Pages in use: 72
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 229/898 74/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 11443193 m, 46573 m/sec, 43073523 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 235 secs. Pages in use: 74
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 234/898 75/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 11674053 m, 46172 m/sec, 43992511 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 240 secs. Pages in use: 75
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 239/898 77/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 11899944 m, 45178 m/sec, 44870424 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 245 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 244/898 78/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 12139600 m, 47931 m/sec, 45787551 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 250 secs. Pages in use: 78
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 249/898 79/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 12367978 m, 45675 m/sec, 46699303 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 255 secs. Pages in use: 79
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 254/898 81/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 12602286 m, 46861 m/sec, 47616717 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 260 secs. Pages in use: 81
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 259/898 82/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 12833118 m, 46166 m/sec, 48526215 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 265 secs. Pages in use: 82
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 264/898 84/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 13062922 m, 45960 m/sec, 49425202 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 270 secs. Pages in use: 84
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 269/898 85/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 13275417 m, 42499 m/sec, 50279971 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 275 secs. Pages in use: 85
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 274/898 87/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 13508168 m, 46550 m/sec, 51155662 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 280 secs. Pages in use: 87
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 279/898 88/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 13736417 m, 45649 m/sec, 52035028 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 285 secs. Pages in use: 88
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 284/898 89/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 13958505 m, 44417 m/sec, 52923502 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 290 secs. Pages in use: 89
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 289/898 91/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 14180533 m, 44405 m/sec, 53813213 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 295 secs. Pages in use: 91
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 294/898 92/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 14397572 m, 43407 m/sec, 54700310 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 300 secs. Pages in use: 92
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 299/898 93/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 14626999 m, 45885 m/sec, 55594868 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 305 secs. Pages in use: 93
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 304/898 95/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 14855329 m, 45666 m/sec, 56475740 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 310 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 309/898 96/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 15074451 m, 43824 m/sec, 57358868 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 315 secs. Pages in use: 96
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 314/898 98/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 15304709 m, 46051 m/sec, 58243340 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 320 secs. Pages in use: 98
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 319/898 99/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 15524481 m, 43954 m/sec, 59120387 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 325 secs. Pages in use: 99
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 324/898 100/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 15749056 m, 44915 m/sec, 59999781 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 330 secs. Pages in use: 100
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 329/898 102/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 15967413 m, 43671 m/sec, 60882264 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 335 secs. Pages in use: 102
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 334/898 103/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 16191755 m, 44868 m/sec, 61760569 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 340 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 339/898 105/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 16411639 m, 43976 m/sec, 62622059 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 345 secs. Pages in use: 105
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 344/898 106/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 16628329 m, 43338 m/sec, 63494617 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 350 secs. Pages in use: 106
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 349/898 107/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 16855249 m, 45384 m/sec, 64372693 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 355 secs. Pages in use: 107
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 354/898 109/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 17076420 m, 44234 m/sec, 65244096 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 360 secs. Pages in use: 109
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 359/898 110/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 17294097 m, 43535 m/sec, 66109014 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 365 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 364/898 111/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 17508932 m, 42967 m/sec, 66979148 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 370 secs. Pages in use: 111
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 369/898 113/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 17726924 m, 43598 m/sec, 67849897 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 375 secs. Pages in use: 113
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 374/898 114/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 17949690 m, 44553 m/sec, 68728287 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 380 secs. Pages in use: 114
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 379/898 115/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 18164665 m, 42995 m/sec, 69598775 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 385 secs. Pages in use: 115
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 384/898 117/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 18391704 m, 45407 m/sec, 70472226 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 390 secs. Pages in use: 117
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 389/898 118/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 18611374 m, 43934 m/sec, 71346916 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 395 secs. Pages in use: 118
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 394/898 120/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 18829007 m, 43526 m/sec, 72215900 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 400 secs. Pages in use: 120
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 399/898 121/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 19041861 m, 42570 m/sec, 73076219 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 405 secs. Pages in use: 121
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 404/898 122/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 19256282 m, 42884 m/sec, 73939208 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 410 secs. Pages in use: 122
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 409/898 124/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 19470253 m, 42794 m/sec, 74797621 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 415 secs. Pages in use: 124
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 414/898 125/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 19686189 m, 43187 m/sec, 75664244 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 420 secs. Pages in use: 125
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 419/898 126/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 19901713 m, 43104 m/sec, 76534269 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 425 secs. Pages in use: 126
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 424/898 128/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 20118048 m, 43267 m/sec, 77396700 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 430 secs. Pages in use: 128
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 429/898 129/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 20334160 m, 43222 m/sec, 78254174 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 435 secs. Pages in use: 129
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 434/898 130/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 20543809 m, 41929 m/sec, 79121526 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 440 secs. Pages in use: 130
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 439/898 132/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 20760974 m, 43433 m/sec, 79980365 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 445 secs. Pages in use: 132
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 444/898 133/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 20970504 m, 41906 m/sec, 80844591 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 450 secs. Pages in use: 133
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 449/898 134/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 21181048 m, 42108 m/sec, 81709308 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 455 secs. Pages in use: 134
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 454/898 136/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 21396505 m, 43091 m/sec, 82565765 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 460 secs. Pages in use: 136
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 459/898 137/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 21613342 m, 43367 m/sec, 83427750 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 465 secs. Pages in use: 137
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 464/898 138/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 21826028 m, 42537 m/sec, 84285079 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 470 secs. Pages in use: 138
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 469/898 139/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 22042159 m, 43226 m/sec, 85145948 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 475 secs. Pages in use: 139
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 474/898 141/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 22262023 m, 43972 m/sec, 86020818 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 480 secs. Pages in use: 141
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 479/898 142/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 22481941 m, 43983 m/sec, 86892454 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 485 secs. Pages in use: 142
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 484/898 143/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 22690243 m, 41660 m/sec, 87744224 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 490 secs. Pages in use: 143
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 489/898 145/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 22900246 m, 42000 m/sec, 88601532 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 495 secs. Pages in use: 145
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 494/898 146/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 23116469 m, 43244 m/sec, 89467922 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 500 secs. Pages in use: 146
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 499/898 147/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 23334142 m, 43534 m/sec, 90318611 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 505 secs. Pages in use: 147
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 504/898 149/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 23543783 m, 41928 m/sec, 91178523 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 510 secs. Pages in use: 149
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 509/898 150/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 23751022 m, 41447 m/sec, 92029236 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 515 secs. Pages in use: 150
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 514/898 151/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 23958980 m, 41591 m/sec, 92876771 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 520 secs. Pages in use: 151
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 519/898 153/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 24167976 m, 41799 m/sec, 93726028 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 525 secs. Pages in use: 153
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 524/898 154/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 24387323 m, 43869 m/sec, 94580648 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 530 secs. Pages in use: 154
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 529/898 155/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 24598092 m, 42153 m/sec, 95428951 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 535 secs. Pages in use: 155
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 534/898 156/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 24806332 m, 41648 m/sec, 96283320 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 540 secs. Pages in use: 156
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 539/898 158/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 25013883 m, 41510 m/sec, 97126676 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 545 secs. Pages in use: 158
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 544/898 159/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 25224180 m, 42059 m/sec, 97985602 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 550 secs. Pages in use: 159
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 549/898 160/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 25438129 m, 42789 m/sec, 98836813 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 555 secs. Pages in use: 160
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 554/898 162/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 25648792 m, 42132 m/sec, 99684876 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 560 secs. Pages in use: 162
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 559/898 163/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 25854835 m, 41208 m/sec, 100533346 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 565 secs. Pages in use: 163
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 564/898 164/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 26061234 m, 41279 m/sec, 101376088 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 570 secs. Pages in use: 164
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 569/898 165/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 26269617 m, 41676 m/sec, 102223050 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 575 secs. Pages in use: 165
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 574/898 167/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 26477961 m, 41668 m/sec, 103069039 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 580 secs. Pages in use: 167
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 579/898 168/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 26688299 m, 42067 m/sec, 103917536 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 585 secs. Pages in use: 168
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 584/898 169/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 26901664 m, 42673 m/sec, 104761577 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 590 secs. Pages in use: 169
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 589/898 171/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 27104899 m, 40647 m/sec, 105605067 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 595 secs. Pages in use: 171
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 594/898 172/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 27313032 m, 41626 m/sec, 106451673 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 600 secs. Pages in use: 172
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 599/898 173/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 27522417 m, 41877 m/sec, 107287275 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 605 secs. Pages in use: 173
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 604/898 174/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 27727134 m, 40943 m/sec, 108133189 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 610 secs. Pages in use: 174
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 609/898 176/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 27936021 m, 41777 m/sec, 108967819 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 615 secs. Pages in use: 176
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 614/898 177/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 28140448 m, 40885 m/sec, 109802174 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 620 secs. Pages in use: 177
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 619/898 178/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 28352702 m, 42450 m/sec, 110627423 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 625 secs. Pages in use: 178
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 624/898 179/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 28565871 m, 42633 m/sec, 111478727 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 630 secs. Pages in use: 179
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 629/898 181/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 28770237 m, 40873 m/sec, 112322394 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 635 secs. Pages in use: 181
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 634/898 182/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 28980480 m, 42048 m/sec, 113167072 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 640 secs. Pages in use: 182
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 639/898 183/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 29184392 m, 40782 m/sec, 113998070 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 645 secs. Pages in use: 183
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 644/898 185/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 29397341 m, 42589 m/sec, 114849175 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 650 secs. Pages in use: 185
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 649/898 186/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 29609238 m, 42379 m/sec, 115687870 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 655 secs. Pages in use: 186
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 654/898 187/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 29812801 m, 40712 m/sec, 116527923 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 660 secs. Pages in use: 187
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 659/898 188/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 30024683 m, 42376 m/sec, 117386776 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 665 secs. Pages in use: 188
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 664/898 190/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 30228512 m, 40765 m/sec, 118225452 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 670 secs. Pages in use: 190
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 669/898 191/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 30435692 m, 41436 m/sec, 119057769 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 675 secs. Pages in use: 191
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 674/898 192/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 30654373 m, 43736 m/sec, 119917118 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 680 secs. Pages in use: 192
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 679/898 194/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 30856245 m, 40374 m/sec, 120722659 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 685 secs. Pages in use: 194
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 684/898 195/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 31049414 m, 38633 m/sec, 121516953 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 690 secs. Pages in use: 195
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 689/898 196/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 31248079 m, 39733 m/sec, 122314267 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 695 secs. Pages in use: 196
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 694/898 197/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 31441085 m, 38601 m/sec, 123104478 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 700 secs. Pages in use: 197
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 699/898 198/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 31637388 m, 39260 m/sec, 123906249 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 705 secs. Pages in use: 198
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 704/898 200/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 31831630 m, 38848 m/sec, 124702068 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 710 secs. Pages in use: 200
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 709/898 201/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 32031373 m, 39948 m/sec, 125485100 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 715 secs. Pages in use: 201
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 714/898 202/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 32227203 m, 39166 m/sec, 126273742 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 720 secs. Pages in use: 202
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 719/898 203/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 32419998 m, 38559 m/sec, 127060310 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 725 secs. Pages in use: 203
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 724/898 204/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 32610042 m, 38008 m/sec, 127861229 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 730 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 729/898 205/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 32803446 m, 38680 m/sec, 128653423 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 735 secs. Pages in use: 205
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 734/898 207/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 32997247 m, 38760 m/sec, 129451535 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 740 secs. Pages in use: 207
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 739/898 208/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 33191452 m, 38841 m/sec, 130237469 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 745 secs. Pages in use: 208
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 744/898 209/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 33382627 m, 38235 m/sec, 131022090 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 750 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 749/898 210/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 33573896 m, 38253 m/sec, 131807650 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 755 secs. Pages in use: 210
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 754/898 211/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 33766831 m, 38587 m/sec, 132592823 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 760 secs. Pages in use: 211
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 759/898 212/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 33957870 m, 38207 m/sec, 133390036 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 765 secs. Pages in use: 212
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 764/898 214/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 34150932 m, 38612 m/sec, 134169525 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 770 secs. Pages in use: 214
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 769/898 215/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 34344741 m, 38761 m/sec, 134965321 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 775 secs. Pages in use: 215
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 774/898 216/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 34536720 m, 38395 m/sec, 135746244 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 780 secs. Pages in use: 216
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 779/898 217/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 34726763 m, 38008 m/sec, 136531611 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 785 secs. Pages in use: 217
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 784/898 218/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 34917650 m, 38177 m/sec, 137316412 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 790 secs. Pages in use: 218
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 789/898 219/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 35105593 m, 37588 m/sec, 138097713 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 795 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 794/898 221/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 35294050 m, 37691 m/sec, 138880112 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 800 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 799/898 222/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 35482781 m, 37746 m/sec, 139661374 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 805 secs. Pages in use: 222
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 804/898 223/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 35671540 m, 37751 m/sec, 140444633 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 810 secs. Pages in use: 223
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 809/898 224/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 35871154 m, 39922 m/sec, 141238382 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 815 secs. Pages in use: 224
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 814/898 225/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 36067953 m, 39359 m/sec, 142034683 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 820 secs. Pages in use: 225
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 819/898 226/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 36256071 m, 37623 m/sec, 142810860 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 825 secs. Pages in use: 226
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 824/898 228/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 36446549 m, 38095 m/sec, 143588298 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 830 secs. Pages in use: 228
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 829/898 229/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 36635641 m, 37818 m/sec, 144365788 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 835 secs. Pages in use: 229
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 834/898 230/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 36818880 m, 36647 m/sec, 145120924 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 840 secs. Pages in use: 230
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 839/898 231/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 37008260 m, 37876 m/sec, 145904796 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 845 secs. Pages in use: 231
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 844/898 232/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 37214661 m, 41280 m/sec, 146684735 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 850 secs. Pages in use: 232
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 849/898 233/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 37402902 m, 37648 m/sec, 147458008 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 855 secs. Pages in use: 233
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 854/898 235/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 37598140 m, 39047 m/sec, 148236660 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 860 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 859/898 236/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 37790269 m, 38425 m/sec, 149027686 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 865 secs. Pages in use: 236
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 864/898 237/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 37980359 m, 38018 m/sec, 149809317 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 870 secs. Pages in use: 237
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 869/898 238/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 38170273 m, 37982 m/sec, 150582215 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 875 secs. Pages in use: 238
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 874/898 239/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 38356590 m, 37263 m/sec, 151348763 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 880 secs. Pages in use: 239
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 879/898 240/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 38543289 m, 37339 m/sec, 152124677 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 885 secs. Pages in use: 240
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 884/898 241/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 38733424 m, 38027 m/sec, 152897634 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 890 secs. Pages in use: 241
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 889/898 243/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 38932960 m, 39907 m/sec, 153697764 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 895 secs. Pages in use: 243
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 894/898 244/2000 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 39120414 m, 37490 m/sec, 154480246 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 900 secs. Pages in use: 244
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 4 (type EXCL) for UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 905 secs. Pages in use: 245
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 40 (type EXCL) for 39 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09
[[35mlola[0m][I] time limit : 898 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 4 (type EXCL) for 3 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01
[[35mlola[0m][I] time limit : 2695 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 40 (type EXCL) for UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 221
[[35mlola[0m][I] fired transitions : 244
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 5/898 3/5 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 311263 m, -7761830 m/sec, 1024470 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 910 secs. Pages in use: 248
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 10/898 5/5 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 582294 m, 54206 m/sec, 1941084 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 915 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 4 (type EXCL) for UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 920 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 1 (type EXCL) for 0 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00
[[35mlola[0m][I] time limit : 1340 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 1 (type EXCL) for UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 223
[[35mlola[0m][I] fired transitions : 239
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 58 (type EXCL) for 57 UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15
[[35mlola[0m][I] time limit : 2680 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 58 (type EXCL) for UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 74
[[35mlola[0m][I] fired transitions : 118
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 925 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 930 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 935 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 940 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 945 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 950 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 955 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 960 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 965 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 970 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 975 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 980 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 985 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 990 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 995 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1000 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1005 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1010 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1015 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1020 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1025 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1030 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1035 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1040 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1045 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1050 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1055 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1060 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1065 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1070 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1075 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1080 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1085 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1090 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1095 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1100 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1105 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1110 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1115 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1120 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1125 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1130 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1135 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1140 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1145 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1150 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1155 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1160 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1165 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1170 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1175 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1180 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1185 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1190 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1195 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1200 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1205 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1210 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1215 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1220 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1225 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1230 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1235 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1240 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1245 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1250 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1255 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1260 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1265 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1270 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1275 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1280 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1285 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1290 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1295 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1300 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1305 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1310 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1315 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1320 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1325 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1330 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1335 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1340 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1345 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1350 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1355 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1360 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1365 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1370 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1375 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1380 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1385 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1390 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1395 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1400 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1405 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1410 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1415 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1420 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1425 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1430 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1435 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1440 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1445 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1450 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1455 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1460 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1465 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1470 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1475 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1480 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1485 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1490 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1495 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1500 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1505 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1510 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1515 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1520 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1525 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1530 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1535 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1540 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1545 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1550 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1555 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1560 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1565 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1570 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1575 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1580 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1585 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1590 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1595 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1600 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1605 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1610 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1615 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1620 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1625 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1630 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1635 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1640 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1645 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1650 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1655 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1660 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1665 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1670 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1675 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1680 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1685 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1690 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1695 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1700 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1705 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1710 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1715 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1720 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1725 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1730 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1735 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1740 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1745 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1750 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1755 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1760 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1766 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1771 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1776 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1781 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1786 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1791 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1796 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1801 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1806 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1811 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1816 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1821 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1826 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1831 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1836 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1841 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1846 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1851 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1856 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1861 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1866 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1871 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1876 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1881 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1886 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1891 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1896 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1901 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1906 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1911 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1916 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-02: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-12: EG true state space / EG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N08-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1921 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
========== file over 1MB has been truncated ======
retrieve it from the run archives if needed
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="UtilityControlRoom-PT-Z4T4N08"
export BK_EXAMINATION="CTLCardinality"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is UtilityControlRoom-PT-Z4T4N08, examination is CTLCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r445-smll-171701112200265"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/UtilityControlRoom-PT-Z4T4N08.tgz
mv UtilityControlRoom-PT-Z4T4N08 execution
cd execution
if [ "CTLCardinality" = "ReachabilityDeadlock" ] || [ "CTLCardinality" = "UpperBounds" ] || [ "CTLCardinality" = "QuasiLiveness" ] || [ "CTLCardinality" = "StableMarking" ] || [ "CTLCardinality" = "Liveness" ] || [ "CTLCardinality" = "OneSafe" ] || [ "CTLCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLCardinality" = "ReachabilityDeadlock" ] || [ "CTLCardinality" = "QuasiLiveness" ] || [ "CTLCardinality" = "StableMarking" ] || [ "CTLCardinality" = "Liveness" ] || [ "CTLCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;