About the Execution of LoLA for UtilityControlRoom-PT-Z4T4N06
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 9148.896 | 3600000.00 | 753826.00 | 9470.90 | F?TF?F?????F?F?F | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r445-smll-171701112200260.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is UtilityControlRoom-PT-Z4T4N06, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r445-smll-171701112200260
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 2.3M
-rw-r--r-- 1 mcc users 34K Apr 13 05:25 CTLCardinality.txt
-rw-r--r-- 1 mcc users 173K Apr 13 05:25 CTLCardinality.xml
-rw-r--r-- 1 mcc users 73K Apr 13 05:21 CTLFireability.txt
-rw-r--r-- 1 mcc users 292K Apr 13 05:21 CTLFireability.xml
-rw-r--r-- 1 mcc users 26K Apr 23 08:04 LTLCardinality.txt
-rw-r--r-- 1 mcc users 87K Apr 23 08:04 LTLCardinality.xml
-rw-r--r-- 1 mcc users 21K Apr 23 08:04 LTLFireability.txt
-rw-r--r-- 1 mcc users 64K Apr 23 08:04 LTLFireability.xml
-rw-r--r-- 1 mcc users 84K Apr 13 05:41 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 433K Apr 13 05:41 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 170K Apr 13 05:37 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 636K Apr 13 05:37 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 4.1K Apr 23 08:04 UpperBounds.txt
-rw-r--r-- 1 mcc users 8.8K Apr 23 08:04 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 8 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 191K May 18 16:43 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME UtilityControlRoom-PT-Z4T4N06-LTLFireability-00
FORMULA_NAME UtilityControlRoom-PT-Z4T4N06-LTLFireability-01
FORMULA_NAME UtilityControlRoom-PT-Z4T4N06-LTLFireability-02
FORMULA_NAME UtilityControlRoom-PT-Z4T4N06-LTLFireability-03
FORMULA_NAME UtilityControlRoom-PT-Z4T4N06-LTLFireability-04
FORMULA_NAME UtilityControlRoom-PT-Z4T4N06-LTLFireability-05
FORMULA_NAME UtilityControlRoom-PT-Z4T4N06-LTLFireability-06
FORMULA_NAME UtilityControlRoom-PT-Z4T4N06-LTLFireability-07
FORMULA_NAME UtilityControlRoom-PT-Z4T4N06-LTLFireability-08
FORMULA_NAME UtilityControlRoom-PT-Z4T4N06-LTLFireability-09
FORMULA_NAME UtilityControlRoom-PT-Z4T4N06-LTLFireability-10
FORMULA_NAME UtilityControlRoom-PT-Z4T4N06-LTLFireability-11
FORMULA_NAME UtilityControlRoom-PT-Z4T4N06-LTLFireability-12
FORMULA_NAME UtilityControlRoom-PT-Z4T4N06-LTLFireability-13
FORMULA_NAME UtilityControlRoom-PT-Z4T4N06-LTLFireability-14
FORMULA_NAME UtilityControlRoom-PT-Z4T4N06-LTLFireability-15
=== Now, execution of the tool begins
BK_START 1717123816985
FORMULA UtilityControlRoom-PT-Z4T4N06-LTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T4N06-LTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T4N06-LTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T4N06-LTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T4N06-LTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T4N06-LTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T4N06-LTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_TIME_CONFINEMENT_REACHED
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mLTLFireability.xml[0m
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 36 (type CNST) for 33 UtilityControlRoom-PT-Z4T4N06-LTLFireability-11
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 36 (type CNST) for UtilityControlRoom-PT-Z4T4N06-LTLFireability-11
[[35mlola[0m][I] result : false
[*** LOG ERROR #0001 ***] [2024-05-31 02:50:17] [status_logger] string pointer is null
[[35mlola[0m][I] LAUNCH task # 10 (type EXCL) for 9 UtilityControlRoom-PT-Z4T4N06-LTLFireability-03
[[35mlola[0m][I] time limit : 138 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 10 (type EXCL) for UtilityControlRoom-PT-Z4T4N06-LTLFireability-03
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 46
[[35mlola[0m][I] fired transitions : 47
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 46 (type CNST) for 43 UtilityControlRoom-PT-Z4T4N06-LTLFireability-13
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 46 (type CNST) for UtilityControlRoom-PT-Z4T4N06-LTLFireability-13
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 1 (type EXCL) for 0 UtilityControlRoom-PT-Z4T4N06-LTLFireability-00
[[35mlola[0m][I] time limit : 200 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] FINISHED task # 1 (type EXCL) for UtilityControlRoom-PT-Z4T4N06-LTLFireability-00
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 24
[[35mlola[0m][I] fired transitions : 24
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 16 (type EXCL) for 15 UtilityControlRoom-PT-Z4T4N06-LTLFireability-05
[[35mlola[0m][I] time limit : 211 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 16 (type EXCL) for UtilityControlRoom-PT-Z4T4N06-LTLFireability-05
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 24
[[35mlola[0m][I] fired transitions : 25
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 61 (type EXCL) for 6 UtilityControlRoom-PT-Z4T4N06-LTLFireability-02
[[35mlola[0m][I] time limit : 225 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 64 (type EQUN) for 6 UtilityControlRoom-PT-Z4T4N06-LTLFireability-02
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] FINISHED task # 61 (type EXCL) for UtilityControlRoom-PT-Z4T4N06-LTLFireability-02
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 64
[[35mlola[0m][I] fired transitions : 192
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 64 (type EQUN) for UtilityControlRoom-PT-Z4T4N06-LTLFireability-02 (obsolete)
[[35mlola[0m][I] LAUNCH task # 58 (type EXCL) for 53 UtilityControlRoom-PT-Z4T4N06-LTLFireability-15
[[35mlola[0m][I] time limit : 327 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 58 (type EXCL) for UtilityControlRoom-PT-Z4T4N06-LTLFireability-15
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 24
[[35mlola[0m][I] fired transitions : 24
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 41 (type EXCL) for 40 UtilityControlRoom-PT-Z4T4N06-LTLFireability-12
[[35mlola[0m][I] time limit : 400 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 64 (type EQUN) for UtilityControlRoom-PT-Z4T4N06-LTLFireability-02
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 41 (type EXCL) for UtilityControlRoom-PT-Z4T4N06-LTLFireability-12
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 211614
[[35mlola[0m][I] fired transitions : 460781
[[35mlola[0m][I] time used : 2
[[35mlola[0m][I] memory pages used : 2
[[35mlola[0m][I] LAUNCH task # 31 (type EXCL) for 30 UtilityControlRoom-PT-Z4T4N06-LTLFireability-10
[[35mlola[0m][I] time limit : 449 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 31 (type EXCL) for UtilityControlRoom-PT-Z4T4N06-LTLFireability-10
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 28
[[35mlola[0m][I] fired transitions : 28
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 28 (type EXCL) for 27 UtilityControlRoom-PT-Z4T4N06-LTLFireability-09
[[35mlola[0m][I] time limit : 514 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 28 (type EXCL) for UtilityControlRoom-PT-Z4T4N06-LTLFireability-09
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 24
[[35mlola[0m][I] fired transitions : 24
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 25 (type EXCL) for 24 UtilityControlRoom-PT-Z4T4N06-LTLFireability-08
[[35mlola[0m][I] time limit : 599 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 25 (type EXCL) for UtilityControlRoom-PT-Z4T4N06-LTLFireability-08
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 25
[[35mlola[0m][I] fired transitions : 24
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 22 (type EXCL) for 21 UtilityControlRoom-PT-Z4T4N06-LTLFireability-07
[[35mlola[0m][I] time limit : 719 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N06-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N06-LTLFireability-02: AU true state space /ER[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N06-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N06-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N06-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N06-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N06-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N06-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N06-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N06-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N06-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N06-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N06-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N06-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N06-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N06-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 3/719 4/2000 UtilityControlRoom-PT-Z4T4N06-LTLFireability-07 472597 m, 94519 m/sec, 1022509 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N06-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N06-LTLFireability-02: AU true state space /ER[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N06-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N06-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N06-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N06-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N06-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N06-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N06-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N06-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N06-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N06-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N06-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N06-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N06-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N06-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 8/719 8/2000 UtilityControlRoom-PT-Z4T4N06-LTLFireability-07 1179585 m, 141397 m/sec, 2606070 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs. Pages in use: 8
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N06-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N06-LTLFireability-02: AU true state space /ER[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N06-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N06-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N06-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N06-LTLFireability-09: LTL false LTL model checker[0m
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========== file over 1MB has been truncated ======
retrieve it from the run archives if needed
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="UtilityControlRoom-PT-Z4T4N06"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is UtilityControlRoom-PT-Z4T4N06, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r445-smll-171701112200260"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/UtilityControlRoom-PT-Z4T4N06.tgz
mv UtilityControlRoom-PT-Z4T4N06 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;