About the Execution of LoLA for UtilityControlRoom-PT-Z4T4N04
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 2482.027 | 215964.00 | 217605.00 | 673.00 | TTFFTTFFFFTFTFFF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r445-smll-171701112100252.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
....................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is UtilityControlRoom-PT-Z4T4N04, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r445-smll-171701112100252
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.7M
-rw-r--r-- 1 mcc users 27K Apr 13 05:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 153K Apr 13 05:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 52K Apr 13 05:19 CTLFireability.txt
-rw-r--r-- 1 mcc users 220K Apr 13 05:19 CTLFireability.xml
-rw-r--r-- 1 mcc users 15K Apr 23 08:04 LTLCardinality.txt
-rw-r--r-- 1 mcc users 55K Apr 23 08:04 LTLCardinality.xml
-rw-r--r-- 1 mcc users 13K Apr 23 08:04 LTLFireability.txt
-rw-r--r-- 1 mcc users 46K Apr 23 08:04 LTLFireability.xml
-rw-r--r-- 1 mcc users 59K Apr 13 05:32 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 321K Apr 13 05:32 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 103K Apr 13 05:29 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 406K Apr 13 05:29 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 3.8K Apr 23 08:04 UpperBounds.txt
-rw-r--r-- 1 mcc users 8.3K Apr 23 08:04 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 8 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 128K May 18 16:43 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME UtilityControlRoom-PT-Z4T4N04-LTLFireability-00
FORMULA_NAME UtilityControlRoom-PT-Z4T4N04-LTLFireability-01
FORMULA_NAME UtilityControlRoom-PT-Z4T4N04-LTLFireability-02
FORMULA_NAME UtilityControlRoom-PT-Z4T4N04-LTLFireability-03
FORMULA_NAME UtilityControlRoom-PT-Z4T4N04-LTLFireability-04
FORMULA_NAME UtilityControlRoom-PT-Z4T4N04-LTLFireability-05
FORMULA_NAME UtilityControlRoom-PT-Z4T4N04-LTLFireability-06
FORMULA_NAME UtilityControlRoom-PT-Z4T4N04-LTLFireability-07
FORMULA_NAME UtilityControlRoom-PT-Z4T4N04-LTLFireability-08
FORMULA_NAME UtilityControlRoom-PT-Z4T4N04-LTLFireability-09
FORMULA_NAME UtilityControlRoom-PT-Z4T4N04-LTLFireability-10
FORMULA_NAME UtilityControlRoom-PT-Z4T4N04-LTLFireability-11
FORMULA_NAME UtilityControlRoom-PT-Z4T4N04-LTLFireability-12
FORMULA_NAME UtilityControlRoom-PT-Z4T4N04-LTLFireability-13
FORMULA_NAME UtilityControlRoom-PT-Z4T4N04-LTLFireability-14
FORMULA_NAME UtilityControlRoom-PT-Z4T4N04-LTLFireability-15
=== Now, execution of the tool begins
BK_START 1717120332972
FORMULA UtilityControlRoom-PT-Z4T4N04-LTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T4N04-LTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T4N04-LTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T4N04-LTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T4N04-LTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T4N04-LTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T4N04-LTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T4N04-LTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T4N04-LTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T4N04-LTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T4N04-LTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T4N04-LTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T4N04-LTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T4N04-LTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T4N04-LTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T4N04-LTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[[35mlola[0m] [1mFINAL RESULTS[0m
[[35mlola[0m] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m] [1m[32mUtilityControlRoom-PT-Z4T4N04-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m] [1m[32mUtilityControlRoom-PT-Z4T4N04-LTLFireability-01: AR true skeleton: state space /EU[0m
[[35mlola[0m] [1m[31mUtilityControlRoom-PT-Z4T4N04-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mUtilityControlRoom-PT-Z4T4N04-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m] [1m[32mUtilityControlRoom-PT-Z4T4N04-LTLFireability-04: LTL true LTL model checker[0m
[[35mlola[0m] [1m[32mUtilityControlRoom-PT-Z4T4N04-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m] [1m[31mUtilityControlRoom-PT-Z4T4N04-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mUtilityControlRoom-PT-Z4T4N04-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mUtilityControlRoom-PT-Z4T4N04-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mUtilityControlRoom-PT-Z4T4N04-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m] [1m[32mUtilityControlRoom-PT-Z4T4N04-LTLFireability-10: CONJ true CONJ[0m
[[35mlola[0m] [1m[31mUtilityControlRoom-PT-Z4T4N04-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m] [1m[32mUtilityControlRoom-PT-Z4T4N04-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m] [1m[31mUtilityControlRoom-PT-Z4T4N04-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mUtilityControlRoom-PT-Z4T4N04-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m] [1m[31mUtilityControlRoom-PT-Z4T4N04-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m]
[[35mlola[0m] Time elapsed: 215 secs. Pages in use: 82
BK_STOP 1717120548936
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mLTLFireability.xml[0m
[[35mlola[0m][I] LAUNCH task # 60 (type SKEL/EQUN) for 3 UtilityControlRoom-PT-Z4T4N04-LTLFireability-01
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 58 (type SKEL/SRCH) for 3 UtilityControlRoom-PT-Z4T4N04-LTLFireability-01
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 58 (type SKEL/SRCH) for UtilityControlRoom-PT-Z4T4N04-LTLFireability-01
[[35mlola[0m][I] result : false
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 60 (type EQUN) for UtilityControlRoom-PT-Z4T4N04-LTLFireability-01 (obsolete)
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] FINISHED task # 60 (type SKEL/EQUN) for UtilityControlRoom-PT-Z4T4N04-LTLFireability-01
[[35mlola[0m][I] result : true
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] planning for UtilityControlRoom-PT-Z4T4N04-LTLFireability-01 stopped (result already fixed).
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 25 (type EXCL) for 24 UtilityControlRoom-PT-Z4T4N04-LTLFireability-08
[[35mlola[0m][I] time limit : 211 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 25 (type EXCL) for UtilityControlRoom-PT-Z4T4N04-LTLFireability-08
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 30
[[35mlola[0m][I] fired transitions : 30
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 54 (type EXCL) for 53 UtilityControlRoom-PT-Z4T4N04-LTLFireability-15
[[35mlola[0m][I] time limit : 225 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 54 (type EXCL) for UtilityControlRoom-PT-Z4T4N04-LTLFireability-15
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 20
[[35mlola[0m][I] fired transitions : 20
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 48 (type EXCL) for 47 UtilityControlRoom-PT-Z4T4N04-LTLFireability-13
[[35mlola[0m][I] time limit : 240 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 65 (type EQUN) for 50 UtilityControlRoom-PT-Z4T4N04-LTLFireability-14
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 48 (type EXCL) for UtilityControlRoom-PT-Z4T4N04-LTLFireability-13
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 20
[[35mlola[0m][I] fired transitions : 20
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 45 (type EXCL) for 44 UtilityControlRoom-PT-Z4T4N04-LTLFireability-12
[[35mlola[0m][I] time limit : 257 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 45 (type EXCL) for UtilityControlRoom-PT-Z4T4N04-LTLFireability-12
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 5
[[35mlola[0m][I] fired transitions : 4
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 42 (type EXCL) for 37 UtilityControlRoom-PT-Z4T4N04-LTLFireability-11
[[35mlola[0m][I] time limit : 276 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 42 (type EXCL) for UtilityControlRoom-PT-Z4T4N04-LTLFireability-11
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 24
[[35mlola[0m][I] fired transitions : 24
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 35 (type EXCL) for 30 UtilityControlRoom-PT-Z4T4N04-LTLFireability-10
[[35mlola[0m][I] time limit : 327 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 35 (type EXCL) for UtilityControlRoom-PT-Z4T4N04-LTLFireability-10
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 33 (type EXCL) for 30 UtilityControlRoom-PT-Z4T4N04-LTLFireability-10
[[35mlola[0m][I] time limit : 360 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 33 (type EXCL) for UtilityControlRoom-PT-Z4T4N04-LTLFireability-10
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 28 (type EXCL) for 27 UtilityControlRoom-PT-Z4T4N04-LTLFireability-09
[[35mlola[0m][I] time limit : 400 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 28 (type EXCL) for UtilityControlRoom-PT-Z4T4N04-LTLFireability-09
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 41
[[35mlola[0m][I] fired transitions : 42
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 22 (type EXCL) for 21 UtilityControlRoom-PT-Z4T4N04-LTLFireability-07
[[35mlola[0m][I] time limit : 450 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 22 (type EXCL) for UtilityControlRoom-PT-Z4T4N04-LTLFireability-07
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 20
[[35mlola[0m][I] fired transitions : 20
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 19 (type EXCL) for 18 UtilityControlRoom-PT-Z4T4N04-LTLFireability-06
[[35mlola[0m][I] time limit : 514 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 19 (type EXCL) for UtilityControlRoom-PT-Z4T4N04-LTLFireability-06
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 187
[[35mlola[0m][I] fired transitions : 303
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 13 (type EXCL) for 12 UtilityControlRoom-PT-Z4T4N04-LTLFireability-04
[[35mlola[0m][I] time limit : 600 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 65 (type EQUN) for UtilityControlRoom-PT-Z4T4N04-LTLFireability-14
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 13 (type EXCL) for UtilityControlRoom-PT-Z4T4N04-LTLFireability-04
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 2224
[[35mlola[0m][I] fired transitions : 2652
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 10 (type EXCL) for 9 UtilityControlRoom-PT-Z4T4N04-LTLFireability-03
[[35mlola[0m][I] time limit : 720 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 10 (type EXCL) for UtilityControlRoom-PT-Z4T4N04-LTLFireability-03
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 307
[[35mlola[0m][I] fired transitions : 489
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 7 (type EXCL) for 6 UtilityControlRoom-PT-Z4T4N04-LTLFireability-02
[[35mlola[0m][I] time limit : 900 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 7 (type EXCL) for UtilityControlRoom-PT-Z4T4N04-LTLFireability-02
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 20
[[35mlola[0m][I] fired transitions : 20
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 1 (type EXCL) for 0 UtilityControlRoom-PT-Z4T4N04-LTLFireability-00
[[35mlola[0m][I] time limit : 1200 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N04-LTLFireability-01: AR true skeleton: state space /EU[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N04-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N04-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N04-LTLFireability-04: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N04-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N04-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N04-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N04-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N04-LTLFireability-10: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N04-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N04-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N04-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N04-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N04-LTLFireability-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N04-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T4N04-LTLFireability-14: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 5/1200 6/2000 UtilityControlRoom-PT-Z4T4N04-LTLFireability-00 719380 m, 143876 m/sec, 1380010 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs. Pages in use: 6
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N04-LTLFireability-01: AR true skeleton: state space /EU[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N04-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T4N04-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T4N04-LTLFireability-04: LTL true LTL model checker[0m
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[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 12766169
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[[35mlola[0m][I] Portfolio finished: no open formulas
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="UtilityControlRoom-PT-Z4T4N04"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is UtilityControlRoom-PT-Z4T4N04, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r445-smll-171701112100252"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/UtilityControlRoom-PT-Z4T4N04.tgz
mv UtilityControlRoom-PT-Z4T4N04 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;