About the Execution of LoLA for UtilityControlRoom-PT-Z4T4N02
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 173.056 | 2569.00 | 2389.00 | 40.10 | TTFTFTTFTFFFFFFF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r445-smll-171701112100244.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is UtilityControlRoom-PT-Z4T4N02, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r445-smll-171701112100244
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.3M
-rw-r--r-- 1 mcc users 23K Apr 13 05:45 CTLCardinality.txt
-rw-r--r-- 1 mcc users 154K Apr 13 05:45 CTLCardinality.xml
-rw-r--r-- 1 mcc users 29K Apr 13 05:42 CTLFireability.txt
-rw-r--r-- 1 mcc users 137K Apr 13 05:42 CTLFireability.xml
-rw-r--r-- 1 mcc users 8.0K Apr 23 08:04 LTLCardinality.txt
-rw-r--r-- 1 mcc users 34K Apr 23 08:04 LTLCardinality.xml
-rw-r--r-- 1 mcc users 16K Apr 23 08:04 LTLFireability.txt
-rw-r--r-- 1 mcc users 50K Apr 23 08:04 LTLFireability.xml
-rw-r--r-- 1 mcc users 46K Apr 13 05:52 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 278K Apr 13 05:52 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 74K Apr 13 05:50 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 312K Apr 13 05:50 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.5K Apr 23 08:04 UpperBounds.txt
-rw-r--r-- 1 mcc users 5.2K Apr 23 08:04 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 8 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 65K May 18 16:43 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME UtilityControlRoom-PT-Z4T4N02-LTLFireability-00
FORMULA_NAME UtilityControlRoom-PT-Z4T4N02-LTLFireability-01
FORMULA_NAME UtilityControlRoom-PT-Z4T4N02-LTLFireability-02
FORMULA_NAME UtilityControlRoom-PT-Z4T4N02-LTLFireability-03
FORMULA_NAME UtilityControlRoom-PT-Z4T4N02-LTLFireability-04
FORMULA_NAME UtilityControlRoom-PT-Z4T4N02-LTLFireability-05
FORMULA_NAME UtilityControlRoom-PT-Z4T4N02-LTLFireability-06
FORMULA_NAME UtilityControlRoom-PT-Z4T4N02-LTLFireability-07
FORMULA_NAME UtilityControlRoom-PT-Z4T4N02-LTLFireability-08
FORMULA_NAME UtilityControlRoom-PT-Z4T4N02-LTLFireability-09
FORMULA_NAME UtilityControlRoom-PT-Z4T4N02-LTLFireability-10
FORMULA_NAME UtilityControlRoom-PT-Z4T4N02-LTLFireability-11
FORMULA_NAME UtilityControlRoom-PT-Z4T4N02-LTLFireability-12
FORMULA_NAME UtilityControlRoom-PT-Z4T4N02-LTLFireability-13
FORMULA_NAME UtilityControlRoom-PT-Z4T4N02-LTLFireability-14
FORMULA_NAME UtilityControlRoom-PT-Z4T4N02-LTLFireability-15
=== Now, execution of the tool begins
BK_START 1717119135594
FORMULA UtilityControlRoom-PT-Z4T4N02-LTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T4N02-LTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T4N02-LTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T4N02-LTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T4N02-LTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T4N02-LTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T4N02-LTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T4N02-LTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T4N02-LTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T4N02-LTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T4N02-LTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T4N02-LTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T4N02-LTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T4N02-LTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T4N02-LTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T4N02-LTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[[35mlola[0m] [1mFINAL RESULTS[0m
[[35mlola[0m] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m] [1m[32mUtilityControlRoom-PT-Z4T4N02-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m] [1m[32mUtilityControlRoom-PT-Z4T4N02-LTLFireability-01: LTL true LTL model checker[0m
[[35mlola[0m] [1m[31mUtilityControlRoom-PT-Z4T4N02-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m] [1m[32mUtilityControlRoom-PT-Z4T4N02-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m] [1m[31mUtilityControlRoom-PT-Z4T4N02-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m] [1m[32mUtilityControlRoom-PT-Z4T4N02-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m] [1m[32mUtilityControlRoom-PT-Z4T4N02-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m] [1m[31mUtilityControlRoom-PT-Z4T4N02-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m] [1m[32mUtilityControlRoom-PT-Z4T4N02-LTLFireability-08: F true state space / EG[0m
[[35mlola[0m] [1m[31mUtilityControlRoom-PT-Z4T4N02-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mUtilityControlRoom-PT-Z4T4N02-LTLFireability-10: CONJ false findpath[0m
[[35mlola[0m] [1m[31mUtilityControlRoom-PT-Z4T4N02-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mUtilityControlRoom-PT-Z4T4N02-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mUtilityControlRoom-PT-Z4T4N02-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mUtilityControlRoom-PT-Z4T4N02-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mUtilityControlRoom-PT-Z4T4N02-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m]
[[35mlola[0m] Time elapsed: 3 secs. Pages in use: 2
BK_STOP 1717119138163
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mLTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 52 (type SKEL/SRCH) for 6 UtilityControlRoom-PT-Z4T4N02-LTLFireability-02
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 52 (type SKEL/SRCH) for UtilityControlRoom-PT-Z4T4N02-LTLFireability-02
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 58
[[35mlola[0m][I] fired transitions : 79
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 13 (type EXCL) for 12 UtilityControlRoom-PT-Z4T4N02-LTLFireability-04
[[35mlola[0m][I] time limit : 128 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 13 (type EXCL) for UtilityControlRoom-PT-Z4T4N02-LTLFireability-04
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 19
[[35mlola[0m][I] fired transitions : 19
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 16 (type EXCL) for 15 UtilityControlRoom-PT-Z4T4N02-LTLFireability-05
[[35mlola[0m][I] time limit : 144 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 57 (type EQUN) for 30 UtilityControlRoom-PT-Z4T4N02-LTLFireability-10
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 64 (type EQUN) for 24 UtilityControlRoom-PT-Z4T4N02-LTLFireability-08
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 61 (type FNDP) for 30 UtilityControlRoom-PT-Z4T4N02-LTLFireability-10
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 61 (type FNDP) for UtilityControlRoom-PT-Z4T4N02-LTLFireability-10
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 57 (type EQUN) for UtilityControlRoom-PT-Z4T4N02-LTLFireability-10 (obsolete)
[[35mlola[0m][I] FINISHED task # 64 (type EQUN) for UtilityControlRoom-PT-Z4T4N02-LTLFireability-08
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 57 (type EQUN) for UtilityControlRoom-PT-Z4T4N02-LTLFireability-10
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 16 (type EXCL) for UtilityControlRoom-PT-Z4T4N02-LTLFireability-05
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 37568
[[35mlola[0m][I] fired transitions : 148648
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 50 (type EXCL) for 49 UtilityControlRoom-PT-Z4T4N02-LTLFireability-15
[[35mlola[0m][I] time limit : 276 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 50 (type EXCL) for UtilityControlRoom-PT-Z4T4N02-LTLFireability-15
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 25
[[35mlola[0m][I] fired transitions : 26
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 47 (type EXCL) for 46 UtilityControlRoom-PT-Z4T4N02-LTLFireability-14
[[35mlola[0m][I] time limit : 299 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 47 (type EXCL) for UtilityControlRoom-PT-Z4T4N02-LTLFireability-14
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 34
[[35mlola[0m][I] fired transitions : 35
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 44 (type EXCL) for 43 UtilityControlRoom-PT-Z4T4N02-LTLFireability-13
[[35mlola[0m][I] time limit : 327 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 44 (type EXCL) for UtilityControlRoom-PT-Z4T4N02-LTLFireability-13
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 822
[[35mlola[0m][I] fired transitions : 1495
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 41 (type EXCL) for 40 UtilityControlRoom-PT-Z4T4N02-LTLFireability-12
[[35mlola[0m][I] time limit : 359 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 41 (type EXCL) for UtilityControlRoom-PT-Z4T4N02-LTLFireability-12
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 26640
[[35mlola[0m][I] fired transitions : 68356
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 38 (type EXCL) for 37 UtilityControlRoom-PT-Z4T4N02-LTLFireability-11
[[35mlola[0m][I] time limit : 399 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 38 (type EXCL) for UtilityControlRoom-PT-Z4T4N02-LTLFireability-11
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 16
[[35mlola[0m][I] fired transitions : 16
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 28 (type EXCL) for 27 UtilityControlRoom-PT-Z4T4N02-LTLFireability-09
[[35mlola[0m][I] time limit : 449 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 28 (type EXCL) for UtilityControlRoom-PT-Z4T4N02-LTLFireability-09
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 18
[[35mlola[0m][I] fired transitions : 19
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 19 (type EXCL) for 18 UtilityControlRoom-PT-Z4T4N02-LTLFireability-06
[[35mlola[0m][I] time limit : 514 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 19 (type EXCL) for UtilityControlRoom-PT-Z4T4N02-LTLFireability-06
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 3
[[35mlola[0m][I] fired transitions : 2
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 10 (type EXCL) for 9 UtilityControlRoom-PT-Z4T4N02-LTLFireability-03
[[35mlola[0m][I] time limit : 599 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 10 (type EXCL) for UtilityControlRoom-PT-Z4T4N02-LTLFireability-03
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 7 (type EXCL) for 6 UtilityControlRoom-PT-Z4T4N02-LTLFireability-02
[[35mlola[0m][I] time limit : 719 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 7 (type EXCL) for UtilityControlRoom-PT-Z4T4N02-LTLFireability-02
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 331
[[35mlola[0m][I] fired transitions : 479
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 4 (type EXCL) for 3 UtilityControlRoom-PT-Z4T4N02-LTLFireability-01
[[35mlola[0m][I] time limit : 899 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 4 (type EXCL) for UtilityControlRoom-PT-Z4T4N02-LTLFireability-01
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 1 (type EXCL) for 0 UtilityControlRoom-PT-Z4T4N02-LTLFireability-00
[[35mlola[0m][I] time limit : 1199 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 1 (type EXCL) for UtilityControlRoom-PT-Z4T4N02-LTLFireability-00
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 204801
[[35mlola[0m][I] fired transitions : 908922
[[35mlola[0m][I] time used : 2
[[35mlola[0m][I] memory pages used : 2
[[35mlola[0m][I] LAUNCH task # 59 (type EXCL) for 24 UtilityControlRoom-PT-Z4T4N02-LTLFireability-08
[[35mlola[0m][I] time limit : 1798 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 59 (type EXCL) for UtilityControlRoom-PT-Z4T4N02-LTLFireability-08
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 22 (type EXCL) for 21 UtilityControlRoom-PT-Z4T4N02-LTLFireability-07
[[35mlola[0m][I] time limit : 3597 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 22 (type EXCL) for UtilityControlRoom-PT-Z4T4N02-LTLFireability-07
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 11
[[35mlola[0m][I] fired transitions : 11
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] Portfolio finished: no open formulas
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="UtilityControlRoom-PT-Z4T4N02"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is UtilityControlRoom-PT-Z4T4N02, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r445-smll-171701112100244"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/UtilityControlRoom-PT-Z4T4N02.tgz
mv UtilityControlRoom-PT-Z4T4N02 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;