About the Execution of LoLA for UtilityControlRoom-PT-Z4T3N10
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16207.392 | 753995.00 | 755875.00 | 2228.90 | ?TF?TFFT??FFFF?? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r445-smll-171701112100233.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is UtilityControlRoom-PT-Z4T3N10, examination is CTLCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r445-smll-171701112100233
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 2.5M
-rw-r--r-- 1 mcc users 38K Apr 13 05:20 CTLCardinality.txt
-rw-r--r-- 1 mcc users 177K Apr 13 05:20 CTLCardinality.xml
-rw-r--r-- 1 mcc users 78K Apr 13 05:15 CTLFireability.txt
-rw-r--r-- 1 mcc users 295K Apr 13 05:15 CTLFireability.xml
-rw-r--r-- 1 mcc users 30K Apr 23 08:04 LTLCardinality.txt
-rw-r--r-- 1 mcc users 101K Apr 23 08:04 LTLCardinality.xml
-rw-r--r-- 1 mcc users 43K Apr 23 08:04 LTLFireability.txt
-rw-r--r-- 1 mcc users 129K Apr 23 08:04 LTLFireability.xml
-rw-r--r-- 1 mcc users 110K Apr 13 05:33 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 507K Apr 13 05:33 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 121K Apr 13 05:29 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 475K Apr 13 05:29 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 4.2K Apr 23 08:04 UpperBounds.txt
-rw-r--r-- 1 mcc users 9.0K Apr 23 08:04 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 8 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 319K May 18 16:43 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00
FORMULA_NAME UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01
FORMULA_NAME UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02
FORMULA_NAME UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03
FORMULA_NAME UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04
FORMULA_NAME UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05
FORMULA_NAME UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06
FORMULA_NAME UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07
FORMULA_NAME UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08
FORMULA_NAME UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09
FORMULA_NAME UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10
FORMULA_NAME UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11
FORMULA_NAME UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12
FORMULA_NAME UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13
FORMULA_NAME UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14
FORMULA_NAME UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15
=== Now, execution of the tool begins
BK_START 1717110204336
FORMULA UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1717110958331
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLCardinality.xml[0m
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 4 (type CNST) for 3 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 4 (type CNST) for UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 52 (type SKEL/EQUN) for 0 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 50 (type SKEL/SRCH) for 0 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 50 (type SKEL/SRCH) for UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 20
[[35mlola[0m][I] fired transitions : 21
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 52 (type EQUN) for UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00 (obsolete)
[[35mlola[0m][I] FINISHED task # 52 (type SKEL/EQUN) for UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 7 (type CNST) for 6 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 7 (type CNST) for UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 13 (type CNST) for 12 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 13 (type CNST) for UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 19 (type CNST) for 18 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 19 (type CNST) for UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 16 (type EXCL) for 15 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05
[[35mlola[0m][I] time limit : 256 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 16 (type EXCL) for UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 61 (type EXCL) for 30 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10
[[35mlola[0m][I] time limit : 326 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 55 (type SKEL/FNDP) for 30 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 56 (type SKEL/EQUN) for 30 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 57 (type SKEL/SRCH) for 30 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 57 (type SKEL/SRCH) for UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 4
[[35mlola[0m][I] fired transitions : 3
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] FINISHED task # 61 (type EXCL) for UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 4
[[35mlola[0m][I] fired transitions : 3
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 55 (type FNDP) for UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10 (obsolete)
[[35mlola[0m][W] CANCELED task # 56 (type EQUN) for UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10 (obsolete)
[[35mlola[0m][I] FINISHED task # 55 (type SKEL/FNDP) for UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] FINISHED task # 56 (type SKEL/EQUN) for UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 37 (type EXCL) for 36 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12
[[35mlola[0m][I] time limit : 359 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 37 (type EXCL) for UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 55
[[35mlola[0m][I] fired transitions : 55
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 34 (type EXCL) for 33 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11
[[35mlola[0m][I] time limit : 399 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 34 (type EXCL) for UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 69
[[35mlola[0m][I] fired transitions : 70
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 22 (type EXCL) for 21 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07
[[35mlola[0m][I] time limit : 449 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 22 (type EXCL) for UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 55
[[35mlola[0m][I] fired transitions : 110
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 40 (type EXCL) for 39 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13
[[35mlola[0m][I] time limit : 513 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 40 (type EXCL) for UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 34
[[35mlola[0m][I] fired transitions : 69
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 46 (type EXCL) for 45 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15
[[35mlola[0m][I] time limit : 599 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 65 (type EQUN) for 0 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 65 (type EQUN) for UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00
[[35mlola[0m][I] result : true
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 5/599 4/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 468523 m, 93704 m/sec, 1074986 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 10/599 7/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 936321 m, 93559 m/sec, 2168730 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 15 secs. Pages in use: 7
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 15/599 10/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 1388770 m, 90489 m/sec, 3228451 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 20 secs. Pages in use: 10
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 20/599 13/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 1816121 m, 85470 m/sec, 4286740 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 25 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 25/599 16/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 2258325 m, 88440 m/sec, 5351826 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 30 secs. Pages in use: 16
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 30/599 18/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 2696290 m, 87593 m/sec, 6386068 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 35 secs. Pages in use: 18
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 35/599 21/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 3125802 m, 85902 m/sec, 7421289 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 40 secs. Pages in use: 21
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 40/599 24/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 3564154 m, 87670 m/sec, 8450259 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 45 secs. Pages in use: 24
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 45/599 26/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 3972417 m, 81652 m/sec, 9491163 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 50 secs. Pages in use: 26
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 50/599 29/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 4393265 m, 84169 m/sec, 10541094 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 55 secs. Pages in use: 29
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 55/599 32/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 4818144 m, 84975 m/sec, 11585965 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 60 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 60/599 35/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 5228598 m, 82090 m/sec, 12626582 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 65 secs. Pages in use: 35
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 65/599 37/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 5646589 m, 83598 m/sec, 13648880 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 70 secs. Pages in use: 37
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 70/599 40/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 6057424 m, 82167 m/sec, 14678697 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 75 secs. Pages in use: 40
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 75/599 43/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 6487192 m, 85953 m/sec, 15731901 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 80 secs. Pages in use: 43
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 80/599 46/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 6879551 m, 78471 m/sec, 16760738 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 85 secs. Pages in use: 46
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 85/599 48/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 7273220 m, 78733 m/sec, 17790416 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 90 secs. Pages in use: 48
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 90/599 51/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 7681719 m, 81699 m/sec, 18837490 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 95 secs. Pages in use: 51
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 95/599 54/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 8072081 m, 78072 m/sec, 19851555 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 100 secs. Pages in use: 54
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 100/599 56/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 8457716 m, 77127 m/sec, 20866247 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 105 secs. Pages in use: 56
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 105/599 59/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 8836235 m, 75703 m/sec, 21878504 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 110 secs. Pages in use: 59
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 110/599 61/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 9212965 m, 75346 m/sec, 22873872 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 115 secs. Pages in use: 61
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 115/599 63/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 9590380 m, 75483 m/sec, 23859241 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 120 secs. Pages in use: 63
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 120/599 66/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 9991350 m, 80194 m/sec, 24903051 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 125 secs. Pages in use: 66
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 125/599 68/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 10367464 m, 75222 m/sec, 25887540 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 130 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 130/599 71/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 10742820 m, 75071 m/sec, 26886894 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 135 secs. Pages in use: 71
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 135/599 73/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 11118224 m, 75080 m/sec, 27883326 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 140 secs. Pages in use: 73
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 140/599 76/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 11491212 m, 74597 m/sec, 28871914 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 145 secs. Pages in use: 76
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 145/599 78/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 11853273 m, 72412 m/sec, 29853299 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 150 secs. Pages in use: 78
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 150/599 80/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 12212492 m, 71843 m/sec, 30821056 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 155 secs. Pages in use: 80
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 155/599 83/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 12585699 m, 74641 m/sec, 31818209 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 160 secs. Pages in use: 83
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 160/599 85/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 12963842 m, 75628 m/sec, 32821753 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 165 secs. Pages in use: 85
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 165/599 88/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 13328226 m, 72876 m/sec, 33798324 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 170 secs. Pages in use: 88
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 170/599 90/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 13691785 m, 72711 m/sec, 34771560 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 175 secs. Pages in use: 90
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 175/599 93/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 14064095 m, 74462 m/sec, 35758267 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 180 secs. Pages in use: 93
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 180/599 95/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 14421802 m, 71541 m/sec, 36721912 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 185 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 185/599 97/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 14788086 m, 73256 m/sec, 37701329 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 190 secs. Pages in use: 97
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 190/599 100/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 15148529 m, 72088 m/sec, 38663718 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 195 secs. Pages in use: 100
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 195/599 102/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 15511191 m, 72532 m/sec, 39631793 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 200 secs. Pages in use: 102
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 200/599 104/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 15878011 m, 73364 m/sec, 40605220 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 205 secs. Pages in use: 104
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 205/599 107/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 16234164 m, 71230 m/sec, 41571263 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 210 secs. Pages in use: 107
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 210/599 109/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 16577804 m, 68728 m/sec, 42504066 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 215 secs. Pages in use: 109
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 215/599 111/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 16926823 m, 69803 m/sec, 43463170 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 220 secs. Pages in use: 111
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 220/599 114/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 17278092 m, 70253 m/sec, 44417230 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 225 secs. Pages in use: 114
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 225/599 116/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 17634136 m, 71208 m/sec, 45384160 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 230 secs. Pages in use: 116
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 230/599 118/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 17999888 m, 73150 m/sec, 46335322 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 235 secs. Pages in use: 118
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 235/599 120/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 18349570 m, 69936 m/sec, 47272551 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 240 secs. Pages in use: 120
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 240/599 123/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 18694167 m, 68919 m/sec, 48213145 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 245 secs. Pages in use: 123
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 245/599 125/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 19049212 m, 71009 m/sec, 49171212 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 250 secs. Pages in use: 125
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 250/599 127/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 19407793 m, 71716 m/sec, 50137631 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 255 secs. Pages in use: 127
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 255/599 130/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 19751950 m, 68831 m/sec, 51070984 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 260 secs. Pages in use: 130
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 260/599 132/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 20099847 m, 69579 m/sec, 52023715 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 265 secs. Pages in use: 132
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 265/599 134/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 20439862 m, 68003 m/sec, 52962293 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 270 secs. Pages in use: 134
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 270/599 136/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 20794994 m, 71026 m/sec, 53928905 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 275 secs. Pages in use: 136
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 275/599 139/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 21139439 m, 68889 m/sec, 54873874 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 280 secs. Pages in use: 139
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 280/599 141/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 21488595 m, 69831 m/sec, 55805871 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 285 secs. Pages in use: 141
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 285/599 143/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 21838969 m, 70074 m/sec, 56762772 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 290 secs. Pages in use: 143
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 290/599 145/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 22174171 m, 67040 m/sec, 57692685 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 295 secs. Pages in use: 145
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 295/599 147/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 22512452 m, 67656 m/sec, 58625892 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 300 secs. Pages in use: 147
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 300/599 150/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 22851032 m, 67716 m/sec, 59556874 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 305 secs. Pages in use: 150
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 305/599 152/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 23186275 m, 67048 m/sec, 60479139 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 310 secs. Pages in use: 152
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 310/599 154/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 23539188 m, 70582 m/sec, 61449405 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 315 secs. Pages in use: 154
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 315/599 156/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 23895684 m, 71299 m/sec, 62431391 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 320 secs. Pages in use: 156
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 320/599 159/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 24250870 m, 71037 m/sec, 63411251 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 325 secs. Pages in use: 159
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 325/599 161/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 24598475 m, 69521 m/sec, 64388838 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 330 secs. Pages in use: 161
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 330/599 163/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 24949545 m, 70214 m/sec, 65352661 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 335 secs. Pages in use: 163
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 335/599 166/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 25300998 m, 70290 m/sec, 66323324 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 340 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 340/599 168/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 25652836 m, 70367 m/sec, 67274832 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 345 secs. Pages in use: 168
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 345/599 170/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 26002331 m, 69899 m/sec, 68242152 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 350 secs. Pages in use: 170
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 350/599 172/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 26346632 m, 68860 m/sec, 69206091 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 355 secs. Pages in use: 172
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 355/599 175/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 26693819 m, 69437 m/sec, 70181776 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 360 secs. Pages in use: 175
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 360/599 177/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 27039573 m, 69150 m/sec, 71147875 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 365 secs. Pages in use: 177
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 365/599 179/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 27385742 m, 69233 m/sec, 72110818 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 370 secs. Pages in use: 179
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 370/599 181/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 27727448 m, 68341 m/sec, 73070282 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 375 secs. Pages in use: 181
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 375/599 183/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 28063857 m, 67281 m/sec, 74007812 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 380 secs. Pages in use: 183
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 380/599 186/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 28384018 m, 64032 m/sec, 74904093 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 385 secs. Pages in use: 186
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 385/599 188/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 28709602 m, 65116 m/sec, 75804033 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 390 secs. Pages in use: 188
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 390/599 190/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 29036317 m, 65343 m/sec, 76719748 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 395 secs. Pages in use: 190
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 395/599 192/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 29360245 m, 64785 m/sec, 77619987 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 400 secs. Pages in use: 192
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 400/599 194/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 29685016 m, 64954 m/sec, 78521473 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 405 secs. Pages in use: 194
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 405/599 196/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 30014468 m, 65890 m/sec, 79447047 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 410 secs. Pages in use: 196
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 410/599 198/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 30347581 m, 66622 m/sec, 80386627 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 415 secs. Pages in use: 198
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 415/599 200/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 30681227 m, 66729 m/sec, 81310882 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 420 secs. Pages in use: 200
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 420/599 203/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 31015144 m, 66783 m/sec, 82239785 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 425 secs. Pages in use: 203
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 425/599 205/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 31337263 m, 64423 m/sec, 83145626 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 430 secs. Pages in use: 205
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 430/599 207/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 31665922 m, 65731 m/sec, 84057610 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 435 secs. Pages in use: 207
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 435/599 209/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 31994427 m, 65701 m/sec, 84974527 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 440 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 440/599 211/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 32317353 m, 64585 m/sec, 85864811 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 445 secs. Pages in use: 211
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 445/599 213/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 32644456 m, 65420 m/sec, 86774192 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 450 secs. Pages in use: 213
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 450/599 215/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 32969310 m, 64970 m/sec, 87680208 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 455 secs. Pages in use: 215
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 455/599 217/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 33295710 m, 65280 m/sec, 88596728 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 460 secs. Pages in use: 217
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 460/599 220/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 33616624 m, 64182 m/sec, 89502277 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 465 secs. Pages in use: 220
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 465/599 222/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 33933128 m, 63300 m/sec, 90398114 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 470 secs. Pages in use: 222
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 470/599 224/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 34254997 m, 64373 m/sec, 91306265 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 475 secs. Pages in use: 224
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 475/599 226/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 34571876 m, 63375 m/sec, 92212439 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 480 secs. Pages in use: 226
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 480/599 228/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 34887842 m, 63193 m/sec, 93106151 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 485 secs. Pages in use: 228
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 485/599 230/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 35205491 m, 63529 m/sec, 93998642 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 490 secs. Pages in use: 230
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 490/599 232/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 35515723 m, 62046 m/sec, 94886407 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 495 secs. Pages in use: 232
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 495/599 234/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 35842121 m, 65279 m/sec, 95776930 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 500 secs. Pages in use: 234
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 500/599 236/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 36167021 m, 64980 m/sec, 96691638 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 505 secs. Pages in use: 236
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 505/599 238/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 36499758 m, 66547 m/sec, 97625635 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 510 secs. Pages in use: 238
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 510/599 240/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 36829761 m, 66000 m/sec, 98552739 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 515 secs. Pages in use: 240
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 515/599 243/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 37155805 m, 65208 m/sec, 99483675 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 520 secs. Pages in use: 243
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 520/599 245/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 37481088 m, 65056 m/sec, 100404115 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 525 secs. Pages in use: 245
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 525/599 247/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 37811326 m, 66047 m/sec, 101330253 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 530 secs. Pages in use: 247
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 530/599 249/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 38143972 m, 66529 m/sec, 102280353 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 535 secs. Pages in use: 249
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 535/599 251/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 38472529 m, 65711 m/sec, 103220666 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 540 secs. Pages in use: 251
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 540/599 253/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 38799176 m, 65329 m/sec, 104146468 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 545 secs. Pages in use: 253
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 545/599 255/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 39126897 m, 65544 m/sec, 105084951 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 550 secs. Pages in use: 255
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 550/599 257/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 39436704 m, 61961 m/sec, 105977273 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 555 secs. Pages in use: 257
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 555/599 260/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 39752738 m, 63206 m/sec, 106876883 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 560 secs. Pages in use: 260
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 560/599 262/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 40061421 m, 61736 m/sec, 107759830 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 565 secs. Pages in use: 262
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 565/599 263/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 40371744 m, 62064 m/sec, 108635750 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 570 secs. Pages in use: 263
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 570/599 265/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 40678875 m, 61426 m/sec, 109518524 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 575 secs. Pages in use: 265
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 575/599 267/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 40991849 m, 62594 m/sec, 110403562 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 580 secs. Pages in use: 267
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 580/599 270/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 41305154 m, 62661 m/sec, 111295593 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 585 secs. Pages in use: 270
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 585/599 272/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 41620690 m, 63107 m/sec, 112202229 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 590 secs. Pages in use: 272
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 590/599 274/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 41940762 m, 64014 m/sec, 113123268 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 595 secs. Pages in use: 274
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 595/599 276/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 42264424 m, 64732 m/sec, 114052508 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 600 secs. Pages in use: 276
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 46 (type EXCL) for UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 605 secs. Pages in use: 278
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 63 (type EXCL) for 0 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00
[[35mlola[0m][I] time limit : 599 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 46 (type EXCL) for 45 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15
[[35mlola[0m][I] time limit : 2995 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 63 (type EXCL) for UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 6
[[35mlola[0m][I] fired transitions : 5
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 5/599 4/5 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 507607 m, -8351363 m/sec, 1172453 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 610 secs. Pages in use: 282
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 46 (type EXCL) for UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 615 secs. Pages in use: 283
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 25 (type EXCL) for 24 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08
[[35mlola[0m][I] time limit : 746 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 5/746 6/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08 769298 m, 153859 m/sec, 1297206 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 620 secs. Pages in use: 284
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 10/746 12/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08 1466215 m, 139383 m/sec, 2538937 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 625 secs. Pages in use: 290
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 15/746 17/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08 2140443 m, 134845 m/sec, 3757901 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 630 secs. Pages in use: 295
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 20/746 21/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08 2800705 m, 132052 m/sec, 4964668 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 635 secs. Pages in use: 299
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 25/746 26/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08 3439032 m, 127665 m/sec, 6154239 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 640 secs. Pages in use: 304
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 30/746 31/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08 4070968 m, 126387 m/sec, 7330640 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 645 secs. Pages in use: 309
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 35/746 35/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08 4690426 m, 123891 m/sec, 8498128 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 650 secs. Pages in use: 313
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 40/746 40/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08 5303476 m, 122610 m/sec, 9655263 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 655 secs. Pages in use: 318
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 45/746 44/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08 5905848 m, 120474 m/sec, 10801176 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 660 secs. Pages in use: 322
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 50/746 48/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08 6501757 m, 119181 m/sec, 11936109 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 665 secs. Pages in use: 326
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 55/746 52/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08 7094823 m, 118613 m/sec, 13072573 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 670 secs. Pages in use: 330
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 60/746 56/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08 7682253 m, 117486 m/sec, 14197909 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 675 secs. Pages in use: 334
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 65/746 61/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08 8266283 m, 116806 m/sec, 15326832 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 680 secs. Pages in use: 339
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 70/746 65/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08 8850491 m, 116841 m/sec, 16455328 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 685 secs. Pages in use: 343
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 75/746 69/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08 9433287 m, 116559 m/sec, 17581127 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 690 secs. Pages in use: 347
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 80/746 73/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08 10012090 m, 115760 m/sec, 18702699 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 695 secs. Pages in use: 351
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 85/746 77/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08 10578785 m, 113339 m/sec, 19806157 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 700 secs. Pages in use: 355
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 90/746 81/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08 11146703 m, 113583 m/sec, 20916165 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 705 secs. Pages in use: 359
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 95/746 85/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08 11716781 m, 114015 m/sec, 22028390 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 710 secs. Pages in use: 363
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 100/746 89/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08 12284014 m, 113446 m/sec, 23131568 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 715 secs. Pages in use: 367
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 105/746 93/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08 12853124 m, 113822 m/sec, 24247410 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 720 secs. Pages in use: 371
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 110/746 97/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08 13414994 m, 112374 m/sec, 25348688 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 725 secs. Pages in use: 375
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 115/746 101/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08 13975963 m, 112193 m/sec, 26444893 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 730 secs. Pages in use: 379
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 120/746 105/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08 14531359 m, 111079 m/sec, 27540396 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 735 secs. Pages in use: 383
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 125/746 109/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08 15080133 m, 109754 m/sec, 28615638 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 740 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-00: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-10: AG false state space[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 130/746 112/2000 UtilityControlRoom-PT-Z4T3N10-CTLCardinality-2024-08 15569719 m, 97917 m/sec, 29584471 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 745 secs. Pages in use: 390
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
/home/mcc/BenchKit/BenchKit_head.sh: line 23: 409 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="UtilityControlRoom-PT-Z4T3N10"
export BK_EXAMINATION="CTLCardinality"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is UtilityControlRoom-PT-Z4T3N10, examination is CTLCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r445-smll-171701112100233"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/UtilityControlRoom-PT-Z4T3N10.tgz
mv UtilityControlRoom-PT-Z4T3N10 execution
cd execution
if [ "CTLCardinality" = "ReachabilityDeadlock" ] || [ "CTLCardinality" = "UpperBounds" ] || [ "CTLCardinality" = "QuasiLiveness" ] || [ "CTLCardinality" = "StableMarking" ] || [ "CTLCardinality" = "Liveness" ] || [ "CTLCardinality" = "OneSafe" ] || [ "CTLCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLCardinality" = "ReachabilityDeadlock" ] || [ "CTLCardinality" = "QuasiLiveness" ] || [ "CTLCardinality" = "StableMarking" ] || [ "CTLCardinality" = "Liveness" ] || [ "CTLCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;